FreeBSD/Linux Kernel Cross Reference
sys/i386/cpufreq/est.c
1 /*-
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/6.3/sys/i386/cpufreq/est.c 159055 2006-05-29 22:40:03Z njl $");
30
31 #include <sys/param.h>
32 #include <sys/bus.h>
33 #include <sys/cpu.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/smp.h>
38 #include <sys/systm.h>
39
40 #include "cpufreq_if.h"
41 #include <machine/md_var.h>
42
43 #include <contrib/dev/acpica/acpi.h>
44 #include <dev/acpica/acpivar.h>
45 #include "acpi_if.h"
46
47 /* Status/control registers (from the IA-32 System Programming Guide). */
48 #define MSR_PERF_STATUS 0x198
49 #define MSR_PERF_CTL 0x199
50
51 /* Register and bit for enabling SpeedStep. */
52 #define MSR_MISC_ENABLE 0x1a0
53 #define MSR_SS_ENABLE (1<<16)
54
55 /* Frequency and MSR control values. */
56 typedef struct {
57 uint16_t freq;
58 uint16_t volts;
59 uint16_t id16;
60 int power;
61 } freq_info;
62
63 /* Identifying characteristics of a processor and supported frequencies. */
64 typedef struct {
65 const char *vendor;
66 uint32_t id32;
67 freq_info *freqtab;
68 } cpu_info;
69
70 struct est_softc {
71 device_t dev;
72 int acpi_settings;
73 freq_info *freq_list;
74 };
75
76 /* Convert MHz and mV into IDs for passing to the MSR. */
77 #define ID16(MHz, mV, bus_clk) \
78 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
79 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
80 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
81
82 /* Format for storing IDs in our table. */
83 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
84 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
85 #define FREQ_INFO(MHz, mV, bus_clk) \
86 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
87 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
88 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
89 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
90 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
91
92 const char intel_id[] = "GenuineIntel";
93 const char centaur_id[] = "CentaurHauls";
94
95 /* Default bus clock value for Centrino processors. */
96 #define INTEL_BUS_CLK 100
97
98 /* XXX Update this if new CPUs have more settings. */
99 #define EST_MAX_SETTINGS 10
100 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
101
102 /* Estimate in microseconds of latency for performing a transition. */
103 #define EST_TRANS_LAT 10
104
105 /*
106 * Frequency (MHz) and voltage (mV) settings. Data from the
107 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
108 *
109 * Dothan processors have multiple VID#s with different settings for
110 * each VID#. Since we can't uniquely identify this info
111 * without undisclosed methods from Intel, we can't support newer
112 * processors with this table method. If ACPI Px states are supported,
113 * we get info from them.
114 */
115 static freq_info PM17_130[] = {
116 /* 130nm 1.70GHz Pentium M */
117 FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
118 FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
119 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
120 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
121 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
122 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
123 FREQ_INFO( 0, 0, 1),
124 };
125 static freq_info PM16_130[] = {
126 /* 130nm 1.60GHz Pentium M */
127 FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
128 FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
129 FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
130 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
131 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
132 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
133 FREQ_INFO( 0, 0, 1),
134 };
135 static freq_info PM15_130[] = {
136 /* 130nm 1.50GHz Pentium M */
137 FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
138 FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
139 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
140 FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
141 FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
142 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
143 FREQ_INFO( 0, 0, 1),
144 };
145 static freq_info PM14_130[] = {
146 /* 130nm 1.40GHz Pentium M */
147 FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
148 FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
149 FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
150 FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
151 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
152 FREQ_INFO( 0, 0, 1),
153 };
154 static freq_info PM13_130[] = {
155 /* 130nm 1.30GHz Pentium M */
156 FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
157 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
158 FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
159 FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
160 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
161 FREQ_INFO( 0, 0, 1),
162 };
163 static freq_info PM13_LV_130[] = {
164 /* 130nm 1.30GHz Low Voltage Pentium M */
165 FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
166 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
167 FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
168 FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
169 FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
170 FREQ_INFO( 800, 988, INTEL_BUS_CLK),
171 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
172 FREQ_INFO( 0, 0, 1),
173 };
174 static freq_info PM12_LV_130[] = {
175 /* 130 nm 1.20GHz Low Voltage Pentium M */
176 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
177 FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
178 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
179 FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
180 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
181 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
182 FREQ_INFO( 0, 0, 1),
183 };
184 static freq_info PM11_LV_130[] = {
185 /* 130 nm 1.10GHz Low Voltage Pentium M */
186 FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
187 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
188 FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
189 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
190 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
191 FREQ_INFO( 0, 0, 1),
192 };
193 static freq_info PM11_ULV_130[] = {
194 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
195 FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
196 FREQ_INFO(1000, 988, INTEL_BUS_CLK),
197 FREQ_INFO( 900, 972, INTEL_BUS_CLK),
198 FREQ_INFO( 800, 956, INTEL_BUS_CLK),
199 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
200 FREQ_INFO( 0, 0, 1),
201 };
202 static freq_info PM10_ULV_130[] = {
203 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
204 FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
205 FREQ_INFO( 900, 988, INTEL_BUS_CLK),
206 FREQ_INFO( 800, 972, INTEL_BUS_CLK),
207 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
208 FREQ_INFO( 0, 0, 1),
209 };
210
211 /*
212 * Data from "Intel Pentium M Processor on 90nm Process with
213 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
214 */
215 static freq_info PM_765A_90[] = {
216 /* 90 nm 2.10GHz Pentium M, VID #A */
217 FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
218 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
219 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
220 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
221 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
222 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
223 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
224 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
225 FREQ_INFO( 0, 0, 1),
226 };
227 static freq_info PM_765B_90[] = {
228 /* 90 nm 2.10GHz Pentium M, VID #B */
229 FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
230 FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
231 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
232 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
233 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
234 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
235 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
236 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
237 FREQ_INFO( 0, 0, 1),
238 };
239 static freq_info PM_765C_90[] = {
240 /* 90 nm 2.10GHz Pentium M, VID #C */
241 FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
242 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
243 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
244 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
245 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
246 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
247 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
248 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
249 FREQ_INFO( 0, 0, 1),
250 };
251 static freq_info PM_765E_90[] = {
252 /* 90 nm 2.10GHz Pentium M, VID #E */
253 FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
254 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
255 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
256 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
257 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
258 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
259 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
260 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
261 FREQ_INFO( 0, 0, 1),
262 };
263 static freq_info PM_755A_90[] = {
264 /* 90 nm 2.00GHz Pentium M, VID #A */
265 FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
266 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
267 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
268 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
269 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
270 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
271 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
272 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
273 FREQ_INFO( 0, 0, 1),
274 };
275 static freq_info PM_755B_90[] = {
276 /* 90 nm 2.00GHz Pentium M, VID #B */
277 FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
278 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
279 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
280 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
281 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
282 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
283 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
284 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
285 FREQ_INFO( 0, 0, 1),
286 };
287 static freq_info PM_755C_90[] = {
288 /* 90 nm 2.00GHz Pentium M, VID #C */
289 FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
290 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
291 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
292 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
293 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
294 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
295 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
296 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
297 FREQ_INFO( 0, 0, 1),
298 };
299 static freq_info PM_755D_90[] = {
300 /* 90 nm 2.00GHz Pentium M, VID #D */
301 FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
302 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
303 FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
304 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
305 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
306 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
307 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
308 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
309 FREQ_INFO( 0, 0, 1),
310 };
311 static freq_info PM_745A_90[] = {
312 /* 90 nm 1.80GHz Pentium M, VID #A */
313 FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
314 FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
315 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
316 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
317 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
318 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
319 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
320 FREQ_INFO( 0, 0, 1),
321 };
322 static freq_info PM_745B_90[] = {
323 /* 90 nm 1.80GHz Pentium M, VID #B */
324 FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
325 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
326 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
327 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
328 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
329 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
330 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
331 FREQ_INFO( 0, 0, 1),
332 };
333 static freq_info PM_745C_90[] = {
334 /* 90 nm 1.80GHz Pentium M, VID #C */
335 FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
336 FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
337 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
338 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
339 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
340 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
341 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
342 FREQ_INFO( 0, 0, 1),
343 };
344 static freq_info PM_745D_90[] = {
345 /* 90 nm 1.80GHz Pentium M, VID #D */
346 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
347 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
348 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
349 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
350 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
351 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
352 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
353 FREQ_INFO( 0, 0, 1),
354 };
355 static freq_info PM_735A_90[] = {
356 /* 90 nm 1.70GHz Pentium M, VID #A */
357 FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
358 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
359 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
360 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
361 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
362 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
363 FREQ_INFO( 0, 0, 1),
364 };
365 static freq_info PM_735B_90[] = {
366 /* 90 nm 1.70GHz Pentium M, VID #B */
367 FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
368 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
369 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
370 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
371 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
372 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
373 FREQ_INFO( 0, 0, 1),
374 };
375 static freq_info PM_735C_90[] = {
376 /* 90 nm 1.70GHz Pentium M, VID #C */
377 FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
378 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
379 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
380 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
381 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
382 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
383 FREQ_INFO( 0, 0, 1),
384 };
385 static freq_info PM_735D_90[] = {
386 /* 90 nm 1.70GHz Pentium M, VID #D */
387 FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
388 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
389 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
390 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
391 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
392 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
393 FREQ_INFO( 0, 0, 1),
394 };
395 static freq_info PM_725A_90[] = {
396 /* 90 nm 1.60GHz Pentium M, VID #A */
397 FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
398 FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
399 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
400 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
401 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
402 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
403 FREQ_INFO( 0, 0, 1),
404 };
405 static freq_info PM_725B_90[] = {
406 /* 90 nm 1.60GHz Pentium M, VID #B */
407 FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
408 FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
409 FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
410 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
411 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
412 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
413 FREQ_INFO( 0, 0, 1),
414 };
415 static freq_info PM_725C_90[] = {
416 /* 90 nm 1.60GHz Pentium M, VID #C */
417 FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
418 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
419 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
420 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
421 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
422 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
423 FREQ_INFO( 0, 0, 1),
424 };
425 static freq_info PM_725D_90[] = {
426 /* 90 nm 1.60GHz Pentium M, VID #D */
427 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
428 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
429 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
430 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
431 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
432 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
433 FREQ_INFO( 0, 0, 1),
434 };
435 static freq_info PM_715A_90[] = {
436 /* 90 nm 1.50GHz Pentium M, VID #A */
437 FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
438 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
439 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
440 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
441 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
442 FREQ_INFO( 0, 0, 1),
443 };
444 static freq_info PM_715B_90[] = {
445 /* 90 nm 1.50GHz Pentium M, VID #B */
446 FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
447 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
448 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
449 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
450 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
451 FREQ_INFO( 0, 0, 1),
452 };
453 static freq_info PM_715C_90[] = {
454 /* 90 nm 1.50GHz Pentium M, VID #C */
455 FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
456 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
457 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
458 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
459 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
460 FREQ_INFO( 0, 0, 1),
461 };
462 static freq_info PM_715D_90[] = {
463 /* 90 nm 1.50GHz Pentium M, VID #D */
464 FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
465 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
466 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
467 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
468 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
469 FREQ_INFO( 0, 0, 1),
470 };
471 static freq_info PM_778_90[] = {
472 /* 90 nm 1.60GHz Low Voltage Pentium M */
473 FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
474 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
475 FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
476 FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
477 FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
478 FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
479 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
480 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
481 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
482 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
483 FREQ_INFO( 0, 0, 1),
484 };
485 static freq_info PM_758_90[] = {
486 /* 90 nm 1.50GHz Low Voltage Pentium M */
487 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
488 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
489 FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
490 FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
491 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
492 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
493 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
494 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
495 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
496 FREQ_INFO( 0, 0, 1),
497 };
498 static freq_info PM_738_90[] = {
499 /* 90 nm 1.40GHz Low Voltage Pentium M */
500 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
501 FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
502 FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
503 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
504 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
505 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
506 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
507 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
508 FREQ_INFO( 0, 0, 1),
509 };
510 static freq_info PM_773G_90[] = {
511 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
512 FREQ_INFO(1300, 956, INTEL_BUS_CLK),
513 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
514 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
515 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
516 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
517 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
518 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
519 };
520 static freq_info PM_773H_90[] = {
521 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
522 FREQ_INFO(1300, 940, INTEL_BUS_CLK),
523 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
524 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
525 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
526 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
527 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
528 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
529 };
530 static freq_info PM_773I_90[] = {
531 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
532 FREQ_INFO(1300, 924, INTEL_BUS_CLK),
533 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
534 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
535 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
536 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
537 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
538 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
539 };
540 static freq_info PM_773J_90[] = {
541 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
542 FREQ_INFO(1300, 908, INTEL_BUS_CLK),
543 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
544 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
545 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
546 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
547 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
548 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
549 };
550 static freq_info PM_773K_90[] = {
551 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
552 FREQ_INFO(1300, 892, INTEL_BUS_CLK),
553 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
554 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
555 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
556 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
557 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
558 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
559 };
560 static freq_info PM_773L_90[] = {
561 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
562 FREQ_INFO(1300, 876, INTEL_BUS_CLK),
563 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
564 FREQ_INFO(1100, 860, INTEL_BUS_CLK),
565 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
566 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
567 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
568 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
569 };
570 static freq_info PM_753G_90[] = {
571 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
572 FREQ_INFO(1200, 956, INTEL_BUS_CLK),
573 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
574 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
575 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
576 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
577 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
578 };
579 static freq_info PM_753H_90[] = {
580 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
581 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
582 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
583 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
584 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
585 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
586 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
587 };
588 static freq_info PM_753I_90[] = {
589 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
590 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
591 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
592 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
593 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
594 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
595 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
596 };
597 static freq_info PM_753J_90[] = {
598 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
599 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
600 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
601 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
602 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
603 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
604 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
605 };
606 static freq_info PM_753K_90[] = {
607 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
608 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
609 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
610 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
611 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
612 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
613 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
614 };
615 static freq_info PM_753L_90[] = {
616 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
617 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
618 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
619 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
620 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
621 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
622 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
623 };
624
625 static freq_info PM_733JG_90[] = {
626 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
627 FREQ_INFO(1100, 956, INTEL_BUS_CLK),
628 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
629 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
630 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
631 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
632 };
633 static freq_info PM_733JH_90[] = {
634 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
635 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
636 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
637 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
638 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
639 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
640 };
641 static freq_info PM_733JI_90[] = {
642 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
643 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
644 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
645 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
646 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
647 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
648 };
649 static freq_info PM_733JJ_90[] = {
650 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
651 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
652 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
653 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
654 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
655 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
656 };
657 static freq_info PM_733JK_90[] = {
658 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
659 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
660 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
661 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
662 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
663 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
664 };
665 static freq_info PM_733JL_90[] = {
666 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
667 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
668 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
669 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
670 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
671 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
672 };
673 static freq_info PM_733_90[] = {
674 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
675 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
676 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
677 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
678 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
679 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
680 FREQ_INFO( 0, 0, 1),
681 };
682 static freq_info PM_723_90[] = {
683 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
684 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
685 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
686 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
687 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
688 FREQ_INFO( 0, 0, 1),
689 };
690
691 /*
692 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
693 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
694 */
695 static freq_info C7M_795[] = {
696 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
697 FREQ_INFO_PWR(2000, 1148, 133, 20000),
698 FREQ_INFO_PWR(1867, 1132, 133, 18000),
699 FREQ_INFO_PWR(1600, 1100, 133, 15000),
700 FREQ_INFO_PWR(1467, 1052, 133, 13000),
701 FREQ_INFO_PWR(1200, 1004, 133, 10000),
702 FREQ_INFO_PWR( 800, 844, 133, 7000),
703 FREQ_INFO_PWR( 667, 844, 133, 6000),
704 FREQ_INFO_PWR( 533, 844, 133, 5000),
705 FREQ_INFO(0, 0, 1),
706 };
707 static freq_info C7M_785[] = {
708 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
709 FREQ_INFO_PWR(1867, 1148, 133, 18000),
710 FREQ_INFO_PWR(1600, 1100, 133, 15000),
711 FREQ_INFO_PWR(1467, 1052, 133, 13000),
712 FREQ_INFO_PWR(1200, 1004, 133, 10000),
713 FREQ_INFO_PWR( 800, 844, 133, 7000),
714 FREQ_INFO_PWR( 667, 844, 133, 6000),
715 FREQ_INFO_PWR( 533, 844, 133, 5000),
716 FREQ_INFO(0, 0, 1),
717 };
718 static freq_info C7M_765[] = {
719 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
720 FREQ_INFO_PWR(1600, 1084, 133, 15000),
721 FREQ_INFO_PWR(1467, 1052, 133, 13000),
722 FREQ_INFO_PWR(1200, 1004, 133, 10000),
723 FREQ_INFO_PWR( 800, 844, 133, 7000),
724 FREQ_INFO_PWR( 667, 844, 133, 6000),
725 FREQ_INFO_PWR( 533, 844, 133, 5000),
726 FREQ_INFO(0, 0, 1),
727 };
728
729 static freq_info C7M_794[] = {
730 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
731 FREQ_INFO_PWR(2000, 1148, 100, 20000),
732 FREQ_INFO_PWR(1800, 1132, 100, 18000),
733 FREQ_INFO_PWR(1600, 1100, 100, 15000),
734 FREQ_INFO_PWR(1400, 1052, 100, 13000),
735 FREQ_INFO_PWR(1000, 1004, 100, 10000),
736 FREQ_INFO_PWR( 800, 844, 100, 7000),
737 FREQ_INFO_PWR( 600, 844, 100, 6000),
738 FREQ_INFO_PWR( 400, 844, 100, 5000),
739 FREQ_INFO(0, 0, 1),
740 };
741 static freq_info C7M_784[] = {
742 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
743 FREQ_INFO_PWR(1800, 1148, 100, 18000),
744 FREQ_INFO_PWR(1600, 1100, 100, 15000),
745 FREQ_INFO_PWR(1400, 1052, 100, 13000),
746 FREQ_INFO_PWR(1000, 1004, 100, 10000),
747 FREQ_INFO_PWR( 800, 844, 100, 7000),
748 FREQ_INFO_PWR( 600, 844, 100, 6000),
749 FREQ_INFO_PWR( 400, 844, 100, 5000),
750 FREQ_INFO(0, 0, 1),
751 };
752 static freq_info C7M_764[] = {
753 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
754 FREQ_INFO_PWR(1600, 1084, 100, 15000),
755 FREQ_INFO_PWR(1400, 1052, 100, 13000),
756 FREQ_INFO_PWR(1000, 1004, 100, 10000),
757 FREQ_INFO_PWR( 800, 844, 100, 7000),
758 FREQ_INFO_PWR( 600, 844, 100, 6000),
759 FREQ_INFO_PWR( 400, 844, 100, 5000),
760 FREQ_INFO(0, 0, 1),
761 };
762 static freq_info C7M_754[] = {
763 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
764 FREQ_INFO_PWR(1500, 1004, 100, 12000),
765 FREQ_INFO_PWR(1400, 988, 100, 11000),
766 FREQ_INFO_PWR(1000, 940, 100, 9000),
767 FREQ_INFO_PWR( 800, 844, 100, 7000),
768 FREQ_INFO_PWR( 600, 844, 100, 6000),
769 FREQ_INFO_PWR( 400, 844, 100, 5000),
770 FREQ_INFO(0, 0, 1),
771 };
772 static freq_info C7M_771[] = {
773 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
774 FREQ_INFO_PWR(1200, 860, 100, 7000),
775 FREQ_INFO_PWR(1000, 860, 100, 6000),
776 FREQ_INFO_PWR( 800, 844, 100, 5500),
777 FREQ_INFO_PWR( 600, 844, 100, 5000),
778 FREQ_INFO_PWR( 400, 844, 100, 4000),
779 FREQ_INFO(0, 0, 1),
780 };
781
782 static freq_info C7M_775_ULV[] = {
783 /* 1.50GHz Centaur C7-M ULV */
784 FREQ_INFO_PWR(1500, 956, 100, 7500),
785 FREQ_INFO_PWR(1400, 940, 100, 6000),
786 FREQ_INFO_PWR(1000, 860, 100, 5000),
787 FREQ_INFO_PWR( 800, 828, 100, 2800),
788 FREQ_INFO_PWR( 600, 796, 100, 2500),
789 FREQ_INFO_PWR( 400, 796, 100, 2000),
790 FREQ_INFO(0, 0, 1),
791 };
792 static freq_info C7M_772_ULV[] = {
793 /* 1.20GHz Centaur C7-M ULV */
794 FREQ_INFO_PWR(1200, 844, 100, 5000),
795 FREQ_INFO_PWR(1000, 844, 100, 4000),
796 FREQ_INFO_PWR( 800, 828, 100, 2800),
797 FREQ_INFO_PWR( 600, 796, 100, 2500),
798 FREQ_INFO_PWR( 400, 796, 100, 2000),
799 FREQ_INFO(0, 0, 1),
800 };
801 static freq_info C7M_779_ULV[] = {
802 /* 1.00GHz Centaur C7-M ULV */
803 FREQ_INFO_PWR(1000, 796, 100, 3500),
804 FREQ_INFO_PWR( 800, 796, 100, 2800),
805 FREQ_INFO_PWR( 600, 796, 100, 2500),
806 FREQ_INFO_PWR( 400, 796, 100, 2000),
807 FREQ_INFO(0, 0, 1),
808 };
809 static freq_info C7M_770_ULV[] = {
810 /* 1.00GHz Centaur C7-M ULV */
811 FREQ_INFO_PWR(1000, 844, 100, 5000),
812 FREQ_INFO_PWR( 800, 796, 100, 2800),
813 FREQ_INFO_PWR( 600, 796, 100, 2500),
814 FREQ_INFO_PWR( 400, 796, 100, 2000),
815 FREQ_INFO(0, 0, 1),
816 };
817
818 static cpu_info ESTprocs[] = {
819 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
820 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
821 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
822 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
823 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
824 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
825 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
826 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
827 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
828 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
829 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
830 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
831 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
832 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
833 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
834 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
835 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
836 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
837 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
838 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
839 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
840 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
841 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
842 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
843 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
844 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
845 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
846 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
847 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
848 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
849 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
850 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
851 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
852 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
853 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
854 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
855 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
856 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
857 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
858 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
859 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
860 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
861 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
862 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
863 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
864 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
865 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
866 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
867 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
868 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
876
877 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
878 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
879 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
880 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
881 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
882 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
883 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
884 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
885 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
886 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
887 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
888 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
889 { NULL, 0, NULL },
890 };
891
892 static void est_identify(driver_t *driver, device_t parent);
893 static int est_features(driver_t *driver, u_int *features);
894 static int est_probe(device_t parent);
895 static int est_attach(device_t parent);
896 static int est_detach(device_t parent);
897 static int est_get_info(device_t dev);
898 static int est_acpi_info(device_t dev, freq_info **freqs);
899 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
900 static freq_info *est_get_current(freq_info *freq_list);
901 static int est_settings(device_t dev, struct cf_setting *sets, int *count);
902 static int est_set(device_t dev, const struct cf_setting *set);
903 static int est_get(device_t dev, struct cf_setting *set);
904 static int est_type(device_t dev, int *type);
905
906 static device_method_t est_methods[] = {
907 /* Device interface */
908 DEVMETHOD(device_identify, est_identify),
909 DEVMETHOD(device_probe, est_probe),
910 DEVMETHOD(device_attach, est_attach),
911 DEVMETHOD(device_detach, est_detach),
912
913 /* cpufreq interface */
914 DEVMETHOD(cpufreq_drv_set, est_set),
915 DEVMETHOD(cpufreq_drv_get, est_get),
916 DEVMETHOD(cpufreq_drv_type, est_type),
917 DEVMETHOD(cpufreq_drv_settings, est_settings),
918
919 /* ACPI interface */
920 DEVMETHOD(acpi_get_features, est_features),
921
922 {0, 0}
923 };
924
925 static driver_t est_driver = {
926 "est",
927 est_methods,
928 sizeof(struct est_softc),
929 };
930
931 static devclass_t est_devclass;
932 DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
933
934 static int
935 est_features(driver_t *driver, u_int *features)
936 {
937
938 /* Notify the ACPI CPU that we support direct access to MSRs */
939 *features = ACPI_CAP_PERF_MSRS;
940 return (0);
941 }
942
943 static void
944 est_identify(driver_t *driver, device_t parent)
945 {
946 device_t child;
947 u_int p[4];
948
949 /* Make sure we're not being doubly invoked. */
950 if (device_find_child(parent, "est", -1) != NULL)
951 return;
952
953 /* Check that CPUID is supported and the vendor is Intel.*/
954 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 &&
955 strcmp(cpu_vendor, centaur_id) != 0))
956 return;
957
958 /*
959 * Read capability bits and check if the CPU supports EST.
960 * This is indicated by bit 7 of ECX.
961 */
962 do_cpuid(1, p);
963 if ((p[2] & 0x80) == 0)
964 return;
965
966 /*
967 * We add a child for each CPU since settings must be performed
968 * on each CPU in the SMP case.
969 */
970 child = BUS_ADD_CHILD(parent, 0, "est", -1);
971 if (child == NULL)
972 device_printf(parent, "add est child failed\n");
973 }
974
975 static int
976 est_probe(device_t dev)
977 {
978 device_t perf_dev;
979 uint64_t msr;
980 int error, type;
981
982 if (resource_disabled("est", 0))
983 return (ENXIO);
984
985 /*
986 * If the ACPI perf driver has attached and is not just offering
987 * info, let it manage things.
988 */
989 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
990 if (perf_dev && device_is_attached(perf_dev)) {
991 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
992 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
993 return (ENXIO);
994 }
995
996 /* Attempt to enable SpeedStep if not currently enabled. */
997 msr = rdmsr(MSR_MISC_ENABLE);
998 if ((msr & MSR_SS_ENABLE) == 0) {
999 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
1000 if (bootverbose)
1001 device_printf(dev, "enabling SpeedStep\n");
1002
1003 /* Check if the enable failed. */
1004 msr = rdmsr(MSR_MISC_ENABLE);
1005 if ((msr & MSR_SS_ENABLE) == 0) {
1006 device_printf(dev, "failed to enable SpeedStep\n");
1007 return (ENXIO);
1008 }
1009 }
1010
1011 device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
1012 return (0);
1013 }
1014
1015 static int
1016 est_attach(device_t dev)
1017 {
1018 struct est_softc *sc;
1019
1020 sc = device_get_softc(dev);
1021 sc->dev = dev;
1022
1023 /* Check CPU for supported settings. */
1024 if (est_get_info(dev))
1025 return (ENXIO);
1026
1027 cpufreq_register(dev);
1028 return (0);
1029 }
1030
1031 static int
1032 est_detach(device_t dev)
1033 {
1034 struct est_softc *sc;
1035
1036 sc = device_get_softc(dev);
1037 if (sc->acpi_settings)
1038 free(sc->freq_list, M_DEVBUF);
1039 return (ENXIO);
1040 }
1041
1042 /*
1043 * Probe for supported CPU settings. First, check our static table of
1044 * settings. If no match, try using the ones offered by acpi_perf
1045 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40
1046 * series) export both legacy SMM IO-based access and direct MSR access
1047 * but the direct access specifies invalid values for _PSS.
1048 */
1049 static int
1050 est_get_info(device_t dev)
1051 {
1052 struct est_softc *sc;
1053 uint64_t msr;
1054 int error;
1055
1056 sc = device_get_softc(dev);
1057 msr = rdmsr(MSR_PERF_STATUS);
1058 error = est_table_info(dev, msr, &sc->freq_list);
1059 if (error)
1060 error = est_acpi_info(dev, &sc->freq_list);
1061
1062 if (error) {
1063 printf(
1064 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1065 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1066 return (ENXIO);
1067 }
1068
1069 return (0);
1070 }
1071
1072 static int
1073 est_acpi_info(device_t dev, freq_info **freqs)
1074 {
1075 struct est_softc *sc;
1076 struct cf_setting *sets;
1077 freq_info *table;
1078 device_t perf_dev;
1079 int count, error, i;
1080
1081 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
1082 if (perf_dev == NULL || !device_is_attached(perf_dev))
1083 return (ENXIO);
1084
1085 /* Fetch settings from acpi_perf. */
1086 sc = device_get_softc(dev);
1087 table = NULL;
1088 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
1089 if (sets == NULL)
1090 return (ENOMEM);
1091 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
1092 if (error)
1093 goto out;
1094
1095 /* Parse settings into our local table format. */
1096 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
1097 if (table == NULL) {
1098 error = ENOMEM;
1099 goto out;
1100 }
1101 for (i = 0; i < count; i++) {
1102 /*
1103 * TODO: Figure out validity checks for id16. Linux checks
1104 * that the control and status values match.
1105 */
1106 table[i].freq = sets[i].freq;
1107 table[i].volts = sets[i].volts;
1108 table[i].id16 = sets[i].spec[0];
1109 table[i].power = sets[i].power;
1110 }
1111
1112 /* Mark end of table with a terminator. */
1113 bzero(&table[i], sizeof(freq_info));
1114
1115 sc->acpi_settings = TRUE;
1116 *freqs = table;
1117 error = 0;
1118
1119 out:
1120 if (sets)
1121 free(sets, M_TEMP);
1122 if (error && table)
1123 free(table, M_DEVBUF);
1124 return (error);
1125 }
1126
1127 static int
1128 est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
1129 {
1130 cpu_info *p;
1131 uint32_t id;
1132
1133 /* Find a table which matches (vendor, id32). */
1134 id = msr >> 32;
1135 for (p = ESTprocs; p->id32 != 0; p++) {
1136 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id)
1137 break;
1138 }
1139 if (p->id32 == 0)
1140 return (EOPNOTSUPP);
1141
1142 /* Make sure the current setpoint is valid. */
1143 if (est_get_current(p->freqtab) == NULL) {
1144 device_printf(dev, "current setting not found in table\n");
1145 return (EOPNOTSUPP);
1146 }
1147
1148 *freqs = p->freqtab;
1149 return (0);
1150 }
1151
1152 static freq_info *
1153 est_get_current(freq_info *freq_list)
1154 {
1155 freq_info *f;
1156 int i;
1157 uint16_t id16;
1158
1159 /*
1160 * Try a few times to get a valid value. Sometimes, if the CPU
1161 * is in the middle of an asynchronous transition (i.e., P4TCC),
1162 * we get a temporary invalid result.
1163 */
1164 for (i = 0; i < 5; i++) {
1165 id16 = rdmsr(MSR_PERF_STATUS) & 0xffff;
1166 for (f = freq_list; f->id16 != 0; f++) {
1167 if (f->id16 == id16)
1168 return (f);
1169 }
1170 DELAY(100);
1171 }
1172 return (NULL);
1173 }
1174
1175 static int
1176 est_settings(device_t dev, struct cf_setting *sets, int *count)
1177 {
1178 struct est_softc *sc;
1179 freq_info *f;
1180 int i;
1181
1182 sc = device_get_softc(dev);
1183 if (*count < EST_MAX_SETTINGS)
1184 return (E2BIG);
1185
1186 i = 0;
1187 for (f = sc->freq_list; f->freq != 0; f++, i++) {
1188 sets[i].freq = f->freq;
1189 sets[i].volts = f->volts;
1190 sets[i].power = f->power;
1191 sets[i].lat = EST_TRANS_LAT;
1192 sets[i].dev = dev;
1193 }
1194 *count = i;
1195
1196 return (0);
1197 }
1198
1199 static int
1200 est_set(device_t dev, const struct cf_setting *set)
1201 {
1202 struct est_softc *sc;
1203 freq_info *f;
1204 uint64_t msr;
1205
1206 /* Find the setting matching the requested one. */
1207 sc = device_get_softc(dev);
1208 for (f = sc->freq_list; f->freq != 0; f++) {
1209 if (f->freq == set->freq)
1210 break;
1211 }
1212 if (f->freq == 0)
1213 return (EINVAL);
1214
1215 /* Read the current register, mask out the old, set the new id. */
1216 msr = rdmsr(MSR_PERF_CTL);
1217 msr = (msr & ~0xffff) | f->id16;
1218 wrmsr(MSR_PERF_CTL, msr);
1219
1220 /* Wait a short while for the new setting. XXX Is this necessary? */
1221 DELAY(EST_TRANS_LAT);
1222
1223 return (0);
1224 }
1225
1226 static int
1227 est_get(device_t dev, struct cf_setting *set)
1228 {
1229 struct est_softc *sc;
1230 freq_info *f;
1231
1232 sc = device_get_softc(dev);
1233 f = est_get_current(sc->freq_list);
1234 if (f == NULL)
1235 return (ENXIO);
1236
1237 set->freq = f->freq;
1238 set->volts = f->volts;
1239 set->power = f->power;
1240 set->lat = EST_TRANS_LAT;
1241 set->dev = dev;
1242 return (0);
1243 }
1244
1245 static int
1246 est_type(device_t dev, int *type)
1247 {
1248
1249 if (type == NULL)
1250 return (EINVAL);
1251
1252 *type = CPUFREQ_TYPE_ABSOLUTE;
1253 return (0);
1254 }
Cache object: 9942e3ccfd407793acf8aa21f94c8c1a
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