The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/cpufreq/est.c

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    1 /*-
    2  * Copyright (c) 2004 Colin Percival
    3  * Copyright (c) 2005 Nate Lawson
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted providing that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
   17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 
   19  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
   24  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
   25  * POSSIBILITY OF SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/7.4/sys/i386/cpufreq/est.c 195667 2009-07-13 22:13:13Z jkim $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/bus.h>
   33 #include <sys/cpu.h>
   34 #include <sys/kernel.h>
   35 #include <sys/malloc.h>
   36 #include <sys/module.h>
   37 #include <sys/smp.h>
   38 #include <sys/systm.h>
   39 
   40 #include "cpufreq_if.h"
   41 #include <machine/clock.h>
   42 #include <machine/cputypes.h>
   43 #include <machine/md_var.h>
   44 #include <machine/specialreg.h>
   45 
   46 #include <contrib/dev/acpica/acpi.h>
   47 #include <dev/acpica/acpivar.h>
   48 #include "acpi_if.h"
   49 
   50 /* Status/control registers (from the IA-32 System Programming Guide). */
   51 #define MSR_PERF_STATUS         0x198
   52 #define MSR_PERF_CTL            0x199
   53 
   54 /* Register and bit for enabling SpeedStep. */
   55 #define MSR_MISC_ENABLE         0x1a0
   56 #define MSR_SS_ENABLE           (1<<16)
   57 
   58 /* Frequency and MSR control values. */
   59 typedef struct {
   60         uint16_t        freq;
   61         uint16_t        volts;
   62         uint16_t        id16;
   63         int             power;
   64 } freq_info;
   65 
   66 /* Identifying characteristics of a processor and supported frequencies. */
   67 typedef struct {
   68         const u_int     vendor_id;
   69         uint32_t        id32;
   70         freq_info       *freqtab;
   71 } cpu_info;
   72 
   73 struct est_softc {
   74         device_t        dev;
   75         int             acpi_settings;
   76         int             msr_settings;
   77         freq_info       *freq_list;
   78 };
   79 
   80 /* Convert MHz and mV into IDs for passing to the MSR. */
   81 #define ID16(MHz, mV, bus_clk)                          \
   82         (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
   83 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk)     \
   84         ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
   85 
   86 /* Format for storing IDs in our table. */
   87 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW)             \
   88         { MHz, mV, ID16(MHz, mV, bus_clk), mW }
   89 #define FREQ_INFO(MHz, mV, bus_clk)                     \
   90         FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
   91 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk)         \
   92         { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
   93 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk)       \
   94         { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
   95 
   96 static int msr_info_enabled = 0;
   97 TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
   98 
   99 /* Default bus clock value for Centrino processors. */
  100 #define INTEL_BUS_CLK           100
  101 
  102 /* XXX Update this if new CPUs have more settings. */
  103 #define EST_MAX_SETTINGS        10
  104 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
  105 
  106 /* Estimate in microseconds of latency for performing a transition. */
  107 #define EST_TRANS_LAT           1000
  108 
  109 /*
  110  * Frequency (MHz) and voltage (mV) settings.  Data from the
  111  * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
  112  *
  113  * Dothan processors have multiple VID#s with different settings for
  114  * each VID#.  Since we can't uniquely identify this info
  115  * without undisclosed methods from Intel, we can't support newer
  116  * processors with this table method.  If ACPI Px states are supported,
  117  * we get info from them.
  118  */
  119 static freq_info PM17_130[] = {
  120         /* 130nm 1.70GHz Pentium M */
  121         FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
  122         FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
  123         FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
  124         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  125         FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
  126         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  127         FREQ_INFO(   0,    0, 1),
  128 };
  129 static freq_info PM16_130[] = {
  130         /* 130nm 1.60GHz Pentium M */
  131         FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
  132         FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
  133         FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
  134         FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
  135         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  136         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  137         FREQ_INFO(   0,    0, 1),
  138 };
  139 static freq_info PM15_130[] = {
  140         /* 130nm 1.50GHz Pentium M */
  141         FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
  142         FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
  143         FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
  144         FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
  145         FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
  146         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  147         FREQ_INFO(   0,    0, 1),
  148 };
  149 static freq_info PM14_130[] = {
  150         /* 130nm 1.40GHz Pentium M */
  151         FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
  152         FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
  153         FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
  154         FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
  155         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  156         FREQ_INFO(   0,    0, 1),
  157 };
  158 static freq_info PM13_130[] = {
  159         /* 130nm 1.30GHz Pentium M */
  160         FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
  161         FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
  162         FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
  163         FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
  164         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  165         FREQ_INFO(   0,    0, 1),
  166 };
  167 static freq_info PM13_LV_130[] = {
  168         /* 130nm 1.30GHz Low Voltage Pentium M */
  169         FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
  170         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  171         FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
  172         FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
  173         FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
  174         FREQ_INFO( 800,  988, INTEL_BUS_CLK),
  175         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  176         FREQ_INFO(   0,    0, 1),
  177 };
  178 static freq_info PM12_LV_130[] = {
  179         /* 130 nm 1.20GHz Low Voltage Pentium M */
  180         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  181         FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
  182         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  183         FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
  184         FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
  185         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  186         FREQ_INFO(   0,    0, 1),
  187 };
  188 static freq_info PM11_LV_130[] = {
  189         /* 130 nm 1.10GHz Low Voltage Pentium M */
  190         FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
  191         FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
  192         FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
  193         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  194         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  195         FREQ_INFO(   0,    0, 1),
  196 };
  197 static freq_info PM11_ULV_130[] = {
  198         /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
  199         FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
  200         FREQ_INFO(1000,  988, INTEL_BUS_CLK),
  201         FREQ_INFO( 900,  972, INTEL_BUS_CLK),
  202         FREQ_INFO( 800,  956, INTEL_BUS_CLK),
  203         FREQ_INFO( 600,  844, INTEL_BUS_CLK),
  204         FREQ_INFO(   0,    0, 1),
  205 };
  206 static freq_info PM10_ULV_130[] = {
  207         /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
  208         FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
  209         FREQ_INFO( 900,  988, INTEL_BUS_CLK),
  210         FREQ_INFO( 800,  972, INTEL_BUS_CLK),
  211         FREQ_INFO( 600,  844, INTEL_BUS_CLK),
  212         FREQ_INFO(   0,    0, 1),
  213 };
  214 
  215 /*
  216  * Data from "Intel Pentium M Processor on 90nm Process with
  217  * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
  218  */
  219 static freq_info PM_765A_90[] = {
  220         /* 90 nm 2.10GHz Pentium M, VID #A */
  221         FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
  222         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  223         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  224         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  225         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  226         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  227         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  228         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  229         FREQ_INFO(   0,    0, 1),
  230 };
  231 static freq_info PM_765B_90[] = {
  232         /* 90 nm 2.10GHz Pentium M, VID #B */
  233         FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
  234         FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
  235         FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
  236         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  237         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  238         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  239         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  240         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  241         FREQ_INFO(   0,    0, 1),
  242 };
  243 static freq_info PM_765C_90[] = {
  244         /* 90 nm 2.10GHz Pentium M, VID #C */
  245         FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
  246         FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
  247         FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
  248         FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
  249         FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
  250         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  251         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  252         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  253         FREQ_INFO(   0,    0, 1),
  254 };
  255 static freq_info PM_765E_90[] = {
  256         /* 90 nm 2.10GHz Pentium M, VID #E */
  257         FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
  258         FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
  259         FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
  260         FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
  261         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  262         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  263         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  264         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  265         FREQ_INFO(   0,    0, 1),
  266 };
  267 static freq_info PM_755A_90[] = {
  268         /* 90 nm 2.00GHz Pentium M, VID #A */
  269         FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
  270         FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
  271         FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
  272         FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
  273         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  274         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  275         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  276         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  277         FREQ_INFO(   0,    0, 1),
  278 };
  279 static freq_info PM_755B_90[] = {
  280         /* 90 nm 2.00GHz Pentium M, VID #B */
  281         FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
  282         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  283         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  284         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  285         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  286         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  287         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  288         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  289         FREQ_INFO(   0,    0, 1),
  290 };
  291 static freq_info PM_755C_90[] = {
  292         /* 90 nm 2.00GHz Pentium M, VID #C */
  293         FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
  294         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  295         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  296         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  297         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  298         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  299         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  300         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  301         FREQ_INFO(   0,    0, 1),
  302 };
  303 static freq_info PM_755D_90[] = {
  304         /* 90 nm 2.00GHz Pentium M, VID #D */
  305         FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
  306         FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
  307         FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
  308         FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
  309         FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
  310         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  311         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  312         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  313         FREQ_INFO(   0,    0, 1),
  314 };
  315 static freq_info PM_745A_90[] = {
  316         /* 90 nm 1.80GHz Pentium M, VID #A */
  317         FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
  318         FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
  319         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  320         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  321         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  322         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  323         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  324         FREQ_INFO(   0,    0, 1),
  325 };
  326 static freq_info PM_745B_90[] = {
  327         /* 90 nm 1.80GHz Pentium M, VID #B */
  328         FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
  329         FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
  330         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  331         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  332         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  333         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  334         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  335         FREQ_INFO(   0,    0, 1),
  336 };
  337 static freq_info PM_745C_90[] = {
  338         /* 90 nm 1.80GHz Pentium M, VID #C */
  339         FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
  340         FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
  341         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  342         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  343         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  344         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  345         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  346         FREQ_INFO(   0,    0, 1),
  347 };
  348 static freq_info PM_745D_90[] = {
  349         /* 90 nm 1.80GHz Pentium M, VID #D */
  350         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  351         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  352         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  353         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  354         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  355         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  356         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  357         FREQ_INFO(   0,    0, 1),
  358 };
  359 static freq_info PM_735A_90[] = {
  360         /* 90 nm 1.70GHz Pentium M, VID #A */
  361         FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
  362         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  363         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  364         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  365         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  366         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  367         FREQ_INFO(   0,    0, 1),
  368 };
  369 static freq_info PM_735B_90[] = {
  370         /* 90 nm 1.70GHz Pentium M, VID #B */
  371         FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
  372         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  373         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  374         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  375         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  376         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  377         FREQ_INFO(   0,    0, 1),
  378 };
  379 static freq_info PM_735C_90[] = {
  380         /* 90 nm 1.70GHz Pentium M, VID #C */
  381         FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
  382         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  383         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  384         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  385         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  386         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  387         FREQ_INFO(   0,    0, 1),
  388 };
  389 static freq_info PM_735D_90[] = {
  390         /* 90 nm 1.70GHz Pentium M, VID #D */
  391         FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
  392         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  393         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  394         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  395         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  396         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  397         FREQ_INFO(   0,    0, 1),
  398 };
  399 static freq_info PM_725A_90[] = {
  400         /* 90 nm 1.60GHz Pentium M, VID #A */
  401         FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
  402         FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
  403         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  404         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  405         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  406         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  407         FREQ_INFO(   0,    0, 1),
  408 };
  409 static freq_info PM_725B_90[] = {
  410         /* 90 nm 1.60GHz Pentium M, VID #B */
  411         FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
  412         FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
  413         FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
  414         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  415         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  416         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  417         FREQ_INFO(   0,    0, 1),
  418 };
  419 static freq_info PM_725C_90[] = {
  420         /* 90 nm 1.60GHz Pentium M, VID #C */
  421         FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
  422         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  423         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  424         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  425         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  426         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  427         FREQ_INFO(   0,    0, 1),
  428 };
  429 static freq_info PM_725D_90[] = {
  430         /* 90 nm 1.60GHz Pentium M, VID #D */
  431         FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
  432         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  433         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  434         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  435         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  436         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  437         FREQ_INFO(   0,    0, 1),
  438 };
  439 static freq_info PM_715A_90[] = {
  440         /* 90 nm 1.50GHz Pentium M, VID #A */
  441         FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
  442         FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
  443         FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
  444         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  445         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  446         FREQ_INFO(   0,    0, 1),
  447 };
  448 static freq_info PM_715B_90[] = {
  449         /* 90 nm 1.50GHz Pentium M, VID #B */
  450         FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
  451         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  452         FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
  453         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  454         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  455         FREQ_INFO(   0,    0, 1),
  456 };
  457 static freq_info PM_715C_90[] = {
  458         /* 90 nm 1.50GHz Pentium M, VID #C */
  459         FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
  460         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  461         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  462         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  463         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  464         FREQ_INFO(   0,    0, 1),
  465 };
  466 static freq_info PM_715D_90[] = {
  467         /* 90 nm 1.50GHz Pentium M, VID #D */
  468         FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
  469         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  470         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  471         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  472         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  473         FREQ_INFO(   0,    0, 1),
  474 };
  475 static freq_info PM_778_90[] = {
  476         /* 90 nm 1.60GHz Low Voltage Pentium M */
  477         FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
  478         FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
  479         FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
  480         FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
  481         FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
  482         FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
  483         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  484         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  485         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  486         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  487         FREQ_INFO(   0,    0, 1),
  488 };
  489 static freq_info PM_758_90[] = {
  490         /* 90 nm 1.50GHz Low Voltage Pentium M */
  491         FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
  492         FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
  493         FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
  494         FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
  495         FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
  496         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  497         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  498         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  499         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  500         FREQ_INFO(   0,    0, 1),
  501 };
  502 static freq_info PM_738_90[] = {
  503         /* 90 nm 1.40GHz Low Voltage Pentium M */
  504         FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
  505         FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
  506         FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
  507         FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
  508         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  509         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  510         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  511         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  512         FREQ_INFO(   0,    0, 1),
  513 };
  514 static freq_info PM_773G_90[] = {
  515         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
  516         FREQ_INFO(1300,  956, INTEL_BUS_CLK),
  517         FREQ_INFO(1200,  940, INTEL_BUS_CLK),
  518         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  519         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  520         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  521         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  522         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  523 };
  524 static freq_info PM_773H_90[] = {
  525         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
  526         FREQ_INFO(1300,  940, INTEL_BUS_CLK),
  527         FREQ_INFO(1200,  924, INTEL_BUS_CLK),
  528         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  529         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  530         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  531         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  532         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  533 };
  534 static freq_info PM_773I_90[] = {
  535         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
  536         FREQ_INFO(1300,  924, INTEL_BUS_CLK),
  537         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  538         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  539         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  540         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  541         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  542         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  543 };
  544 static freq_info PM_773J_90[] = {
  545         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
  546         FREQ_INFO(1300,  908, INTEL_BUS_CLK),
  547         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  548         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  549         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  550         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  551         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  552         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  553 };
  554 static freq_info PM_773K_90[] = {
  555         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
  556         FREQ_INFO(1300,  892, INTEL_BUS_CLK),
  557         FREQ_INFO(1200,  892, INTEL_BUS_CLK),
  558         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  559         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  560         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  561         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  562         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  563 };
  564 static freq_info PM_773L_90[] = {
  565         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
  566         FREQ_INFO(1300,  876, INTEL_BUS_CLK),
  567         FREQ_INFO(1200,  876, INTEL_BUS_CLK),
  568         FREQ_INFO(1100,  860, INTEL_BUS_CLK),
  569         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  570         FREQ_INFO( 900,  844, INTEL_BUS_CLK),
  571         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  572         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  573 };
  574 static freq_info PM_753G_90[] = {
  575         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
  576         FREQ_INFO(1200,  956, INTEL_BUS_CLK),
  577         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  578         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  579         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  580         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  581         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  582 };
  583 static freq_info PM_753H_90[] = {
  584         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
  585         FREQ_INFO(1200,  940, INTEL_BUS_CLK),
  586         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  587         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  588         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  589         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  590         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  591 };
  592 static freq_info PM_753I_90[] = {
  593         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
  594         FREQ_INFO(1200,  924, INTEL_BUS_CLK),
  595         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  596         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  597         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  598         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  599         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  600 };
  601 static freq_info PM_753J_90[] = {
  602         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
  603         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  604         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  605         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  606         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  607         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  608         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  609 };
  610 static freq_info PM_753K_90[] = {
  611         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
  612         FREQ_INFO(1200,  892, INTEL_BUS_CLK),
  613         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  614         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  615         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  616         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  617         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  618 };
  619 static freq_info PM_753L_90[] = {
  620         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
  621         FREQ_INFO(1200,  876, INTEL_BUS_CLK),
  622         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  623         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  624         FREQ_INFO( 900,  844, INTEL_BUS_CLK),
  625         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  626         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  627 };
  628 
  629 static freq_info PM_733JG_90[] = {
  630         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
  631         FREQ_INFO(1100,  956, INTEL_BUS_CLK),
  632         FREQ_INFO(1000,  940, INTEL_BUS_CLK),
  633         FREQ_INFO( 900,  908, INTEL_BUS_CLK),
  634         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  635         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  636 };
  637 static freq_info PM_733JH_90[] = {
  638         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
  639         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  640         FREQ_INFO(1000,  924, INTEL_BUS_CLK),
  641         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  642         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  643         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  644 };
  645 static freq_info PM_733JI_90[] = {
  646         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
  647         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  648         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  649         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  650         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  651         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  652 };
  653 static freq_info PM_733JJ_90[] = {
  654         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
  655         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  656         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  657         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  658         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  659         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  660 };
  661 static freq_info PM_733JK_90[] = {
  662         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
  663         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  664         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  665         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  666         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  667         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  668 };
  669 static freq_info PM_733JL_90[] = {
  670         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
  671         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  672         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  673         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  674         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  675         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  676 };
  677 static freq_info PM_733_90[] = {
  678         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
  679         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  680         FREQ_INFO(1000,  924, INTEL_BUS_CLK),
  681         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  682         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  683         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  684         FREQ_INFO(   0,    0, 1),
  685 };
  686 static freq_info PM_723_90[] = {
  687         /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
  688         FREQ_INFO(1000,  940, INTEL_BUS_CLK),
  689         FREQ_INFO( 900,  908, INTEL_BUS_CLK),
  690         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  691         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  692         FREQ_INFO(   0,    0, 1),
  693 };
  694 
  695 /*
  696  * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
  697  * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
  698  */
  699 static freq_info C7M_795[] = {
  700         /* 2.00GHz Centaur C7-M 533 Mhz FSB */
  701         FREQ_INFO_PWR(2000, 1148, 133, 20000),
  702         FREQ_INFO_PWR(1867, 1132, 133, 18000),
  703         FREQ_INFO_PWR(1600, 1100, 133, 15000),
  704         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  705         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  706         FREQ_INFO_PWR( 800,  844, 133,  7000),
  707         FREQ_INFO_PWR( 667,  844, 133,  6000),
  708         FREQ_INFO_PWR( 533,  844, 133,  5000),
  709         FREQ_INFO(0, 0, 1),
  710 };
  711 static freq_info C7M_785[] = {
  712         /* 1.80GHz Centaur C7-M 533 Mhz FSB */
  713         FREQ_INFO_PWR(1867, 1148, 133, 18000),
  714         FREQ_INFO_PWR(1600, 1100, 133, 15000),
  715         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  716         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  717         FREQ_INFO_PWR( 800,  844, 133,  7000),
  718         FREQ_INFO_PWR( 667,  844, 133,  6000),
  719         FREQ_INFO_PWR( 533,  844, 133,  5000),
  720         FREQ_INFO(0, 0, 1),
  721 };
  722 static freq_info C7M_765[] = {
  723         /* 1.60GHz Centaur C7-M 533 Mhz FSB */
  724         FREQ_INFO_PWR(1600, 1084, 133, 15000),
  725         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  726         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  727         FREQ_INFO_PWR( 800,  844, 133,  7000),
  728         FREQ_INFO_PWR( 667,  844, 133,  6000),
  729         FREQ_INFO_PWR( 533,  844, 133,  5000),
  730         FREQ_INFO(0, 0, 1),
  731 };
  732 
  733 static freq_info C7M_794[] = {
  734         /* 2.00GHz Centaur C7-M 400 Mhz FSB */
  735         FREQ_INFO_PWR(2000, 1148, 100, 20000),
  736         FREQ_INFO_PWR(1800, 1132, 100, 18000),
  737         FREQ_INFO_PWR(1600, 1100, 100, 15000),
  738         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  739         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  740         FREQ_INFO_PWR( 800,  844, 100,  7000),
  741         FREQ_INFO_PWR( 600,  844, 100,  6000),
  742         FREQ_INFO_PWR( 400,  844, 100,  5000),
  743         FREQ_INFO(0, 0, 1),
  744 };
  745 static freq_info C7M_784[] = {
  746         /* 1.80GHz Centaur C7-M 400 Mhz FSB */
  747         FREQ_INFO_PWR(1800, 1148, 100, 18000),
  748         FREQ_INFO_PWR(1600, 1100, 100, 15000),
  749         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  750         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  751         FREQ_INFO_PWR( 800,  844, 100,  7000),
  752         FREQ_INFO_PWR( 600,  844, 100,  6000),
  753         FREQ_INFO_PWR( 400,  844, 100,  5000),
  754         FREQ_INFO(0, 0, 1),
  755 };
  756 static freq_info C7M_764[] = {
  757         /* 1.60GHz Centaur C7-M 400 Mhz FSB */
  758         FREQ_INFO_PWR(1600, 1084, 100, 15000),
  759         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  760         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  761         FREQ_INFO_PWR( 800,  844, 100,  7000),
  762         FREQ_INFO_PWR( 600,  844, 100,  6000),
  763         FREQ_INFO_PWR( 400,  844, 100,  5000),
  764         FREQ_INFO(0, 0, 1),
  765 };
  766 static freq_info C7M_754[] = {
  767         /* 1.50GHz Centaur C7-M 400 Mhz FSB */
  768         FREQ_INFO_PWR(1500, 1004, 100, 12000),
  769         FREQ_INFO_PWR(1400,  988, 100, 11000),
  770         FREQ_INFO_PWR(1000,  940, 100,  9000),
  771         FREQ_INFO_PWR( 800,  844, 100,  7000),
  772         FREQ_INFO_PWR( 600,  844, 100,  6000),
  773         FREQ_INFO_PWR( 400,  844, 100,  5000),
  774         FREQ_INFO(0, 0, 1),
  775 };
  776 static freq_info C7M_771[] = {
  777         /* 1.20GHz Centaur C7-M 400 Mhz FSB */
  778         FREQ_INFO_PWR(1200,  860, 100,  7000),
  779         FREQ_INFO_PWR(1000,  860, 100,  6000),
  780         FREQ_INFO_PWR( 800,  844, 100,  5500),
  781         FREQ_INFO_PWR( 600,  844, 100,  5000),
  782         FREQ_INFO_PWR( 400,  844, 100,  4000),
  783         FREQ_INFO(0, 0, 1),
  784 };
  785 
  786 static freq_info C7M_775_ULV[] = {
  787         /* 1.50GHz Centaur C7-M ULV */
  788         FREQ_INFO_PWR(1500,  956, 100,  7500),
  789         FREQ_INFO_PWR(1400,  940, 100,  6000),
  790         FREQ_INFO_PWR(1000,  860, 100,  5000),
  791         FREQ_INFO_PWR( 800,  828, 100,  2800),
  792         FREQ_INFO_PWR( 600,  796, 100,  2500),
  793         FREQ_INFO_PWR( 400,  796, 100,  2000),
  794         FREQ_INFO(0, 0, 1),
  795 };
  796 static freq_info C7M_772_ULV[] = {
  797         /* 1.20GHz Centaur C7-M ULV */
  798         FREQ_INFO_PWR(1200,  844, 100,  5000),
  799         FREQ_INFO_PWR(1000,  844, 100,  4000),
  800         FREQ_INFO_PWR( 800,  828, 100,  2800),
  801         FREQ_INFO_PWR( 600,  796, 100,  2500),
  802         FREQ_INFO_PWR( 400,  796, 100,  2000),
  803         FREQ_INFO(0, 0, 1),
  804 };
  805 static freq_info C7M_779_ULV[] = {
  806         /* 1.00GHz Centaur C7-M ULV */
  807         FREQ_INFO_PWR(1000,  796, 100,  3500),
  808         FREQ_INFO_PWR( 800,  796, 100,  2800),
  809         FREQ_INFO_PWR( 600,  796, 100,  2500),
  810         FREQ_INFO_PWR( 400,  796, 100,  2000),
  811         FREQ_INFO(0, 0, 1),
  812 };
  813 static freq_info C7M_770_ULV[] = {
  814         /* 1.00GHz Centaur C7-M ULV */
  815         FREQ_INFO_PWR(1000,  844, 100,  5000),
  816         FREQ_INFO_PWR( 800,  796, 100,  2800),
  817         FREQ_INFO_PWR( 600,  796, 100,  2500),
  818         FREQ_INFO_PWR( 400,  796, 100,  2000),
  819         FREQ_INFO(0, 0, 1),
  820 };
  821 
  822 static cpu_info ESTprocs[] = {
  823         INTEL(PM17_130,         1700, 1484, 600, 956, INTEL_BUS_CLK),
  824         INTEL(PM16_130,         1600, 1484, 600, 956, INTEL_BUS_CLK),
  825         INTEL(PM15_130,         1500, 1484, 600, 956, INTEL_BUS_CLK),
  826         INTEL(PM14_130,         1400, 1484, 600, 956, INTEL_BUS_CLK),
  827         INTEL(PM13_130,         1300, 1388, 600, 956, INTEL_BUS_CLK),
  828         INTEL(PM13_LV_130,      1300, 1180, 600, 956, INTEL_BUS_CLK),
  829         INTEL(PM12_LV_130,      1200, 1180, 600, 956, INTEL_BUS_CLK),
  830         INTEL(PM11_LV_130,      1100, 1180, 600, 956, INTEL_BUS_CLK),
  831         INTEL(PM11_ULV_130,     1100, 1004, 600, 844, INTEL_BUS_CLK),
  832         INTEL(PM10_ULV_130,     1000, 1004, 600, 844, INTEL_BUS_CLK),
  833         INTEL(PM_765A_90,       2100, 1340, 600, 988, INTEL_BUS_CLK),
  834         INTEL(PM_765B_90,       2100, 1324, 600, 988, INTEL_BUS_CLK),
  835         INTEL(PM_765C_90,       2100, 1308, 600, 988, INTEL_BUS_CLK),
  836         INTEL(PM_765E_90,       2100, 1356, 600, 988, INTEL_BUS_CLK),
  837         INTEL(PM_755A_90,       2000, 1340, 600, 988, INTEL_BUS_CLK),
  838         INTEL(PM_755B_90,       2000, 1324, 600, 988, INTEL_BUS_CLK),
  839         INTEL(PM_755C_90,       2000, 1308, 600, 988, INTEL_BUS_CLK),
  840         INTEL(PM_755D_90,       2000, 1276, 600, 988, INTEL_BUS_CLK),
  841         INTEL(PM_745A_90,       1800, 1340, 600, 988, INTEL_BUS_CLK),
  842         INTEL(PM_745B_90,       1800, 1324, 600, 988, INTEL_BUS_CLK),
  843         INTEL(PM_745C_90,       1800, 1308, 600, 988, INTEL_BUS_CLK),
  844         INTEL(PM_745D_90,       1800, 1276, 600, 988, INTEL_BUS_CLK),
  845         INTEL(PM_735A_90,       1700, 1340, 600, 988, INTEL_BUS_CLK),
  846         INTEL(PM_735B_90,       1700, 1324, 600, 988, INTEL_BUS_CLK),
  847         INTEL(PM_735C_90,       1700, 1308, 600, 988, INTEL_BUS_CLK),
  848         INTEL(PM_735D_90,       1700, 1276, 600, 988, INTEL_BUS_CLK),
  849         INTEL(PM_725A_90,       1600, 1340, 600, 988, INTEL_BUS_CLK),
  850         INTEL(PM_725B_90,       1600, 1324, 600, 988, INTEL_BUS_CLK),
  851         INTEL(PM_725C_90,       1600, 1308, 600, 988, INTEL_BUS_CLK),
  852         INTEL(PM_725D_90,       1600, 1276, 600, 988, INTEL_BUS_CLK),
  853         INTEL(PM_715A_90,       1500, 1340, 600, 988, INTEL_BUS_CLK),
  854         INTEL(PM_715B_90,       1500, 1324, 600, 988, INTEL_BUS_CLK),
  855         INTEL(PM_715C_90,       1500, 1308, 600, 988, INTEL_BUS_CLK),
  856         INTEL(PM_715D_90,       1500, 1276, 600, 988, INTEL_BUS_CLK),
  857         INTEL(PM_778_90,        1600, 1116, 600, 988, INTEL_BUS_CLK),
  858         INTEL(PM_758_90,        1500, 1116, 600, 988, INTEL_BUS_CLK),
  859         INTEL(PM_738_90,        1400, 1116, 600, 988, INTEL_BUS_CLK),
  860         INTEL(PM_773G_90,       1300,  956, 600, 812, INTEL_BUS_CLK),
  861         INTEL(PM_773H_90,       1300,  940, 600, 812, INTEL_BUS_CLK),
  862         INTEL(PM_773I_90,       1300,  924, 600, 812, INTEL_BUS_CLK),
  863         INTEL(PM_773J_90,       1300,  908, 600, 812, INTEL_BUS_CLK),
  864         INTEL(PM_773K_90,       1300,  892, 600, 812, INTEL_BUS_CLK),
  865         INTEL(PM_773L_90,       1300,  876, 600, 812, INTEL_BUS_CLK),
  866         INTEL(PM_753G_90,       1200,  956, 600, 812, INTEL_BUS_CLK),
  867         INTEL(PM_753H_90,       1200,  940, 600, 812, INTEL_BUS_CLK),
  868         INTEL(PM_753I_90,       1200,  924, 600, 812, INTEL_BUS_CLK),
  869         INTEL(PM_753J_90,       1200,  908, 600, 812, INTEL_BUS_CLK),
  870         INTEL(PM_753K_90,       1200,  892, 600, 812, INTEL_BUS_CLK),
  871         INTEL(PM_753L_90,       1200,  876, 600, 812, INTEL_BUS_CLK),
  872         INTEL(PM_733JG_90,      1100,  956, 600, 812, INTEL_BUS_CLK),
  873         INTEL(PM_733JH_90,      1100,  940, 600, 812, INTEL_BUS_CLK),
  874         INTEL(PM_733JI_90,      1100,  924, 600, 812, INTEL_BUS_CLK),
  875         INTEL(PM_733JJ_90,      1100,  908, 600, 812, INTEL_BUS_CLK),
  876         INTEL(PM_733JK_90,      1100,  892, 600, 812, INTEL_BUS_CLK),
  877         INTEL(PM_733JL_90,      1100,  876, 600, 812, INTEL_BUS_CLK),
  878         INTEL(PM_733_90,        1100,  940, 600, 812, INTEL_BUS_CLK),
  879         INTEL(PM_723_90,        1000,  940, 600, 812, INTEL_BUS_CLK),
  880 
  881         CENTAUR(C7M_795,        2000, 1148, 533, 844, 133),
  882         CENTAUR(C7M_794,        2000, 1148, 400, 844, 100),
  883         CENTAUR(C7M_785,        1867, 1148, 533, 844, 133),
  884         CENTAUR(C7M_784,        1800, 1148, 400, 844, 100),
  885         CENTAUR(C7M_765,        1600, 1084, 533, 844, 133),
  886         CENTAUR(C7M_764,        1600, 1084, 400, 844, 100),
  887         CENTAUR(C7M_754,        1500, 1004, 400, 844, 100),
  888         CENTAUR(C7M_775_ULV,    1500,  956, 400, 796, 100),
  889         CENTAUR(C7M_771,        1200,  860, 400, 844, 100),
  890         CENTAUR(C7M_772_ULV,    1200,  844, 400, 796, 100),
  891         CENTAUR(C7M_779_ULV,    1000,  796, 400, 796, 100),
  892         CENTAUR(C7M_770_ULV,    1000,  844, 400, 796, 100),
  893         { 0, 0, NULL },
  894 };
  895 
  896 static void     est_identify(driver_t *driver, device_t parent);
  897 static int      est_features(driver_t *driver, u_int *features);
  898 static int      est_probe(device_t parent);
  899 static int      est_attach(device_t parent);
  900 static int      est_detach(device_t parent);
  901 static int      est_get_info(device_t dev);
  902 static int      est_acpi_info(device_t dev, freq_info **freqs);
  903 static int      est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
  904 static int      est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
  905 static freq_info *est_get_current(freq_info *freq_list);
  906 static int      est_settings(device_t dev, struct cf_setting *sets, int *count);
  907 static int      est_set(device_t dev, const struct cf_setting *set);
  908 static int      est_get(device_t dev, struct cf_setting *set);
  909 static int      est_type(device_t dev, int *type);
  910 static int      est_set_id16(device_t dev, uint16_t id16, int need_check);
  911 static void     est_get_id16(uint16_t *id16_p);
  912 
  913 static device_method_t est_methods[] = {
  914         /* Device interface */
  915         DEVMETHOD(device_identify,      est_identify),
  916         DEVMETHOD(device_probe,         est_probe),
  917         DEVMETHOD(device_attach,        est_attach),
  918         DEVMETHOD(device_detach,        est_detach),
  919 
  920         /* cpufreq interface */
  921         DEVMETHOD(cpufreq_drv_set,      est_set),
  922         DEVMETHOD(cpufreq_drv_get,      est_get),
  923         DEVMETHOD(cpufreq_drv_type,     est_type),
  924         DEVMETHOD(cpufreq_drv_settings, est_settings),
  925 
  926         /* ACPI interface */
  927         DEVMETHOD(acpi_get_features,    est_features),
  928 
  929         {0, 0}
  930 };
  931 
  932 static driver_t est_driver = {
  933         "est",
  934         est_methods,
  935         sizeof(struct est_softc),
  936 };
  937 
  938 static devclass_t est_devclass;
  939 DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
  940 
  941 static int
  942 est_features(driver_t *driver, u_int *features)
  943 {
  944 
  945         /* Notify the ACPI CPU that we support direct access to MSRs */
  946         *features = ACPI_CAP_PERF_MSRS;
  947         return (0);
  948 }
  949 
  950 static void
  951 est_identify(driver_t *driver, device_t parent)
  952 {
  953         device_t child;
  954 
  955         /* Make sure we're not being doubly invoked. */
  956         if (device_find_child(parent, "est", -1) != NULL)
  957                 return;
  958 
  959         /* Check that CPUID is supported and the vendor is Intel.*/
  960         if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
  961             cpu_vendor_id != CPU_VENDOR_CENTAUR))
  962                 return;
  963 
  964         /*
  965          * Check if the CPU supports EST.
  966          */
  967         if (!(cpu_feature2 & CPUID2_EST))
  968                 return;
  969 
  970         /*
  971          * We add a child for each CPU since settings must be performed
  972          * on each CPU in the SMP case.
  973          */
  974         child = BUS_ADD_CHILD(parent, 10, "est", -1);
  975         if (child == NULL)
  976                 device_printf(parent, "add est child failed\n");
  977 }
  978 
  979 static int
  980 est_probe(device_t dev)
  981 {
  982         device_t perf_dev;
  983         uint64_t msr;
  984         int error, type;
  985         
  986         if (resource_disabled("est", 0))
  987                 return (ENXIO);
  988 
  989         /*
  990          * If the ACPI perf driver has attached and is not just offering
  991          * info, let it manage things.
  992          */
  993         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
  994         if (perf_dev && device_is_attached(perf_dev)) {
  995                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
  996                 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
  997                         return (ENXIO);
  998         }
  999 
 1000         /* Attempt to enable SpeedStep if not currently enabled. */
 1001         msr = rdmsr(MSR_MISC_ENABLE);
 1002         if ((msr & MSR_SS_ENABLE) == 0) {
 1003                 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
 1004                 if (bootverbose)
 1005                         device_printf(dev, "enabling SpeedStep\n");
 1006 
 1007                 /* Check if the enable failed. */
 1008                 msr = rdmsr(MSR_MISC_ENABLE);
 1009                 if ((msr & MSR_SS_ENABLE) == 0) {
 1010                         device_printf(dev, "failed to enable SpeedStep\n");
 1011                         return (ENXIO);
 1012                 }
 1013         }
 1014 
 1015         device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
 1016         return (0);
 1017 }
 1018 
 1019 static int
 1020 est_attach(device_t dev)
 1021 {
 1022         struct est_softc *sc;
 1023 
 1024         sc = device_get_softc(dev);
 1025         sc->dev = dev;
 1026 
 1027         /* Check CPU for supported settings. */
 1028         if (est_get_info(dev))
 1029                 return (ENXIO);
 1030 
 1031         cpufreq_register(dev);
 1032         return (0);
 1033 }
 1034 
 1035 static int
 1036 est_detach(device_t dev)
 1037 {
 1038         struct est_softc *sc;
 1039         int error;
 1040 
 1041         error = cpufreq_unregister(dev);
 1042         if (error)
 1043                 return (error);
 1044 
 1045         sc = device_get_softc(dev);
 1046         if (sc->acpi_settings || sc->msr_settings)
 1047                 free(sc->freq_list, M_DEVBUF);
 1048         return (0);
 1049 }
 1050 
 1051 /*
 1052  * Probe for supported CPU settings.  First, check our static table of
 1053  * settings.  If no match, try using the ones offered by acpi_perf
 1054  * (i.e., _PSS).  We use ACPI second because some systems (IBM R/T40
 1055  * series) export both legacy SMM IO-based access and direct MSR access
 1056  * but the direct access specifies invalid values for _PSS.
 1057  */
 1058 static int
 1059 est_get_info(device_t dev)
 1060 {
 1061         struct est_softc *sc;
 1062         uint64_t msr;
 1063         int error;
 1064 
 1065         sc = device_get_softc(dev);
 1066         msr = rdmsr(MSR_PERF_STATUS);
 1067         error = est_table_info(dev, msr, &sc->freq_list);
 1068         if (error)
 1069                 error = est_acpi_info(dev, &sc->freq_list);
 1070         if (error)
 1071                 error = est_msr_info(dev, msr, &sc->freq_list);
 1072 
 1073         if (error) {
 1074                 printf(
 1075         "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
 1076         "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
 1077                 return (ENXIO);
 1078         }
 1079 
 1080         return (0);
 1081 }
 1082 
 1083 static int
 1084 est_acpi_info(device_t dev, freq_info **freqs)
 1085 {
 1086         struct est_softc *sc;
 1087         struct cf_setting *sets;
 1088         freq_info *table;
 1089         device_t perf_dev;
 1090         int count, error, i, j;
 1091         uint16_t saved_id16;
 1092 
 1093         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 1094         if (perf_dev == NULL || !device_is_attached(perf_dev))
 1095                 return (ENXIO);
 1096 
 1097         /* Fetch settings from acpi_perf. */
 1098         sc = device_get_softc(dev);
 1099         table = NULL;
 1100         sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
 1101         if (sets == NULL)
 1102                 return (ENOMEM);
 1103         count = MAX_SETTINGS;
 1104         error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
 1105         if (error)
 1106                 goto out;
 1107 
 1108         /* Parse settings into our local table format. */
 1109         table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
 1110         if (table == NULL) {
 1111                 error = ENOMEM;
 1112                 goto out;
 1113         }
 1114         est_get_id16(&saved_id16);
 1115         for (i = 0, j = 0; i < count; i++) {
 1116                 /*
 1117                  * Confirm id16 value is correct.
 1118                  */
 1119                 if (sets[i].freq > 0) {
 1120                         error = est_set_id16(dev, sets[i].spec[0], 1);
 1121                         if (error != 0) {
 1122                                 if (bootverbose) 
 1123                                         device_printf(dev, "Invalid freq %u, "
 1124                                             "ignored.\n", sets[i].freq);
 1125                         } else {
 1126                                 table[j].freq = sets[i].freq;
 1127                                 table[j].volts = sets[i].volts;
 1128                                 table[j].id16 = sets[i].spec[0];
 1129                                 table[j].power = sets[i].power;
 1130                                 ++j;
 1131                         }
 1132                 }
 1133         }
 1134         /* restore saved setting */
 1135         est_set_id16(dev, saved_id16, 0);
 1136 
 1137         /* Mark end of table with a terminator. */
 1138         bzero(&table[j], sizeof(freq_info));
 1139 
 1140         sc->acpi_settings = TRUE;
 1141         *freqs = table;
 1142         error = 0;
 1143 
 1144 out:
 1145         if (sets)
 1146                 free(sets, M_TEMP);
 1147         if (error && table)
 1148                 free(table, M_DEVBUF);
 1149         return (error);
 1150 }
 1151 
 1152 static int
 1153 est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
 1154 {
 1155         cpu_info *p;
 1156         uint32_t id;
 1157 
 1158         /* Find a table which matches (vendor, id32). */
 1159         id = msr >> 32;
 1160         for (p = ESTprocs; p->id32 != 0; p++) {
 1161                 if (p->vendor_id == cpu_vendor_id && p->id32 == id)
 1162                         break;
 1163         }
 1164         if (p->id32 == 0)
 1165                 return (EOPNOTSUPP);
 1166 
 1167         /* Make sure the current setpoint is valid. */
 1168         if (est_get_current(p->freqtab) == NULL) {
 1169                 device_printf(dev, "current setting not found in table\n");
 1170                 return (EOPNOTSUPP);
 1171         }
 1172 
 1173         *freqs = p->freqtab;
 1174         return (0);
 1175 }
 1176 
 1177 static int
 1178 bus_speed_ok(int bus)
 1179 {
 1180 
 1181         switch (bus) {
 1182         case 100:
 1183         case 133:
 1184         case 333:
 1185                 return (1);
 1186         default:
 1187                 return (0);
 1188         }
 1189 }
 1190 
 1191 /*
 1192  * Flesh out a simple rate table containing the high and low frequencies
 1193  * based on the current clock speed and the upper 32 bits of the MSR.
 1194  */
 1195 static int
 1196 est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
 1197 {
 1198         struct est_softc *sc;
 1199         freq_info *fp;
 1200         int bus, freq, volts;
 1201         uint16_t id;
 1202 
 1203         if (!msr_info_enabled)
 1204                 return (EOPNOTSUPP);
 1205 
 1206         /* Figure out the bus clock. */
 1207         freq = tsc_freq / 1000000;
 1208         id = msr >> 32;
 1209         bus = freq / (id >> 8);
 1210         device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
 1211         if (!bus_speed_ok(bus)) {
 1212                 /* We may be running on the low frequency. */
 1213                 id = msr >> 48;
 1214                 bus = freq / (id >> 8);
 1215                 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
 1216                 if (!bus_speed_ok(bus))
 1217                         return (EOPNOTSUPP);
 1218                 
 1219                 /* Calculate high frequency. */
 1220                 id = msr >> 32;
 1221                 freq = ((id >> 8) & 0xff) * bus;
 1222         }
 1223 
 1224         /* Fill out a new freq table containing just the high and low freqs. */
 1225         sc = device_get_softc(dev);
 1226         fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
 1227 
 1228         /* First, the high frequency. */
 1229         volts = id & 0xff;
 1230         if (volts != 0) {
 1231                 volts <<= 4;
 1232                 volts += 700;
 1233         }
 1234         fp[0].freq = freq;
 1235         fp[0].volts = volts;
 1236         fp[0].id16 = id;
 1237         fp[0].power = CPUFREQ_VAL_UNKNOWN;
 1238         device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
 1239             volts);
 1240 
 1241         /* Second, the low frequency. */
 1242         id = msr >> 48;
 1243         freq = ((id >> 8) & 0xff) * bus;
 1244         volts = id & 0xff;
 1245         if (volts != 0) {
 1246                 volts <<= 4;
 1247                 volts += 700;
 1248         }
 1249         fp[1].freq = freq;
 1250         fp[1].volts = volts;
 1251         fp[1].id16 = id;
 1252         fp[1].power = CPUFREQ_VAL_UNKNOWN;
 1253         device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
 1254             volts);
 1255 
 1256         /* Table is already terminated due to M_ZERO. */
 1257         sc->msr_settings = TRUE;
 1258         *freqs = fp;
 1259         return (0);
 1260 }
 1261 
 1262 static void
 1263 est_get_id16(uint16_t *id16_p)
 1264 {
 1265         *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
 1266 }
 1267 
 1268 static int
 1269 est_set_id16(device_t dev, uint16_t id16, int need_check)
 1270 {
 1271         uint64_t msr;
 1272         uint16_t new_id16;
 1273         int ret = 0;
 1274 
 1275         /* Read the current register, mask out the old, set the new id. */
 1276         msr = rdmsr(MSR_PERF_CTL);
 1277         msr = (msr & ~0xffff) | id16;
 1278         wrmsr(MSR_PERF_CTL, msr);
 1279         
 1280         /* Wait a short while for the new setting.  XXX Is this necessary? */
 1281         DELAY(EST_TRANS_LAT);
 1282         
 1283         if  (need_check) {
 1284                 est_get_id16(&new_id16);                
 1285                 if (new_id16 != id16) {
 1286                         if (bootverbose) 
 1287                                 device_printf(dev, "Invalid id16 (set, cur) "
 1288                                     "= (%u, %u)\n", id16, new_id16);
 1289                         ret = ENXIO;
 1290                 }
 1291         }
 1292         return (ret);
 1293 }
 1294 
 1295 static freq_info *
 1296 est_get_current(freq_info *freq_list)
 1297 {
 1298         freq_info *f;
 1299         int i;
 1300         uint16_t id16;
 1301 
 1302         /*
 1303          * Try a few times to get a valid value.  Sometimes, if the CPU
 1304          * is in the middle of an asynchronous transition (i.e., P4TCC),
 1305          * we get a temporary invalid result.
 1306          */
 1307         for (i = 0; i < 5; i++) {
 1308                 est_get_id16(&id16);
 1309                 for (f = freq_list; f->id16 != 0; f++) {
 1310                         if (f->id16 == id16)
 1311                                 return (f);
 1312                 }
 1313                 DELAY(100);
 1314         }
 1315         return (NULL);
 1316 }
 1317 
 1318 static int
 1319 est_settings(device_t dev, struct cf_setting *sets, int *count)
 1320 {
 1321         struct est_softc *sc;
 1322         freq_info *f;
 1323         int i;
 1324 
 1325         sc = device_get_softc(dev);
 1326         if (*count < EST_MAX_SETTINGS)
 1327                 return (E2BIG);
 1328 
 1329         i = 0;
 1330         for (f = sc->freq_list; f->freq != 0; f++, i++) {
 1331                 sets[i].freq = f->freq;
 1332                 sets[i].volts = f->volts;
 1333                 sets[i].power = f->power;
 1334                 sets[i].lat = EST_TRANS_LAT;
 1335                 sets[i].dev = dev;
 1336         }
 1337         *count = i;
 1338 
 1339         return (0);
 1340 }
 1341 
 1342 static int
 1343 est_set(device_t dev, const struct cf_setting *set)
 1344 {
 1345         struct est_softc *sc;
 1346         freq_info *f;
 1347 
 1348         /* Find the setting matching the requested one. */
 1349         sc = device_get_softc(dev);
 1350         for (f = sc->freq_list; f->freq != 0; f++) {
 1351                 if (f->freq == set->freq)
 1352                         break;
 1353         }
 1354         if (f->freq == 0)
 1355                 return (EINVAL);
 1356 
 1357         /* Read the current register, mask out the old, set the new id. */
 1358         est_set_id16(dev, f->id16, 0);
 1359 
 1360         return (0);
 1361 }
 1362 
 1363 static int
 1364 est_get(device_t dev, struct cf_setting *set)
 1365 {
 1366         struct est_softc *sc;
 1367         freq_info *f;
 1368 
 1369         sc = device_get_softc(dev);
 1370         f = est_get_current(sc->freq_list);
 1371         if (f == NULL)
 1372                 return (ENXIO);
 1373 
 1374         set->freq = f->freq;
 1375         set->volts = f->volts;
 1376         set->power = f->power;
 1377         set->lat = EST_TRANS_LAT;
 1378         set->dev = dev;
 1379         return (0);
 1380 }
 1381 
 1382 static int
 1383 est_type(device_t dev, int *type)
 1384 {
 1385 
 1386         if (type == NULL)
 1387                 return (EINVAL);
 1388 
 1389         *type = CPUFREQ_TYPE_ABSOLUTE;
 1390         return (0);
 1391 }

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