Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/i386/cpufreq/hwpstate.c
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1 /*- 2 * Copyright (c) 2005 Nate Lawson 3 * Copyright (c) 2004 Colin Percival 4 * Copyright (c) 2004-2005 Bruno Durcot 5 * Copyright (c) 2004 FUKUDA Nobuhiko 6 * Copyright (c) 2009 Michael Reifenberger 7 * Copyright (c) 2009 Norikatsu Shigemura 8 * Copyright (c) 2008-2009 Gen Otsuji 9 * 10 * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c 11 * in various parts. The authors of these files are Nate Lawson, 12 * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko. 13 * This code contains patches by Michael Reifenberger and Norikatsu Shigemura. 14 * Thank you. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted providing that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 34 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * For more info: 40 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors 41 * 31116 Rev 3.20 February 04, 2009 42 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors 43 * 41256 Rev 3.00 - July 07, 2008 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD: releng/8.1/sys/i386/cpufreq/hwpstate.c 199583 2009-11-20 15:27:52Z jhb $"); 48 49 #include <sys/param.h> 50 #include <sys/bus.h> 51 #include <sys/cpu.h> 52 #include <sys/kernel.h> 53 #include <sys/module.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 #include <sys/pcpu.h> 57 #include <sys/smp.h> 58 #include <sys/sched.h> 59 60 #include <machine/md_var.h> 61 #include <machine/cputypes.h> 62 #include <machine/specialreg.h> 63 64 #include <contrib/dev/acpica/include/acpi.h> 65 66 #include <dev/acpica/acpivar.h> 67 68 #include "acpi_if.h" 69 #include "cpufreq_if.h" 70 71 #define MSR_AMD_10H_11H_LIMIT 0xc0010061 72 #define MSR_AMD_10H_11H_CONTROL 0xc0010062 73 #define MSR_AMD_10H_11H_STATUS 0xc0010063 74 #define MSR_AMD_10H_11H_CONFIG 0xc0010064 75 76 #define AMD_10H_11H_MAX_STATES 16 77 78 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */ 79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7) 80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) 81 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */ 82 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) 83 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) 84 #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) 85 86 #define HWPSTATE_DEBUG(dev, msg...) \ 87 do{ \ 88 if(hwpstate_verbose) \ 89 device_printf(dev, msg); \ 90 }while(0) 91 92 struct hwpstate_setting { 93 int freq; /* CPU clock in Mhz or 100ths of a percent. */ 94 int volts; /* Voltage in mV. */ 95 int power; /* Power consumed in mW. */ 96 int lat; /* Transition latency in us. */ 97 int pstate_id; /* P-State id */ 98 }; 99 100 struct hwpstate_softc { 101 device_t dev; 102 struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES]; 103 int cfnum; 104 }; 105 106 static void hwpstate_identify(driver_t *driver, device_t parent); 107 static int hwpstate_probe(device_t dev); 108 static int hwpstate_attach(device_t dev); 109 static int hwpstate_detach(device_t dev); 110 static int hwpstate_set(device_t dev, const struct cf_setting *cf); 111 static int hwpstate_get(device_t dev, struct cf_setting *cf); 112 static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count); 113 static int hwpstate_type(device_t dev, int *type); 114 static int hwpstate_shutdown(device_t dev); 115 static int hwpstate_features(driver_t *driver, u_int *features); 116 static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev); 117 static int hwpstate_get_info_from_msr(device_t dev); 118 static int hwpstate_goto_pstate(device_t dev, int pstate_id); 119 120 static int hwpstate_verbose = 0; 121 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RDTUN, 122 &hwpstate_verbose, 0, "Debug hwpstate"); 123 124 static device_method_t hwpstate_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_identify, hwpstate_identify), 127 DEVMETHOD(device_probe, hwpstate_probe), 128 DEVMETHOD(device_attach, hwpstate_attach), 129 DEVMETHOD(device_detach, hwpstate_detach), 130 DEVMETHOD(device_shutdown, hwpstate_shutdown), 131 132 /* cpufreq interface */ 133 DEVMETHOD(cpufreq_drv_set, hwpstate_set), 134 DEVMETHOD(cpufreq_drv_get, hwpstate_get), 135 DEVMETHOD(cpufreq_drv_settings, hwpstate_settings), 136 DEVMETHOD(cpufreq_drv_type, hwpstate_type), 137 138 /* ACPI interface */ 139 DEVMETHOD(acpi_get_features, hwpstate_features), 140 141 {0, 0} 142 }; 143 144 static devclass_t hwpstate_devclass; 145 static driver_t hwpstate_driver = { 146 "hwpstate", 147 hwpstate_methods, 148 sizeof(struct hwpstate_softc), 149 }; 150 151 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0); 152 153 /* 154 * Go to Px-state on all cpus considering the limit. 155 */ 156 static int 157 hwpstate_goto_pstate(device_t dev, int pstate) 158 { 159 struct pcpu *pc; 160 int i; 161 uint64_t msr; 162 int j; 163 int limit; 164 int id = pstate; 165 int error; 166 167 /* get the current pstate limit */ 168 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 169 limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr); 170 if(limit > id) 171 id = limit; 172 173 error = 0; 174 /* 175 * We are going to the same Px-state on all cpus. 176 */ 177 for (i = 0; i < mp_ncpus; i++) { 178 /* Find each cpu. */ 179 pc = pcpu_find(i); 180 if (pc == NULL) 181 return (ENXIO); 182 thread_lock(curthread); 183 /* Bind to each cpu. */ 184 sched_bind(curthread, pc->pc_cpuid); 185 thread_unlock(curthread); 186 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", 187 id, PCPU_GET(cpuid)); 188 /* Go To Px-state */ 189 wrmsr(MSR_AMD_10H_11H_CONTROL, id); 190 /* wait loop (100*100 usec is enough ?) */ 191 for(j = 0; j < 100; j++){ 192 msr = rdmsr(MSR_AMD_10H_11H_STATUS); 193 if(msr == id){ 194 break; 195 } 196 DELAY(100); 197 } 198 /* get the result. not assure msr=id */ 199 msr = rdmsr(MSR_AMD_10H_11H_STATUS); 200 HWPSTATE_DEBUG(dev, "result P%d-state on cpu%d\n", 201 (int)msr, PCPU_GET(cpuid)); 202 if (msr != id) { 203 HWPSTATE_DEBUG(dev, "error: loop is not enough.\n"); 204 error = ENXIO; 205 } 206 thread_lock(curthread); 207 sched_unbind(curthread); 208 thread_unlock(curthread); 209 } 210 return (error); 211 } 212 213 static int 214 hwpstate_set(device_t dev, const struct cf_setting *cf) 215 { 216 struct hwpstate_softc *sc; 217 struct hwpstate_setting *set; 218 int i; 219 220 if (cf == NULL) 221 return (EINVAL); 222 sc = device_get_softc(dev); 223 set = sc->hwpstate_settings; 224 for (i = 0; i < sc->cfnum; i++) 225 if (CPUFREQ_CMP(cf->freq, set[i].freq)) 226 break; 227 if (i == sc->cfnum) 228 return (EINVAL); 229 230 return (hwpstate_goto_pstate(dev, set[i].pstate_id)); 231 } 232 233 static int 234 hwpstate_get(device_t dev, struct cf_setting *cf) 235 { 236 struct hwpstate_softc *sc; 237 struct hwpstate_setting set; 238 uint64_t msr; 239 240 sc = device_get_softc(dev); 241 if (cf == NULL) 242 return (EINVAL); 243 msr = rdmsr(MSR_AMD_10H_11H_STATUS); 244 if(msr >= sc->cfnum) 245 return (EINVAL); 246 set = sc->hwpstate_settings[msr]; 247 248 cf->freq = set.freq; 249 cf->volts = set.volts; 250 cf->power = set.power; 251 cf->lat = set.lat; 252 cf->dev = dev; 253 return (0); 254 } 255 256 static int 257 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count) 258 { 259 struct hwpstate_softc *sc; 260 struct hwpstate_setting set; 261 int i; 262 263 if (sets == NULL || count == NULL) 264 return (EINVAL); 265 sc = device_get_softc(dev); 266 if (*count < sc->cfnum) 267 return (E2BIG); 268 for (i = 0; i < sc->cfnum; i++, sets++) { 269 set = sc->hwpstate_settings[i]; 270 sets->freq = set.freq; 271 sets->volts = set.volts; 272 sets->power = set.power; 273 sets->lat = set.lat; 274 sets->dev = dev; 275 } 276 *count = sc->cfnum; 277 278 return (0); 279 } 280 281 static int 282 hwpstate_type(device_t dev, int *type) 283 { 284 285 if (type == NULL) 286 return (EINVAL); 287 288 *type = CPUFREQ_TYPE_ABSOLUTE; 289 return (0); 290 } 291 292 static void 293 hwpstate_identify(driver_t *driver, device_t parent) 294 { 295 296 if (device_find_child(parent, "hwpstate", -1) != NULL) 297 return; 298 299 if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) 300 return; 301 302 /* 303 * Check if hardware pstate enable bit is set. 304 */ 305 if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) { 306 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n"); 307 return; 308 } 309 310 if (resource_disabled("hwpstate", 0)) 311 return; 312 313 if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL) 314 device_printf(parent, "hwpstate: add child failed\n"); 315 } 316 317 static int 318 hwpstate_probe(device_t dev) 319 { 320 struct hwpstate_softc *sc; 321 device_t perf_dev; 322 uint64_t msr; 323 int error, type; 324 325 /* 326 * Only hwpstate0. 327 * It goes well with acpi_throttle. 328 */ 329 if (device_get_unit(dev) != 0) 330 return (ENXIO); 331 332 sc = device_get_softc(dev); 333 sc->dev = dev; 334 335 /* 336 * Check if acpi_perf has INFO only flag. 337 */ 338 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 339 error = TRUE; 340 if (perf_dev && device_is_attached(perf_dev)) { 341 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 342 if (error == 0) { 343 if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) { 344 /* 345 * If acpi_perf doesn't have INFO_ONLY flag, 346 * it will take care of pstate transitions. 347 */ 348 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n"); 349 return (ENXIO); 350 } else { 351 /* 352 * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW) 353 * we can get _PSS info from acpi_perf 354 * without going into ACPI. 355 */ 356 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n"); 357 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev); 358 } 359 } 360 } 361 362 if (error == 0) { 363 /* 364 * Now we get _PSS info from acpi_perf without error. 365 * Let's check it. 366 */ 367 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 368 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) { 369 HWPSTATE_DEBUG(dev, "msr and acpi _PSS count mismatch.\n"); 370 error = TRUE; 371 } 372 } 373 374 /* 375 * If we cannot get info from acpi_perf, 376 * Let's get info from MSRs. 377 */ 378 if (error) 379 error = hwpstate_get_info_from_msr(dev); 380 if (error) 381 return (error); 382 383 device_set_desc(dev, "Cool`n'Quiet 2.0"); 384 return (0); 385 } 386 387 static int 388 hwpstate_attach(device_t dev) 389 { 390 391 return (cpufreq_register(dev)); 392 } 393 394 static int 395 hwpstate_get_info_from_msr(device_t dev) 396 { 397 struct hwpstate_softc *sc; 398 struct hwpstate_setting *hwpstate_set; 399 uint64_t msr; 400 int family, i, fid, did; 401 402 family = CPUID_TO_FAMILY(cpu_id); 403 sc = device_get_softc(dev); 404 /* Get pstate count */ 405 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 406 sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr); 407 hwpstate_set = sc->hwpstate_settings; 408 for (i = 0; i < sc->cfnum; i++) { 409 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); 410 if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) { 411 HWPSTATE_DEBUG(dev, "msr is not valid.\n"); 412 return (ENXIO); 413 } 414 did = AMD_10H_11H_CUR_DID(msr); 415 fid = AMD_10H_11H_CUR_FID(msr); 416 switch(family) { 417 case 0x11: 418 /* fid/did to frequency */ 419 hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did); 420 break; 421 case 0x10: 422 /* fid/did to frequency */ 423 hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did); 424 break; 425 default: 426 HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family); 427 return (ENXIO); 428 break; 429 } 430 hwpstate_set[i].pstate_id = i; 431 /* There was volts calculation, but deleted it. */ 432 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN; 433 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN; 434 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN; 435 } 436 return (0); 437 } 438 439 static int 440 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev) 441 { 442 struct hwpstate_softc *sc; 443 struct cf_setting *perf_set; 444 struct hwpstate_setting *hwpstate_set; 445 int count, error, i; 446 447 perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT); 448 if (perf_set == NULL) { 449 HWPSTATE_DEBUG(dev, "nomem\n"); 450 return (ENOMEM); 451 } 452 /* 453 * Fetch settings from acpi_perf. 454 * Now it is attached, and has info only flag. 455 */ 456 count = MAX_SETTINGS; 457 error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count); 458 if (error) { 459 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n"); 460 goto out; 461 } 462 sc = device_get_softc(dev); 463 sc->cfnum = count; 464 hwpstate_set = sc->hwpstate_settings; 465 for (i = 0; i < count; i++) { 466 if (i == perf_set[i].spec[0]) { 467 hwpstate_set[i].pstate_id = i; 468 hwpstate_set[i].freq = perf_set[i].freq; 469 hwpstate_set[i].volts = perf_set[i].volts; 470 hwpstate_set[i].power = perf_set[i].power; 471 hwpstate_set[i].lat = perf_set[i].lat; 472 } else { 473 HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n"); 474 error = ENXIO; 475 goto out; 476 } 477 } 478 out: 479 if (perf_set) 480 free(perf_set, M_TEMP); 481 return (error); 482 } 483 484 static int 485 hwpstate_detach(device_t dev) 486 { 487 488 hwpstate_goto_pstate(dev, 0); 489 return (cpufreq_unregister(dev)); 490 } 491 492 static int 493 hwpstate_shutdown(device_t dev) 494 { 495 496 /* hwpstate_goto_pstate(dev, 0); */ 497 return (0); 498 } 499 500 static int 501 hwpstate_features(driver_t *driver, u_int *features) 502 { 503 504 /* Notify the ACPI CPU that we support direct access to MSRs */ 505 *features = ACPI_CAP_PERF_MSRS; 506 return (0); 507 }
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