The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/cpufreq/p4tcc.c

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    1 /*-
    2  * Copyright (c) 2005 Nate Lawson
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Throttle clock frequency by using the thermal control circuit.  This
   29  * operates independently of SpeedStep and ACPI throttling and is supported
   30  * on Pentium 4 and later models (feature TM).
   31  *
   32  * Reference:  Intel Developer's manual v.3 #245472-012
   33  *
   34  * The original version of this driver was written by Ted Unangst for
   35  * OpenBSD and imported by Maxim Sobolev.  It was rewritten by Nate Lawson
   36  * for use with the cpufreq framework.
   37  */
   38 
   39 #include <sys/cdefs.h>
   40 __FBSDID("$FreeBSD: src/sys/i386/cpufreq/p4tcc.c,v 1.11.4.1 2005/07/21 09:20:10 bruno Exp $");
   41 
   42 #include <sys/param.h>
   43 #include <sys/systm.h>
   44 #include <sys/bus.h>
   45 #include <sys/cpu.h>
   46 #include <sys/kernel.h>
   47 #include <sys/module.h>
   48 
   49 #include <machine/md_var.h>
   50 #include <machine/specialreg.h>
   51 
   52 #include "cpufreq_if.h"
   53 
   54 #include <contrib/dev/acpica/acpi.h>
   55 #include <dev/acpica/acpivar.h>
   56 #include "acpi_if.h"
   57  
   58 struct p4tcc_softc {
   59         device_t        dev;
   60         int             set_count;
   61         int             lowest_val;
   62         int             auto_mode;
   63 };
   64 
   65 #define TCC_NUM_SETTINGS        8
   66 
   67 #define TCC_ENABLE_ONDEMAND     (1<<4)
   68 #define TCC_REG_OFFSET          1
   69 #define TCC_SPEED_PERCENT(x)    ((10000 * (x)) / TCC_NUM_SETTINGS)
   70 
   71 static int      p4tcc_features(driver_t *driver, u_int *features);
   72 static void     p4tcc_identify(driver_t *driver, device_t parent);
   73 static int      p4tcc_probe(device_t dev);
   74 static int      p4tcc_attach(device_t dev);
   75 static int      p4tcc_settings(device_t dev, struct cf_setting *sets,
   76                     int *count);
   77 static int      p4tcc_set(device_t dev, const struct cf_setting *set);
   78 static int      p4tcc_get(device_t dev, struct cf_setting *set);
   79 static int      p4tcc_type(device_t dev, int *type);
   80 
   81 static device_method_t p4tcc_methods[] = {
   82         /* Device interface */
   83         DEVMETHOD(device_identify,      p4tcc_identify),
   84         DEVMETHOD(device_probe,         p4tcc_probe),
   85         DEVMETHOD(device_attach,        p4tcc_attach),
   86 
   87         /* cpufreq interface */
   88         DEVMETHOD(cpufreq_drv_set,      p4tcc_set),
   89         DEVMETHOD(cpufreq_drv_get,      p4tcc_get),
   90         DEVMETHOD(cpufreq_drv_type,     p4tcc_type),
   91         DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
   92 
   93         /* ACPI interface */
   94         DEVMETHOD(acpi_get_features,    p4tcc_features),
   95 
   96         {0, 0}
   97 };
   98 
   99 static driver_t p4tcc_driver = {
  100         "p4tcc",
  101         p4tcc_methods,
  102         sizeof(struct p4tcc_softc),
  103 };
  104 
  105 static devclass_t p4tcc_devclass;
  106 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
  107 
  108 static int
  109 p4tcc_features(driver_t *driver, u_int *features)
  110 {
  111 
  112         /* Notify the ACPI CPU that we support direct access to MSRs */
  113         *features = ACPI_CAP_THR_MSRS;
  114         return (0);
  115 }
  116 
  117 static void
  118 p4tcc_identify(driver_t *driver, device_t parent)
  119 {
  120 
  121         if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
  122                 return;
  123 
  124         /* Make sure we're not being doubly invoked. */
  125         if (device_find_child(parent, "p4tcc", -1) != NULL)
  126                 return;
  127 
  128         /*
  129          * We attach a p4tcc child for every CPU since settings need to
  130          * be performed on every CPU in the SMP case.  See section 13.15.3
  131          * of the IA32 Intel Architecture Software Developer's Manual,
  132          * Volume 3, for more info.
  133          */
  134         if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL)
  135                 device_printf(parent, "add p4tcc child failed\n");
  136 }
  137 
  138 static int
  139 p4tcc_probe(device_t dev)
  140 {
  141 
  142         if (resource_disabled("p4tcc", 0))
  143                 return (ENXIO);
  144 
  145         device_set_desc(dev, "CPU Frequency Thermal Control");
  146         return (0);
  147 }
  148 
  149 static int
  150 p4tcc_attach(device_t dev)
  151 {
  152         struct p4tcc_softc *sc;
  153 
  154         sc = device_get_softc(dev);
  155         sc->dev = dev;
  156         sc->set_count = TCC_NUM_SETTINGS;
  157 
  158         /*
  159          * On boot, the TCC is usually in Automatic mode where reading the
  160          * current performance level is likely to produce bogus results.
  161          * We record that state here and don't trust the contents of the
  162          * status MSR until we've set it ourselves.
  163          */
  164         sc->auto_mode = TRUE;
  165 
  166         switch (cpu_id & 0xf) {
  167         case 0x22:
  168         case 0x24:
  169         case 0x25:
  170         case 0x27:
  171         case 0x29:
  172                 /*
  173                  * These CPU models hang when set to 12.5%.
  174                  * See Errata O50, P44, and Z21.
  175                  */
  176                 sc->set_count -= 1;
  177                 break;
  178         case 0x07:      /* errata N44 and P18 */
  179         case 0x0a:
  180         case 0x12:
  181         case 0x13:
  182                 /*
  183                  * These CPU models hang when set to 12.5% or 25%.
  184                  * See Errata N44 and P18l.
  185                  */
  186                 sc->set_count -= 2;
  187                 break;
  188         }
  189         sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
  190 
  191         cpufreq_register(dev);
  192         return (0);
  193 }
  194 
  195 static int
  196 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
  197 {
  198         struct p4tcc_softc *sc;
  199         int i, val;
  200 
  201         sc = device_get_softc(dev);
  202         if (sets == NULL || count == NULL)
  203                 return (EINVAL);
  204         if (*count < sc->set_count)
  205                 return (E2BIG);
  206 
  207         /* Return a list of valid settings for this driver. */
  208         memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
  209         val = TCC_NUM_SETTINGS;
  210         for (i = 0; i < sc->set_count; i++, val--) {
  211                 sets[i].freq = TCC_SPEED_PERCENT(val);
  212                 sets[i].dev = dev;
  213         }
  214         *count = sc->set_count;
  215 
  216         return (0);
  217 }
  218 
  219 static int
  220 p4tcc_set(device_t dev, const struct cf_setting *set)
  221 {
  222         struct p4tcc_softc *sc;
  223         uint64_t mask, msr;
  224         int val;
  225 
  226         if (set == NULL)
  227                 return (EINVAL);
  228         sc = device_get_softc(dev);
  229 
  230         /*
  231          * Validate requested state converts to a setting that is an integer
  232          * from [sc->lowest_val .. TCC_NUM_SETTINGS].
  233          */
  234         val = set->freq * TCC_NUM_SETTINGS / 10000;
  235         if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
  236             val < sc->lowest_val || val > TCC_NUM_SETTINGS)
  237                 return (EINVAL);
  238 
  239         /*
  240          * Read the current register and mask off the old setting and
  241          * On-Demand bit.  If the new val is < 100%, set it and the On-Demand
  242          * bit, otherwise just return to Automatic mode.
  243          */
  244         msr = rdmsr(MSR_THERM_CONTROL);
  245         mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
  246         msr &= ~(mask | TCC_ENABLE_ONDEMAND);
  247         if (val < TCC_NUM_SETTINGS)
  248                 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
  249         wrmsr(MSR_THERM_CONTROL, msr);
  250 
  251         /*
  252          * Record whether we're now in Automatic or On-Demand mode.  We have
  253          * to cache this since there is no reliable way to check if TCC is in
  254          * Automatic mode (i.e., at 100% or possibly 50%).  Reading bit 4 of
  255          * the ACPI Thermal Monitor Control Register produces 0 no matter
  256          * what the current mode.
  257          */
  258         if (msr & TCC_ENABLE_ONDEMAND)
  259                 sc->auto_mode = TRUE;
  260         else
  261                 sc->auto_mode = FALSE;
  262 
  263         return (0);
  264 }
  265 
  266 static int
  267 p4tcc_get(device_t dev, struct cf_setting *set)
  268 {
  269         struct p4tcc_softc *sc;
  270         uint64_t msr;
  271         int val;
  272 
  273         if (set == NULL)
  274                 return (EINVAL);
  275         sc = device_get_softc(dev);
  276 
  277         /*
  278          * Read the current register and extract the current setting.  If
  279          * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
  280          *
  281          * XXX This is not completely reliable since at high temperatures
  282          * the CPU may be automatically throttling to 50% but it's the best
  283          * we can do.
  284          */
  285         if (!sc->auto_mode) {
  286                 msr = rdmsr(MSR_THERM_CONTROL);
  287                 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
  288         } else
  289                 val = TCC_NUM_SETTINGS;
  290 
  291         memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
  292         set->freq = TCC_SPEED_PERCENT(val);
  293         set->dev = dev;
  294 
  295         return (0);
  296 }
  297 
  298 static int
  299 p4tcc_type(device_t dev, int *type)
  300 {
  301 
  302         if (type == NULL)
  303                 return (EINVAL);
  304 
  305         *type = CPUFREQ_TYPE_RELATIVE;
  306         return (0);
  307 }

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