The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/cpufreq/p4tcc.c

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    1 /*-
    2  * Copyright (c) 2005 Nate Lawson
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Throttle clock frequency by using the thermal control circuit.  This
   29  * operates independently of SpeedStep and ACPI throttling and is supported
   30  * on Pentium 4 and later models (feature TM).
   31  *
   32  * Reference:  Intel Developer's manual v.3 #245472-012
   33  *
   34  * The original version of this driver was written by Ted Unangst for
   35  * OpenBSD and imported by Maxim Sobolev.  It was rewritten by Nate Lawson
   36  * for use with the cpufreq framework.
   37  */
   38 
   39 #include <sys/cdefs.h>
   40 __FBSDID("$FreeBSD: releng/6.0/sys/i386/cpufreq/p4tcc.c 151675 2005-10-25 20:53:22Z njl $");
   41 
   42 #include <sys/param.h>
   43 #include <sys/systm.h>
   44 #include <sys/bus.h>
   45 #include <sys/cpu.h>
   46 #include <sys/kernel.h>
   47 #include <sys/module.h>
   48 
   49 #include <machine/md_var.h>
   50 #include <machine/specialreg.h>
   51 
   52 #include "cpufreq_if.h"
   53 
   54 #include <contrib/dev/acpica/acpi.h>
   55 #include <dev/acpica/acpivar.h>
   56 #include "acpi_if.h"
   57  
   58 struct p4tcc_softc {
   59         device_t        dev;
   60         int             set_count;
   61         int             lowest_val;
   62         int             auto_mode;
   63 };
   64 
   65 #define TCC_NUM_SETTINGS        8
   66 
   67 #define TCC_ENABLE_ONDEMAND     (1<<4)
   68 #define TCC_REG_OFFSET          1
   69 #define TCC_SPEED_PERCENT(x)    ((10000 * (x)) / TCC_NUM_SETTINGS)
   70 
   71 static int      p4tcc_features(driver_t *driver, u_int *features);
   72 static void     p4tcc_identify(driver_t *driver, device_t parent);
   73 static int      p4tcc_probe(device_t dev);
   74 static int      p4tcc_attach(device_t dev);
   75 static int      p4tcc_settings(device_t dev, struct cf_setting *sets,
   76                     int *count);
   77 static int      p4tcc_set(device_t dev, const struct cf_setting *set);
   78 static int      p4tcc_get(device_t dev, struct cf_setting *set);
   79 static int      p4tcc_type(device_t dev, int *type);
   80 
   81 static device_method_t p4tcc_methods[] = {
   82         /* Device interface */
   83         DEVMETHOD(device_identify,      p4tcc_identify),
   84         DEVMETHOD(device_probe,         p4tcc_probe),
   85         DEVMETHOD(device_attach,        p4tcc_attach),
   86 
   87         /* cpufreq interface */
   88         DEVMETHOD(cpufreq_drv_set,      p4tcc_set),
   89         DEVMETHOD(cpufreq_drv_get,      p4tcc_get),
   90         DEVMETHOD(cpufreq_drv_type,     p4tcc_type),
   91         DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
   92 
   93         /* ACPI interface */
   94         DEVMETHOD(acpi_get_features,    p4tcc_features),
   95 
   96         {0, 0}
   97 };
   98 
   99 static driver_t p4tcc_driver = {
  100         "p4tcc",
  101         p4tcc_methods,
  102         sizeof(struct p4tcc_softc),
  103 };
  104 
  105 static devclass_t p4tcc_devclass;
  106 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
  107 
  108 static int
  109 p4tcc_features(driver_t *driver, u_int *features)
  110 {
  111 
  112         /* Notify the ACPI CPU that we support direct access to MSRs */
  113         *features = ACPI_CAP_THR_MSRS;
  114         return (0);
  115 }
  116 
  117 static void
  118 p4tcc_identify(driver_t *driver, device_t parent)
  119 {
  120 
  121         if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
  122                 return;
  123 
  124         /* Make sure we're not being doubly invoked. */
  125         if (device_find_child(parent, "p4tcc", -1) != NULL)
  126                 return;
  127 
  128         /*
  129          * We attach a p4tcc child for every CPU since settings need to
  130          * be performed on every CPU in the SMP case.  See section 13.15.3
  131          * of the IA32 Intel Architecture Software Developer's Manual,
  132          * Volume 3, for more info.
  133          */
  134         if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL)
  135                 device_printf(parent, "add p4tcc child failed\n");
  136 }
  137 
  138 static int
  139 p4tcc_probe(device_t dev)
  140 {
  141 
  142         if (resource_disabled("p4tcc", 0))
  143                 return (ENXIO);
  144 
  145         device_set_desc(dev, "CPU Frequency Thermal Control");
  146         return (0);
  147 }
  148 
  149 static int
  150 p4tcc_attach(device_t dev)
  151 {
  152         struct p4tcc_softc *sc;
  153         struct cf_setting set;
  154 
  155         sc = device_get_softc(dev);
  156         sc->dev = dev;
  157         sc->set_count = TCC_NUM_SETTINGS;
  158 
  159         /*
  160          * On boot, the TCC is usually in Automatic mode where reading the
  161          * current performance level is likely to produce bogus results.
  162          * We record that state here and don't trust the contents of the
  163          * status MSR until we've set it ourselves.
  164          */
  165         sc->auto_mode = TRUE;
  166 
  167         switch (cpu_id & 0xf) {
  168         case 0x22:
  169         case 0x24:
  170         case 0x25:
  171         case 0x27:
  172         case 0x29:
  173                 /*
  174                  * These CPU models hang when set to 12.5%.
  175                  * See Errata O50, P44, and Z21.
  176                  */
  177                 sc->set_count -= 1;
  178                 break;
  179         case 0x07:      /* errata N44 and P18 */
  180         case 0x0a:
  181         case 0x12:
  182         case 0x13:
  183                 /*
  184                  * These CPU models hang when set to 12.5% or 25%.
  185                  * See Errata N44 and P18l.
  186                  */
  187                 sc->set_count -= 2;
  188                 break;
  189         }
  190         sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
  191 
  192         /*
  193          * Before we finish attach, switch to 100%.  It's possible the BIOS
  194          * set us to a lower rate.  The user can override this after boot.
  195          */
  196         set.freq = 10000;
  197         p4tcc_set(dev, &set);
  198 
  199         cpufreq_register(dev);
  200         return (0);
  201 }
  202 
  203 static int
  204 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
  205 {
  206         struct p4tcc_softc *sc;
  207         int i, val;
  208 
  209         sc = device_get_softc(dev);
  210         if (sets == NULL || count == NULL)
  211                 return (EINVAL);
  212         if (*count < sc->set_count)
  213                 return (E2BIG);
  214 
  215         /* Return a list of valid settings for this driver. */
  216         memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
  217         val = TCC_NUM_SETTINGS;
  218         for (i = 0; i < sc->set_count; i++, val--) {
  219                 sets[i].freq = TCC_SPEED_PERCENT(val);
  220                 sets[i].dev = dev;
  221         }
  222         *count = sc->set_count;
  223 
  224         return (0);
  225 }
  226 
  227 static int
  228 p4tcc_set(device_t dev, const struct cf_setting *set)
  229 {
  230         struct p4tcc_softc *sc;
  231         uint64_t mask, msr;
  232         int val;
  233 
  234         if (set == NULL)
  235                 return (EINVAL);
  236         sc = device_get_softc(dev);
  237 
  238         /*
  239          * Validate requested state converts to a setting that is an integer
  240          * from [sc->lowest_val .. TCC_NUM_SETTINGS].
  241          */
  242         val = set->freq * TCC_NUM_SETTINGS / 10000;
  243         if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
  244             val < sc->lowest_val || val > TCC_NUM_SETTINGS)
  245                 return (EINVAL);
  246 
  247         /*
  248          * Read the current register and mask off the old setting and
  249          * On-Demand bit.  If the new val is < 100%, set it and the On-Demand
  250          * bit, otherwise just return to Automatic mode.
  251          */
  252         msr = rdmsr(MSR_THERM_CONTROL);
  253         mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
  254         msr &= ~(mask | TCC_ENABLE_ONDEMAND);
  255         if (val < TCC_NUM_SETTINGS)
  256                 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
  257         wrmsr(MSR_THERM_CONTROL, msr);
  258 
  259         /*
  260          * Record whether we're now in Automatic or On-Demand mode.  We have
  261          * to cache this since there is no reliable way to check if TCC is in
  262          * Automatic mode (i.e., at 100% or possibly 50%).  Reading bit 4 of
  263          * the ACPI Thermal Monitor Control Register produces 0 no matter
  264          * what the current mode.
  265          */
  266         if (msr & TCC_ENABLE_ONDEMAND)
  267                 sc->auto_mode = TRUE;
  268         else
  269                 sc->auto_mode = FALSE;
  270 
  271         return (0);
  272 }
  273 
  274 static int
  275 p4tcc_get(device_t dev, struct cf_setting *set)
  276 {
  277         struct p4tcc_softc *sc;
  278         uint64_t msr;
  279         int val;
  280 
  281         if (set == NULL)
  282                 return (EINVAL);
  283         sc = device_get_softc(dev);
  284 
  285         /*
  286          * Read the current register and extract the current setting.  If
  287          * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
  288          *
  289          * XXX This is not completely reliable since at high temperatures
  290          * the CPU may be automatically throttling to 50% but it's the best
  291          * we can do.
  292          */
  293         if (!sc->auto_mode) {
  294                 msr = rdmsr(MSR_THERM_CONTROL);
  295                 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
  296         } else
  297                 val = TCC_NUM_SETTINGS;
  298 
  299         memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
  300         set->freq = TCC_SPEED_PERCENT(val);
  301         set->dev = dev;
  302 
  303         return (0);
  304 }
  305 
  306 static int
  307 p4tcc_type(device_t dev, int *type)
  308 {
  309 
  310         if (type == NULL)
  311                 return (EINVAL);
  312 
  313         *type = CPUFREQ_TYPE_RELATIVE;
  314         return (0);
  315 }

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