1 /*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: vector.s, 386BSD 0.1 unknown origin
31 * $FreeBSD: releng/5.3/sys/i386/i386/apic_vector.s 140341 2005-01-16 08:29:13Z kensmith $
32 */
33
34 /*
35 * Interrupt entry points for external interrupts triggered by I/O APICs
36 * as well as IPI handlers.
37 */
38
39 #include <machine/asmacros.h>
40 #include <machine/apicreg.h>
41 #include <machine/smptests.h>
42
43 #include "assym.s"
44
45 /*
46 * Macros to create and destroy a trap frame.
47 */
48 #define PUSH_FRAME \
49 pushl $0 ; /* dummy error code */ \
50 pushl $0 ; /* dummy trap type */ \
51 pushal ; /* 8 ints */ \
52 pushl %ds ; /* save data and extra segments ... */ \
53 pushl %es ; \
54 pushl %fs
55
56 #define POP_FRAME \
57 popl %fs ; \
58 popl %es ; \
59 popl %ds ; \
60 popal ; \
61 addl $4+4,%esp
62
63 /*
64 * I/O Interrupt Entry Point. Rather than having one entry point for
65 * each interrupt source, we use one entry point for each 32-bit word
66 * in the ISR. The handler determines the highest bit set in the ISR,
67 * translates that into a vector, and passes the vector to the
68 * lapic_handle_intr() function.
69 */
70 #define ISR_VEC(index, vec_name) \
71 .text ; \
72 SUPERALIGN_TEXT ; \
73 IDTVEC(vec_name) ; \
74 PUSH_FRAME ; \
75 movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
76 movl %eax, %ds ; \
77 movl %eax, %es ; \
78 movl $KPSEL, %eax ; /* reload with per-CPU data segment */ \
79 movl %eax, %fs ; \
80 FAKE_MCOUNT(TF_EIP(%esp)) ; \
81 movl lapic, %edx ; /* pointer to local APIC */ \
82 movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \
83 bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
84 jz 2f ; \
85 addl $(32 * index),%eax ; \
86 1: ; \
87 pushl %eax ; /* pass the IRQ */ \
88 call lapic_handle_intr ; \
89 addl $4, %esp ; /* discard parameter */ \
90 MEXITCOUNT ; \
91 jmp doreti ; \
92 2: movl $-1, %eax ; /* send a vector of -1 */ \
93 jmp 1b
94
95 /*
96 * Handle "spurious INTerrupts".
97 * Notes:
98 * This is different than the "spurious INTerrupt" generated by an
99 * 8259 PIC for missing INTs. See the APIC documentation for details.
100 * This routine should NOT do an 'EOI' cycle.
101 */
102 .text
103 SUPERALIGN_TEXT
104 IDTVEC(spuriousint)
105
106 /* No EOI cycle used here */
107
108 iret
109
110 ISR_VEC(1, apic_isr1)
111 ISR_VEC(2, apic_isr2)
112 ISR_VEC(3, apic_isr3)
113 ISR_VEC(4, apic_isr4)
114 ISR_VEC(5, apic_isr5)
115 ISR_VEC(6, apic_isr6)
116 ISR_VEC(7, apic_isr7)
117
118 #ifdef SMP
119 /*
120 * Global address space TLB shootdown.
121 */
122 .text
123 SUPERALIGN_TEXT
124 IDTVEC(invltlb)
125 pushl %eax
126 pushl %ds
127 movl $KDSEL, %eax /* Kernel data selector */
128 movl %eax, %ds
129
130 #ifdef COUNT_XINVLTLB_HITS
131 pushl %fs
132 movl $KPSEL, %eax /* Private space selector */
133 movl %eax, %fs
134 movl PCPU(CPUID), %eax
135 popl %fs
136 incl xhits_gbl(,%eax,4)
137 #endif /* COUNT_XINVLTLB_HITS */
138
139 movl %cr3, %eax /* invalidate the TLB */
140 movl %eax, %cr3
141
142 movl lapic, %eax
143 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
144
145 lock
146 incl smp_tlb_wait
147
148 popl %ds
149 popl %eax
150 iret
151
152 /*
153 * Single page TLB shootdown
154 */
155 .text
156 SUPERALIGN_TEXT
157 IDTVEC(invlpg)
158 pushl %eax
159 pushl %ds
160 movl $KDSEL, %eax /* Kernel data selector */
161 movl %eax, %ds
162
163 #ifdef COUNT_XINVLTLB_HITS
164 pushl %fs
165 movl $KPSEL, %eax /* Private space selector */
166 movl %eax, %fs
167 movl PCPU(CPUID), %eax
168 popl %fs
169 incl xhits_pg(,%eax,4)
170 #endif /* COUNT_XINVLTLB_HITS */
171
172 movl smp_tlb_addr1, %eax
173 invlpg (%eax) /* invalidate single page */
174
175 movl lapic, %eax
176 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
177
178 lock
179 incl smp_tlb_wait
180
181 popl %ds
182 popl %eax
183 iret
184
185 /*
186 * Page range TLB shootdown.
187 */
188 .text
189 SUPERALIGN_TEXT
190 IDTVEC(invlrng)
191 pushl %eax
192 pushl %edx
193 pushl %ds
194 movl $KDSEL, %eax /* Kernel data selector */
195 movl %eax, %ds
196
197 #ifdef COUNT_XINVLTLB_HITS
198 pushl %fs
199 movl $KPSEL, %eax /* Private space selector */
200 movl %eax, %fs
201 movl PCPU(CPUID), %eax
202 popl %fs
203 incl xhits_rng(,%eax,4)
204 #endif /* COUNT_XINVLTLB_HITS */
205
206 movl smp_tlb_addr1, %edx
207 movl smp_tlb_addr2, %eax
208 1: invlpg (%edx) /* invalidate single page */
209 addl $PAGE_SIZE, %edx
210 cmpl %eax, %edx
211 jb 1b
212
213 movl lapic, %eax
214 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
215
216 lock
217 incl smp_tlb_wait
218
219 popl %ds
220 popl %edx
221 popl %eax
222 iret
223
224 /*
225 * Forward hardclock to another CPU. Pushes a clockframe and calls
226 * forwarded_hardclock().
227 */
228 .text
229 SUPERALIGN_TEXT
230 IDTVEC(ipi_intr_bitmap_handler)
231
232 PUSH_FRAME
233 movl $KDSEL, %eax /* reload with kernel's data segment */
234 movl %eax, %ds
235 movl %eax, %es
236 movl $KPSEL, %eax
237 movl %eax, %fs
238
239 movl lapic, %edx
240 movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */
241
242 FAKE_MCOUNT(TF_EIP(%esp))
243
244 pushl $0 /* XXX convert trapframe to clockframe */
245 call ipi_bitmap_handler
246 addl $4, %esp /* XXX convert clockframe to trapframe */
247 MEXITCOUNT
248 jmp doreti
249
250 /*
251 * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
252 *
253 * - Signals its receipt.
254 * - Waits for permission to restart.
255 * - Signals its restart.
256 */
257 .text
258 SUPERALIGN_TEXT
259 IDTVEC(cpustop)
260 pushl %ebp
261 movl %esp, %ebp
262 pushl %eax
263 pushl %ecx
264 pushl %edx
265 pushl %ds /* save current data segment */
266 pushl %es
267 pushl %fs
268
269 movl $KDSEL, %eax
270 movl %eax, %ds /* use KERNEL data segment */
271 movl %eax, %es
272 movl $KPSEL, %eax
273 movl %eax, %fs
274
275 movl lapic, %eax
276 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
277
278 movl PCPU(CPUID), %eax
279 imull $PCB_SIZE, %eax
280 leal CNAME(stoppcbs)(%eax), %eax
281 pushl %eax
282 call CNAME(savectx) /* Save process context */
283 addl $4, %esp
284
285 movl PCPU(CPUID), %eax
286
287 lock
288 btsl %eax, CNAME(stopped_cpus) /* stopped_cpus |= (1<<id) */
289 1:
290 btl %eax, CNAME(started_cpus) /* while (!(started_cpus & (1<<id))) */
291 jnc 1b
292
293 lock
294 btrl %eax, CNAME(started_cpus) /* started_cpus &= ~(1<<id) */
295 lock
296 btrl %eax, CNAME(stopped_cpus) /* stopped_cpus &= ~(1<<id) */
297
298 test %eax, %eax
299 jnz 2f
300
301 movl CNAME(cpustop_restartfunc), %eax
302 test %eax, %eax
303 jz 2f
304 movl $0, CNAME(cpustop_restartfunc) /* One-shot */
305
306 call *%eax
307 2:
308 popl %fs
309 popl %es
310 popl %ds /* restore previous data segment */
311 popl %edx
312 popl %ecx
313 popl %eax
314 movl %ebp, %esp
315 popl %ebp
316 iret
317
318 /*
319 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
320 *
321 * - Calls the generic rendezvous action function.
322 */
323 .text
324 SUPERALIGN_TEXT
325 IDTVEC(rendezvous)
326 PUSH_FRAME
327 movl $KDSEL, %eax
328 movl %eax, %ds /* use KERNEL data segment */
329 movl %eax, %es
330 movl $KPSEL, %eax
331 movl %eax, %fs
332
333 call smp_rendezvous_action
334
335 movl lapic, %eax
336 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
337 POP_FRAME
338 iret
339
340 /*
341 * Clean up when we lose out on the lazy context switch optimization.
342 * ie: when we are about to release a PTD but a cpu is still borrowing it.
343 */
344 SUPERALIGN_TEXT
345 IDTVEC(lazypmap)
346 PUSH_FRAME
347 movl $KDSEL, %eax
348 movl %eax, %ds /* use KERNEL data segment */
349 movl %eax, %es
350 movl $KPSEL, %eax
351 movl %eax, %fs
352
353 call pmap_lazyfix_action
354
355 movl lapic, %eax
356 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
357 POP_FRAME
358 iret
359 #endif /* SMP */
Cache object: bacc1e9f85722233987baf77c391bf33
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