1 /*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: vector.s, 386BSD 0.1 unknown origin
31 * $FreeBSD: releng/8.0/sys/i386/i386/apic_vector.s 184113 2008-10-21 08:01:19Z kmacy $
32 */
33
34 /*
35 * Interrupt entry points for external interrupts triggered by I/O APICs
36 * as well as IPI handlers.
37 */
38
39 #include "opt_smp.h"
40
41 #include <machine/asmacros.h>
42 #include <machine/apicreg.h>
43
44 #include "assym.s"
45
46 /*
47 * I/O Interrupt Entry Point. Rather than having one entry point for
48 * each interrupt source, we use one entry point for each 32-bit word
49 * in the ISR. The handler determines the highest bit set in the ISR,
50 * translates that into a vector, and passes the vector to the
51 * lapic_handle_intr() function.
52 */
53 #define ISR_VEC(index, vec_name) \
54 .text ; \
55 SUPERALIGN_TEXT ; \
56 IDTVEC(vec_name) ; \
57 PUSH_FRAME ; \
58 SET_KERNEL_SREGS ; \
59 FAKE_MCOUNT(TF_EIP(%esp)) ; \
60 movl lapic, %edx ; /* pointer to local APIC */ \
61 movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \
62 bsrl %eax, %eax ; /* index of highset set bit in ISR */ \
63 jz 2f ; \
64 addl $(32 * index),%eax ; \
65 1: ; \
66 pushl %esp ; \
67 pushl %eax ; /* pass the IRQ */ \
68 call lapic_handle_intr ; \
69 addl $8, %esp ; /* discard parameter */ \
70 MEXITCOUNT ; \
71 jmp doreti ; \
72 2: movl $-1, %eax ; /* send a vector of -1 */ \
73 jmp 1b
74
75 /*
76 * Handle "spurious INTerrupts".
77 * Notes:
78 * This is different than the "spurious INTerrupt" generated by an
79 * 8259 PIC for missing INTs. See the APIC documentation for details.
80 * This routine should NOT do an 'EOI' cycle.
81 */
82 .text
83 SUPERALIGN_TEXT
84 IDTVEC(spuriousint)
85
86 /* No EOI cycle used here */
87
88 iret
89
90 ISR_VEC(1, apic_isr1)
91 ISR_VEC(2, apic_isr2)
92 ISR_VEC(3, apic_isr3)
93 ISR_VEC(4, apic_isr4)
94 ISR_VEC(5, apic_isr5)
95 ISR_VEC(6, apic_isr6)
96 ISR_VEC(7, apic_isr7)
97
98 /*
99 * Local APIC periodic timer handler.
100 */
101 .text
102 SUPERALIGN_TEXT
103 IDTVEC(timerint)
104 PUSH_FRAME
105 SET_KERNEL_SREGS
106 FAKE_MCOUNT(TF_EIP(%esp))
107 pushl %esp
108 call lapic_handle_timer
109 add $4, %esp
110 MEXITCOUNT
111 jmp doreti
112
113 #ifdef SMP
114 /*
115 * Global address space TLB shootdown.
116 */
117 .text
118 SUPERALIGN_TEXT
119 IDTVEC(invltlb)
120 pushl %eax
121 pushl %ds
122 movl $KDSEL, %eax /* Kernel data selector */
123 movl %eax, %ds
124
125 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
126 pushl %fs
127 movl $KPSEL, %eax /* Private space selector */
128 movl %eax, %fs
129 movl PCPU(CPUID), %eax
130 popl %fs
131 #ifdef COUNT_XINVLTLB_HITS
132 incl xhits_gbl(,%eax,4)
133 #endif
134 #ifdef COUNT_IPIS
135 movl ipi_invltlb_counts(,%eax,4),%eax
136 incl (%eax)
137 #endif
138 #endif
139
140 movl %cr3, %eax /* invalidate the TLB */
141 movl %eax, %cr3
142
143 movl lapic, %eax
144 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
145
146 lock
147 incl smp_tlb_wait
148
149 popl %ds
150 popl %eax
151 iret
152
153 /*
154 * Single page TLB shootdown
155 */
156 .text
157 SUPERALIGN_TEXT
158 IDTVEC(invlpg)
159 pushl %eax
160 pushl %ds
161 movl $KDSEL, %eax /* Kernel data selector */
162 movl %eax, %ds
163
164 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
165 pushl %fs
166 movl $KPSEL, %eax /* Private space selector */
167 movl %eax, %fs
168 movl PCPU(CPUID), %eax
169 popl %fs
170 #ifdef COUNT_XINVLTLB_HITS
171 incl xhits_pg(,%eax,4)
172 #endif
173 #ifdef COUNT_IPIS
174 movl ipi_invlpg_counts(,%eax,4),%eax
175 incl (%eax)
176 #endif
177 #endif
178
179 movl smp_tlb_addr1, %eax
180 invlpg (%eax) /* invalidate single page */
181
182 movl lapic, %eax
183 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
184
185 lock
186 incl smp_tlb_wait
187
188 popl %ds
189 popl %eax
190 iret
191
192 /*
193 * Page range TLB shootdown.
194 */
195 .text
196 SUPERALIGN_TEXT
197 IDTVEC(invlrng)
198 pushl %eax
199 pushl %edx
200 pushl %ds
201 movl $KDSEL, %eax /* Kernel data selector */
202 movl %eax, %ds
203
204 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
205 pushl %fs
206 movl $KPSEL, %eax /* Private space selector */
207 movl %eax, %fs
208 movl PCPU(CPUID), %eax
209 popl %fs
210 #ifdef COUNT_XINVLTLB_HITS
211 incl xhits_rng(,%eax,4)
212 #endif
213 #ifdef COUNT_IPIS
214 movl ipi_invlrng_counts(,%eax,4),%eax
215 incl (%eax)
216 #endif
217 #endif
218
219 movl smp_tlb_addr1, %edx
220 movl smp_tlb_addr2, %eax
221 1: invlpg (%edx) /* invalidate single page */
222 addl $PAGE_SIZE, %edx
223 cmpl %eax, %edx
224 jb 1b
225
226 movl lapic, %eax
227 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
228
229 lock
230 incl smp_tlb_wait
231
232 popl %ds
233 popl %edx
234 popl %eax
235 iret
236
237 /*
238 * Invalidate cache.
239 */
240 .text
241 SUPERALIGN_TEXT
242 IDTVEC(invlcache)
243 pushl %eax
244 pushl %ds
245 movl $KDSEL, %eax /* Kernel data selector */
246 movl %eax, %ds
247
248 #ifdef COUNT_IPIS
249 pushl %fs
250 movl $KPSEL, %eax /* Private space selector */
251 movl %eax, %fs
252 movl PCPU(CPUID), %eax
253 popl %fs
254 movl ipi_invlcache_counts(,%eax,4),%eax
255 incl (%eax)
256 #endif
257
258 wbinvd
259
260 movl lapic, %eax
261 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
262
263 lock
264 incl smp_tlb_wait
265
266 popl %ds
267 popl %eax
268 iret
269
270 /*
271 * Handler for IPIs sent via the per-cpu IPI bitmap.
272 */
273 #ifndef XEN
274 .text
275 SUPERALIGN_TEXT
276 IDTVEC(ipi_intr_bitmap_handler)
277 PUSH_FRAME
278 SET_KERNEL_SREGS
279
280 movl lapic, %edx
281 movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */
282
283 FAKE_MCOUNT(TF_EIP(%esp))
284
285 call ipi_bitmap_handler
286 MEXITCOUNT
287 jmp doreti
288 #endif
289 /*
290 * Executed by a CPU when it receives an IPI_STOP from another CPU.
291 */
292 .text
293 SUPERALIGN_TEXT
294 IDTVEC(cpustop)
295 PUSH_FRAME
296 SET_KERNEL_SREGS
297
298 movl lapic, %eax
299 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
300
301 call cpustop_handler
302
303 POP_FRAME
304 iret
305
306 /*
307 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
308 *
309 * - Calls the generic rendezvous action function.
310 */
311 .text
312 SUPERALIGN_TEXT
313 IDTVEC(rendezvous)
314 PUSH_FRAME
315 SET_KERNEL_SREGS
316
317 #ifdef COUNT_IPIS
318 movl PCPU(CPUID), %eax
319 movl ipi_rendezvous_counts(,%eax,4), %eax
320 incl (%eax)
321 #endif
322 call smp_rendezvous_action
323
324 movl lapic, %eax
325 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
326 POP_FRAME
327 iret
328
329 /*
330 * Clean up when we lose out on the lazy context switch optimization.
331 * ie: when we are about to release a PTD but a cpu is still borrowing it.
332 */
333 SUPERALIGN_TEXT
334 IDTVEC(lazypmap)
335 PUSH_FRAME
336 SET_KERNEL_SREGS
337
338 call pmap_lazyfix_action
339
340 movl lapic, %eax
341 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
342 POP_FRAME
343 iret
344 #endif /* SMP */
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