1 /*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: vector.s, 386BSD 0.1 unknown origin
31 * $FreeBSD: releng/9.0/sys/i386/i386/apic_vector.s 217360 2011-01-13 17:00:22Z jhb $
32 */
33
34 /*
35 * Interrupt entry points for external interrupts triggered by I/O APICs
36 * as well as IPI handlers.
37 */
38
39 #include "opt_smp.h"
40
41 #include <machine/asmacros.h>
42 #include <x86/apicreg.h>
43
44 #include "assym.s"
45
46 /*
47 * I/O Interrupt Entry Point. Rather than having one entry point for
48 * each interrupt source, we use one entry point for each 32-bit word
49 * in the ISR. The handler determines the highest bit set in the ISR,
50 * translates that into a vector, and passes the vector to the
51 * lapic_handle_intr() function.
52 */
53 #define ISR_VEC(index, vec_name) \
54 .text ; \
55 SUPERALIGN_TEXT ; \
56 IDTVEC(vec_name) ; \
57 PUSH_FRAME ; \
58 SET_KERNEL_SREGS ; \
59 cld ; \
60 FAKE_MCOUNT(TF_EIP(%esp)) ; \
61 movl lapic, %edx ; /* pointer to local APIC */ \
62 movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \
63 bsrl %eax, %eax ; /* index of highest set bit in ISR */ \
64 jz 1f ; \
65 addl $(32 * index),%eax ; \
66 pushl %esp ; \
67 pushl %eax ; /* pass the IRQ */ \
68 call lapic_handle_intr ; \
69 addl $8, %esp ; /* discard parameter */ \
70 1: ; \
71 MEXITCOUNT ; \
72 jmp doreti
73
74 /*
75 * Handle "spurious INTerrupts".
76 * Notes:
77 * This is different than the "spurious INTerrupt" generated by an
78 * 8259 PIC for missing INTs. See the APIC documentation for details.
79 * This routine should NOT do an 'EOI' cycle.
80 */
81 .text
82 SUPERALIGN_TEXT
83 IDTVEC(spuriousint)
84
85 /* No EOI cycle used here */
86
87 iret
88
89 ISR_VEC(1, apic_isr1)
90 ISR_VEC(2, apic_isr2)
91 ISR_VEC(3, apic_isr3)
92 ISR_VEC(4, apic_isr4)
93 ISR_VEC(5, apic_isr5)
94 ISR_VEC(6, apic_isr6)
95 ISR_VEC(7, apic_isr7)
96
97 /*
98 * Local APIC periodic timer handler.
99 */
100 .text
101 SUPERALIGN_TEXT
102 IDTVEC(timerint)
103 PUSH_FRAME
104 SET_KERNEL_SREGS
105 cld
106 FAKE_MCOUNT(TF_EIP(%esp))
107 pushl %esp
108 call lapic_handle_timer
109 add $4, %esp
110 MEXITCOUNT
111 jmp doreti
112
113 /*
114 * Local APIC CMCI handler.
115 */
116 .text
117 SUPERALIGN_TEXT
118 IDTVEC(cmcint)
119 PUSH_FRAME
120 SET_KERNEL_SREGS
121 cld
122 FAKE_MCOUNT(TF_EIP(%esp))
123 call lapic_handle_cmc
124 MEXITCOUNT
125 jmp doreti
126
127 /*
128 * Local APIC error interrupt handler.
129 */
130 .text
131 SUPERALIGN_TEXT
132 IDTVEC(errorint)
133 PUSH_FRAME
134 SET_KERNEL_SREGS
135 cld
136 FAKE_MCOUNT(TF_EIP(%esp))
137 call lapic_handle_error
138 MEXITCOUNT
139 jmp doreti
140
141 #ifdef SMP
142 /*
143 * Global address space TLB shootdown.
144 */
145 .text
146 SUPERALIGN_TEXT
147 IDTVEC(invltlb)
148 pushl %eax
149 pushl %ds
150 movl $KDSEL, %eax /* Kernel data selector */
151 movl %eax, %ds
152
153 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
154 pushl %fs
155 movl $KPSEL, %eax /* Private space selector */
156 movl %eax, %fs
157 movl PCPU(CPUID), %eax
158 popl %fs
159 #ifdef COUNT_XINVLTLB_HITS
160 incl xhits_gbl(,%eax,4)
161 #endif
162 #ifdef COUNT_IPIS
163 movl ipi_invltlb_counts(,%eax,4),%eax
164 incl (%eax)
165 #endif
166 #endif
167
168 movl %cr3, %eax /* invalidate the TLB */
169 movl %eax, %cr3
170
171 movl lapic, %eax
172 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
173
174 lock
175 incl smp_tlb_wait
176
177 popl %ds
178 popl %eax
179 iret
180
181 /*
182 * Single page TLB shootdown
183 */
184 .text
185 SUPERALIGN_TEXT
186 IDTVEC(invlpg)
187 pushl %eax
188 pushl %ds
189 movl $KDSEL, %eax /* Kernel data selector */
190 movl %eax, %ds
191
192 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
193 pushl %fs
194 movl $KPSEL, %eax /* Private space selector */
195 movl %eax, %fs
196 movl PCPU(CPUID), %eax
197 popl %fs
198 #ifdef COUNT_XINVLTLB_HITS
199 incl xhits_pg(,%eax,4)
200 #endif
201 #ifdef COUNT_IPIS
202 movl ipi_invlpg_counts(,%eax,4),%eax
203 incl (%eax)
204 #endif
205 #endif
206
207 movl smp_tlb_addr1, %eax
208 invlpg (%eax) /* invalidate single page */
209
210 movl lapic, %eax
211 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
212
213 lock
214 incl smp_tlb_wait
215
216 popl %ds
217 popl %eax
218 iret
219
220 /*
221 * Page range TLB shootdown.
222 */
223 .text
224 SUPERALIGN_TEXT
225 IDTVEC(invlrng)
226 pushl %eax
227 pushl %edx
228 pushl %ds
229 movl $KDSEL, %eax /* Kernel data selector */
230 movl %eax, %ds
231
232 #if defined(COUNT_XINVLTLB_HITS) || defined(COUNT_IPIS)
233 pushl %fs
234 movl $KPSEL, %eax /* Private space selector */
235 movl %eax, %fs
236 movl PCPU(CPUID), %eax
237 popl %fs
238 #ifdef COUNT_XINVLTLB_HITS
239 incl xhits_rng(,%eax,4)
240 #endif
241 #ifdef COUNT_IPIS
242 movl ipi_invlrng_counts(,%eax,4),%eax
243 incl (%eax)
244 #endif
245 #endif
246
247 movl smp_tlb_addr1, %edx
248 movl smp_tlb_addr2, %eax
249 1: invlpg (%edx) /* invalidate single page */
250 addl $PAGE_SIZE, %edx
251 cmpl %eax, %edx
252 jb 1b
253
254 movl lapic, %eax
255 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
256
257 lock
258 incl smp_tlb_wait
259
260 popl %ds
261 popl %edx
262 popl %eax
263 iret
264
265 /*
266 * Invalidate cache.
267 */
268 .text
269 SUPERALIGN_TEXT
270 IDTVEC(invlcache)
271 pushl %eax
272 pushl %ds
273 movl $KDSEL, %eax /* Kernel data selector */
274 movl %eax, %ds
275
276 #ifdef COUNT_IPIS
277 pushl %fs
278 movl $KPSEL, %eax /* Private space selector */
279 movl %eax, %fs
280 movl PCPU(CPUID), %eax
281 popl %fs
282 movl ipi_invlcache_counts(,%eax,4),%eax
283 incl (%eax)
284 #endif
285
286 wbinvd
287
288 movl lapic, %eax
289 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
290
291 lock
292 incl smp_tlb_wait
293
294 popl %ds
295 popl %eax
296 iret
297
298 /*
299 * Handler for IPIs sent via the per-cpu IPI bitmap.
300 */
301 #ifndef XEN
302 .text
303 SUPERALIGN_TEXT
304 IDTVEC(ipi_intr_bitmap_handler)
305 PUSH_FRAME
306 SET_KERNEL_SREGS
307 cld
308
309 movl lapic, %edx
310 movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */
311
312 FAKE_MCOUNT(TF_EIP(%esp))
313
314 call ipi_bitmap_handler
315 MEXITCOUNT
316 jmp doreti
317 #endif
318 /*
319 * Executed by a CPU when it receives an IPI_STOP from another CPU.
320 */
321 .text
322 SUPERALIGN_TEXT
323 IDTVEC(cpustop)
324 PUSH_FRAME
325 SET_KERNEL_SREGS
326 cld
327
328 movl lapic, %eax
329 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
330
331 call cpustop_handler
332
333 POP_FRAME
334 iret
335
336 /*
337 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
338 *
339 * - Calls the generic rendezvous action function.
340 */
341 .text
342 SUPERALIGN_TEXT
343 IDTVEC(rendezvous)
344 PUSH_FRAME
345 SET_KERNEL_SREGS
346 cld
347
348 #ifdef COUNT_IPIS
349 movl PCPU(CPUID), %eax
350 movl ipi_rendezvous_counts(,%eax,4), %eax
351 incl (%eax)
352 #endif
353 call smp_rendezvous_action
354
355 movl lapic, %eax
356 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
357 POP_FRAME
358 iret
359
360 /*
361 * Clean up when we lose out on the lazy context switch optimization.
362 * ie: when we are about to release a PTD but a cpu is still borrowing it.
363 */
364 SUPERALIGN_TEXT
365 IDTVEC(lazypmap)
366 PUSH_FRAME
367 SET_KERNEL_SREGS
368 cld
369
370 call pmap_lazyfix_action
371
372 movl lapic, %eax
373 movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */
374 POP_FRAME
375 iret
376 #endif /* SMP */
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