1 /*-
2 * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/7.3/sys/i386/i386/i686_mem.c 195667 2009-07-13 22:13:13Z jkim $");
29
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/memrange.h>
35 #include <sys/smp.h>
36 #include <sys/sysctl.h>
37
38 #include <machine/cputypes.h>
39 #include <machine/md_var.h>
40 #include <machine/specialreg.h>
41
42 /*
43 * i686 memory range operations
44 *
45 * This code will probably be impenetrable without reference to the
46 * Intel Pentium Pro documentation.
47 */
48
49 static char *mem_owner_bios = "BIOS";
50
51 #define MR686_FIXMTRR (1<<0)
52
53 #define mrwithin(mr, a) \
54 (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
55 #define mroverlap(mra, mrb) \
56 (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
57
58 #define mrvalid(base, len) \
59 ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \
60 ((len) >= (1 << 12)) && /* length is >= 4k */ \
61 powerof2((len)) && /* ... and power of two */ \
62 !((base) & ((len) - 1))) /* range is not discontiuous */
63
64 #define mrcopyflags(curr, new) \
65 (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
66
67 static int mtrrs_disabled;
68 TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled);
69 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
70 &mtrrs_disabled, 0, "Disable i686 MTRRs.");
71
72 static void i686_mrinit(struct mem_range_softc *sc);
73 static int i686_mrset(struct mem_range_softc *sc,
74 struct mem_range_desc *mrd, int *arg);
75 static void i686_mrAPinit(struct mem_range_softc *sc);
76
77 static struct mem_range_ops i686_mrops = {
78 i686_mrinit,
79 i686_mrset,
80 i686_mrAPinit
81 };
82
83 /* XXX for AP startup hook */
84 static u_int64_t mtrrcap, mtrrdef;
85
86 /* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */
87 static u_int64_t mtrr_physmask;
88
89 static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc,
90 struct mem_range_desc *mrd);
91 static void i686_mrfetch(struct mem_range_softc *sc);
92 static int i686_mtrrtype(int flags);
93 static int i686_mrt2mtrr(int flags, int oldval);
94 static int i686_mtrrconflict(int flag1, int flag2);
95 static void i686_mrstore(struct mem_range_softc *sc);
96 static void i686_mrstoreone(void *arg);
97 static struct mem_range_desc *i686_mtrrfixsearch(struct mem_range_softc *sc,
98 u_int64_t addr);
99 static int i686_mrsetlow(struct mem_range_softc *sc,
100 struct mem_range_desc *mrd, int *arg);
101 static int i686_mrsetvariable(struct mem_range_softc *sc,
102 struct mem_range_desc *mrd, int *arg);
103
104 /* i686 MTRR type to memory range type conversion */
105 static int i686_mtrrtomrt[] = {
106 MDF_UNCACHEABLE,
107 MDF_WRITECOMBINE,
108 MDF_UNKNOWN,
109 MDF_UNKNOWN,
110 MDF_WRITETHROUGH,
111 MDF_WRITEPROTECT,
112 MDF_WRITEBACK
113 };
114
115 #define MTRRTOMRTLEN (sizeof(i686_mtrrtomrt) / sizeof(i686_mtrrtomrt[0]))
116
117 static int
118 i686_mtrr2mrt(int val)
119 {
120
121 if (val < 0 || val >= MTRRTOMRTLEN)
122 return (MDF_UNKNOWN);
123 return (i686_mtrrtomrt[val]);
124 }
125
126 /*
127 * i686 MTRR conflicts. Writeback and uncachable may overlap.
128 */
129 static int
130 i686_mtrrconflict(int flag1, int flag2)
131 {
132
133 flag1 &= MDF_ATTRMASK;
134 flag2 &= MDF_ATTRMASK;
135 if (flag1 == flag2 ||
136 (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
137 (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
138 return (0);
139 return (1);
140 }
141
142 /*
143 * Look for an exactly-matching range.
144 */
145 static struct mem_range_desc *
146 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
147 {
148 struct mem_range_desc *cand;
149 int i;
150
151 for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
152 if ((cand->mr_base == mrd->mr_base) &&
153 (cand->mr_len == mrd->mr_len))
154 return (cand);
155 return (NULL);
156 }
157
158 /*
159 * Fetch the current mtrr settings from the current CPU (assumed to
160 * all be in sync in the SMP case). Note that if we are here, we
161 * assume that MTRRs are enabled, and we may or may not have fixed
162 * MTRRs.
163 */
164 static void
165 i686_mrfetch(struct mem_range_softc *sc)
166 {
167 struct mem_range_desc *mrd;
168 u_int64_t msrv;
169 int i, j, msr;
170
171 mrd = sc->mr_desc;
172
173 /* Get fixed-range MTRRs. */
174 if (sc->mr_cap & MR686_FIXMTRR) {
175 msr = MSR_MTRR64kBase;
176 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
177 msrv = rdmsr(msr);
178 for (j = 0; j < 8; j++, mrd++) {
179 mrd->mr_flags =
180 (mrd->mr_flags & ~MDF_ATTRMASK) |
181 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
182 if (mrd->mr_owner[0] == 0)
183 strcpy(mrd->mr_owner, mem_owner_bios);
184 msrv = msrv >> 8;
185 }
186 }
187 msr = MSR_MTRR16kBase;
188 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
189 msrv = rdmsr(msr);
190 for (j = 0; j < 8; j++, mrd++) {
191 mrd->mr_flags =
192 (mrd->mr_flags & ~MDF_ATTRMASK) |
193 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
194 if (mrd->mr_owner[0] == 0)
195 strcpy(mrd->mr_owner, mem_owner_bios);
196 msrv = msrv >> 8;
197 }
198 }
199 msr = MSR_MTRR4kBase;
200 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
201 msrv = rdmsr(msr);
202 for (j = 0; j < 8; j++, mrd++) {
203 mrd->mr_flags =
204 (mrd->mr_flags & ~MDF_ATTRMASK) |
205 i686_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
206 if (mrd->mr_owner[0] == 0)
207 strcpy(mrd->mr_owner, mem_owner_bios);
208 msrv = msrv >> 8;
209 }
210 }
211 }
212
213 /* Get remainder which must be variable MTRRs. */
214 msr = MSR_MTRRVarBase;
215 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
216 msrv = rdmsr(msr);
217 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
218 i686_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE);
219 mrd->mr_base = msrv & mtrr_physmask;
220 msrv = rdmsr(msr + 1);
221 mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ?
222 (mrd->mr_flags | MDF_ACTIVE) :
223 (mrd->mr_flags & ~MDF_ACTIVE);
224
225 /* Compute the range from the mask. Ick. */
226 mrd->mr_len = (~(msrv & mtrr_physmask) &
227 (mtrr_physmask | 0xfffLL)) + 1;
228 if (!mrvalid(mrd->mr_base, mrd->mr_len))
229 mrd->mr_flags |= MDF_BOGUS;
230
231 /* If unclaimed and active, must be the BIOS. */
232 if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
233 strcpy(mrd->mr_owner, mem_owner_bios);
234 }
235 }
236
237 /*
238 * Return the MTRR memory type matching a region's flags
239 */
240 static int
241 i686_mtrrtype(int flags)
242 {
243 int i;
244
245 flags &= MDF_ATTRMASK;
246
247 for (i = 0; i < MTRRTOMRTLEN; i++) {
248 if (i686_mtrrtomrt[i] == MDF_UNKNOWN)
249 continue;
250 if (flags == i686_mtrrtomrt[i])
251 return (i);
252 }
253 return (-1);
254 }
255
256 static int
257 i686_mrt2mtrr(int flags, int oldval)
258 {
259 int val;
260
261 if ((val = i686_mtrrtype(flags)) == -1)
262 return (oldval & 0xff);
263 return (val & 0xff);
264 }
265
266 /*
267 * Update running CPU(s) MTRRs to match the ranges in the descriptor
268 * list.
269 *
270 * XXX Must be called with interrupts enabled.
271 */
272 static void
273 i686_mrstore(struct mem_range_softc *sc)
274 {
275 #ifdef SMP
276 /*
277 * We should use ipi_all_but_self() to call other CPUs into a
278 * locking gate, then call a target function to do this work.
279 * The "proper" solution involves a generalised locking gate
280 * implementation, not ready yet.
281 */
282 smp_rendezvous(NULL, i686_mrstoreone, NULL, sc);
283 #else
284 disable_intr(); /* disable interrupts */
285 i686_mrstoreone(sc);
286 enable_intr();
287 #endif
288 }
289
290 /*
291 * Update the current CPU's MTRRs with those represented in the
292 * descriptor list. Note that we do this wholesale rather than just
293 * stuffing one entry; this is simpler (but slower, of course).
294 */
295 static void
296 i686_mrstoreone(void *arg)
297 {
298 struct mem_range_softc *sc = arg;
299 struct mem_range_desc *mrd;
300 u_int64_t omsrv, msrv;
301 int i, j, msr;
302 u_int cr4save;
303
304 mrd = sc->mr_desc;
305
306 /* Disable PGE. */
307 cr4save = rcr4();
308 if (cr4save & CR4_PGE)
309 load_cr4(cr4save & ~CR4_PGE);
310
311 /* Disable caches (CD = 1, NW = 0). */
312 load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
313
314 /* Flushes caches and TLBs. */
315 wbinvd();
316
317 /* Disable MTRRs (E = 0). */
318 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
319
320 /* Set fixed-range MTRRs. */
321 if (sc->mr_cap & MR686_FIXMTRR) {
322 msr = MSR_MTRR64kBase;
323 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
324 msrv = 0;
325 omsrv = rdmsr(msr);
326 for (j = 7; j >= 0; j--) {
327 msrv = msrv << 8;
328 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
329 omsrv >> (j * 8));
330 }
331 wrmsr(msr, msrv);
332 mrd += 8;
333 }
334 msr = MSR_MTRR16kBase;
335 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
336 msrv = 0;
337 omsrv = rdmsr(msr);
338 for (j = 7; j >= 0; j--) {
339 msrv = msrv << 8;
340 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
341 omsrv >> (j * 8));
342 }
343 wrmsr(msr, msrv);
344 mrd += 8;
345 }
346 msr = MSR_MTRR4kBase;
347 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
348 msrv = 0;
349 omsrv = rdmsr(msr);
350 for (j = 7; j >= 0; j--) {
351 msrv = msrv << 8;
352 msrv |= i686_mrt2mtrr((mrd + j)->mr_flags,
353 omsrv >> (j * 8));
354 }
355 wrmsr(msr, msrv);
356 mrd += 8;
357 }
358 }
359
360 /* Set remainder which must be variable MTRRs. */
361 msr = MSR_MTRRVarBase;
362 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
363 /* base/type register */
364 omsrv = rdmsr(msr);
365 if (mrd->mr_flags & MDF_ACTIVE) {
366 msrv = mrd->mr_base & mtrr_physmask;
367 msrv |= i686_mrt2mtrr(mrd->mr_flags, omsrv);
368 } else {
369 msrv = 0;
370 }
371 wrmsr(msr, msrv);
372
373 /* mask/active register */
374 if (mrd->mr_flags & MDF_ACTIVE) {
375 msrv = MTRR_PHYSMASK_VALID |
376 (~(mrd->mr_len - 1) & mtrr_physmask);
377 } else {
378 msrv = 0;
379 }
380 wrmsr(msr + 1, msrv);
381 }
382
383 /* Flush caches, TLBs. */
384 wbinvd();
385
386 /* Enable MTRRs. */
387 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
388
389 /* Enable caches (CD = 0, NW = 0). */
390 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
391
392 /* Restore PGE. */
393 load_cr4(cr4save);
394 }
395
396 /*
397 * Hunt for the fixed MTRR referencing (addr)
398 */
399 static struct mem_range_desc *
400 i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
401 {
402 struct mem_range_desc *mrd;
403 int i;
404
405 for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K);
406 i++, mrd++)
407 if ((addr >= mrd->mr_base) &&
408 (addr < (mrd->mr_base + mrd->mr_len)))
409 return (mrd);
410 return (NULL);
411 }
412
413 /*
414 * Try to satisfy the given range request by manipulating the fixed
415 * MTRRs that cover low memory.
416 *
417 * Note that we try to be generous here; we'll bloat the range out to
418 * the next higher/lower boundary to avoid the consumer having to know
419 * too much about the mechanisms here.
420 *
421 * XXX note that this will have to be updated when we start supporting
422 * "busy" ranges.
423 */
424 static int
425 i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
426 {
427 struct mem_range_desc *first_md, *last_md, *curr_md;
428
429 /* Range check. */
430 if (((first_md = i686_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
431 ((last_md = i686_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
432 return (EINVAL);
433
434 /* Check that we aren't doing something risky. */
435 if (!(mrd->mr_flags & MDF_FORCE))
436 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
437 if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
438 return (EACCES);
439 }
440
441 /* Set flags, clear set-by-firmware flag. */
442 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
443 curr_md->mr_flags = mrcopyflags(curr_md->mr_flags &
444 ~MDF_FIRMWARE, mrd->mr_flags);
445 bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
446 }
447
448 return (0);
449 }
450
451 /*
452 * Modify/add a variable MTRR to satisfy the request.
453 *
454 * XXX needs to be updated to properly support "busy" ranges.
455 */
456 static int
457 i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd,
458 int *arg)
459 {
460 struct mem_range_desc *curr_md, *free_md;
461 int i;
462
463 /*
464 * Scan the currently active variable descriptors, look for
465 * one we exactly match (straight takeover) and for possible
466 * accidental overlaps.
467 *
468 * Keep track of the first empty variable descriptor in case
469 * we can't perform a takeover.
470 */
471 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
472 curr_md = sc->mr_desc + i;
473 free_md = NULL;
474 for (; i < sc->mr_ndesc; i++, curr_md++) {
475 if (curr_md->mr_flags & MDF_ACTIVE) {
476 /* Exact match? */
477 if ((curr_md->mr_base == mrd->mr_base) &&
478 (curr_md->mr_len == mrd->mr_len)) {
479
480 /* Whoops, owned by someone. */
481 if (curr_md->mr_flags & MDF_BUSY)
482 return (EBUSY);
483
484 /* Check that we aren't doing something risky */
485 if (!(mrd->mr_flags & MDF_FORCE) &&
486 ((curr_md->mr_flags & MDF_ATTRMASK) ==
487 MDF_UNKNOWN))
488 return (EACCES);
489
490 /* Ok, just hijack this entry. */
491 free_md = curr_md;
492 break;
493 }
494
495 /* Non-exact overlap? */
496 if (mroverlap(curr_md, mrd)) {
497 /* Between conflicting region types? */
498 if (i686_mtrrconflict(curr_md->mr_flags,
499 mrd->mr_flags))
500 return (EINVAL);
501 }
502 } else if (free_md == NULL) {
503 free_md = curr_md;
504 }
505 }
506
507 /* Got somewhere to put it? */
508 if (free_md == NULL)
509 return (ENOSPC);
510
511 /* Set up new descriptor. */
512 free_md->mr_base = mrd->mr_base;
513 free_md->mr_len = mrd->mr_len;
514 free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
515 bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
516 return (0);
517 }
518
519 /*
520 * Handle requests to set memory range attributes by manipulating MTRRs.
521 */
522 static int
523 i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
524 {
525 struct mem_range_desc *targ;
526 int error = 0;
527
528 switch(*arg) {
529 case MEMRANGE_SET_UPDATE:
530 /*
531 * Make sure that what's being asked for is even
532 * possible at all.
533 */
534 if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
535 i686_mtrrtype(mrd->mr_flags) == -1)
536 return (EINVAL);
537
538 #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
539
540 /* Are the "low memory" conditions applicable? */
541 if ((sc->mr_cap & MR686_FIXMTRR) &&
542 ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
543 if ((error = i686_mrsetlow(sc, mrd, arg)) != 0)
544 return (error);
545 } else {
546 /* It's time to play with variable MTRRs. */
547 if ((error = i686_mrsetvariable(sc, mrd, arg)) != 0)
548 return (error);
549 }
550 break;
551
552 case MEMRANGE_SET_REMOVE:
553 if ((targ = mem_range_match(sc, mrd)) == NULL)
554 return (ENOENT);
555 if (targ->mr_flags & MDF_FIXACTIVE)
556 return (EPERM);
557 if (targ->mr_flags & MDF_BUSY)
558 return (EBUSY);
559 targ->mr_flags &= ~MDF_ACTIVE;
560 targ->mr_owner[0] = 0;
561 break;
562
563 default:
564 return (EOPNOTSUPP);
565 }
566
567 /* Update the hardware. */
568 i686_mrstore(sc);
569
570 /* Refetch to see where we're at. */
571 i686_mrfetch(sc);
572 return (0);
573 }
574
575 /*
576 * Work out how many ranges we support, initialise storage for them,
577 * and fetch the initial settings.
578 */
579 static void
580 i686_mrinit(struct mem_range_softc *sc)
581 {
582 struct mem_range_desc *mrd;
583 u_int regs[4];
584 int i, nmdesc = 0, pabits;
585
586 mtrrcap = rdmsr(MSR_MTRRcap);
587 mtrrdef = rdmsr(MSR_MTRRdefType);
588
589 /* For now, bail out if MTRRs are not enabled. */
590 if (!(mtrrdef & MTRR_DEF_ENABLE)) {
591 if (bootverbose)
592 printf("CPU supports MTRRs but not enabled\n");
593 return;
594 }
595 nmdesc = mtrrcap & MTRR_CAP_VCNT;
596 if (bootverbose)
597 printf("Pentium Pro MTRR support enabled\n");
598
599 /*
600 * Determine the size of the PhysMask and PhysBase fields in
601 * the variable range MTRRs. If the extended CPUID 0x80000008
602 * is present, use that to figure out how many physical
603 * address bits the CPU supports. Otherwise, default to 36
604 * address bits.
605 */
606 if (cpu_exthigh >= 0x80000008) {
607 do_cpuid(0x80000008, regs);
608 pabits = regs[0] & 0xff;
609 } else
610 pabits = 36;
611 mtrr_physmask = ((1ULL << pabits) - 1) & ~0xfffULL;
612
613 /* If fixed MTRRs supported and enabled. */
614 if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) {
615 sc->mr_cap = MR686_FIXMTRR;
616 nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
617 }
618
619 sc->mr_desc = malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC,
620 M_WAITOK | M_ZERO);
621 sc->mr_ndesc = nmdesc;
622
623 mrd = sc->mr_desc;
624
625 /* Populate the fixed MTRR entries' base/length. */
626 if (sc->mr_cap & MR686_FIXMTRR) {
627 for (i = 0; i < MTRR_N64K; i++, mrd++) {
628 mrd->mr_base = i * 0x10000;
629 mrd->mr_len = 0x10000;
630 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
631 MDF_FIXACTIVE;
632 }
633 for (i = 0; i < MTRR_N16K; i++, mrd++) {
634 mrd->mr_base = i * 0x4000 + 0x80000;
635 mrd->mr_len = 0x4000;
636 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
637 MDF_FIXACTIVE;
638 }
639 for (i = 0; i < MTRR_N4K; i++, mrd++) {
640 mrd->mr_base = i * 0x1000 + 0xc0000;
641 mrd->mr_len = 0x1000;
642 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
643 MDF_FIXACTIVE;
644 }
645 }
646
647 /*
648 * Get current settings, anything set now is considered to
649 * have been set by the firmware. (XXX has something already
650 * played here?)
651 */
652 i686_mrfetch(sc);
653 mrd = sc->mr_desc;
654 for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
655 if (mrd->mr_flags & MDF_ACTIVE)
656 mrd->mr_flags |= MDF_FIRMWARE;
657 }
658 }
659
660 /*
661 * Initialise MTRRs on an AP after the BSP has run the init code.
662 */
663 static void
664 i686_mrAPinit(struct mem_range_softc *sc)
665 {
666
667 i686_mrstoreone(sc);
668 wrmsr(MSR_MTRRdefType, mtrrdef);
669 }
670
671 static void
672 i686_mem_drvinit(void *unused)
673 {
674
675 if (mtrrs_disabled)
676 return;
677 if (!(cpu_feature & CPUID_MTRR))
678 return;
679 if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
680 return;
681 switch (cpu_vendor_id) {
682 case CPU_VENDOR_INTEL:
683 case CPU_VENDOR_AMD:
684 break;
685 case CPU_VENDOR_CENTAUR:
686 if (cpu_exthigh >= 0x80000008)
687 break;
688 /* FALLTHROUGH */
689 default:
690 return;
691 }
692 mem_range_softc.mr_op = &i686_mrops;
693 }
694 SYSINIT(i686memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, i686_mem_drvinit, NULL);
Cache object: e6b42c274f89b918956d063125e710c6
|