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sys/i386/i386/identcpu.c
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1 /* 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 * $FreeBSD$ 40 */ 41 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/sysctl.h> 48 49 #include <machine/asmacros.h> 50 #include <machine/clock.h> 51 #include <machine/cputypes.h> 52 #include <machine/segments.h> 53 #include <machine/specialreg.h> 54 #include <machine/md_var.h> 55 56 #include <i386/isa/intr_machdep.h> 57 58 #define IDENTBLUE_CYRIX486 0 59 #define IDENTBLUE_IBMCPU 1 60 #define IDENTBLUE_CYRIXM2 2 61 62 /* XXX - should be in header file: */ 63 void printcpuinfo(void); 64 void finishidentcpu(void); 65 void earlysetcpuclass(void); 66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 67 void enable_K5_wt_alloc(void); 68 void enable_K6_wt_alloc(void); 69 void enable_K6_2_wt_alloc(void); 70 #endif 71 void panicifcpuunsupported(void); 72 73 static void identifycyrix(void); 74 static void print_AMD_features(u_int *regs); 75 static void print_AMD_info(u_int amd_maxregs); 76 static void print_AMD_assoc(int i); 77 static void do_cpuid(u_int ax, u_int *p); 78 79 u_int cyrix_did; /* Device ID of Cyrix CPU */ 80 int cpu_class = CPUCLASS_386; /* least common denominator */ 81 char machine[] = "i386"; 82 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 83 machine, 0, "Machine class"); 84 85 static char cpu_model[128]; 86 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 87 cpu_model, 0, "Machine model"); 88 89 static struct cpu_nameclass i386_cpus[] = { 90 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 91 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 92 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 93 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 94 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 95 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 96 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 97 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 98 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 99 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 100 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 101 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 102 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 103 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 104 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 105 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 106 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 107 }; 108 109 static void 110 do_cpuid(u_int ax, u_int *p) 111 { 112 __asm __volatile( 113 ".byte 0x0f, 0xa2;" 114 "movl %%eax, (%2);" 115 "movl %%ebx, 4(%2);" 116 "movl %%ecx, 8(%2);" 117 "movl %%edx, 12(%2);" 118 : "=a" (ax) 119 : "" (ax), "S" (p) 120 : "bx", "cx", "dx" 121 ); 122 } 123 124 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 125 int has_f00f_bug = 0; 126 #endif 127 128 void 129 printcpuinfo(void) 130 { 131 132 u_int regs[4], nreg = 0; 133 cpu_class = i386_cpus[cpu].cpu_class; 134 printf("CPU: "); 135 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model); 136 137 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 138 if (strcmp(cpu_vendor,"GenuineIntel") == 0) { 139 if ((cpu_id & 0xf00) > 0x300) { 140 cpu_model[0] = '\0'; 141 142 switch (cpu_id & 0x3000) { 143 case 0x1000: 144 strcpy(cpu_model, "Overdrive "); 145 break; 146 case 0x2000: 147 strcpy(cpu_model, "Dual "); 148 break; 149 } 150 151 switch (cpu_id & 0xf00) { 152 case 0x400: 153 strcat(cpu_model, "i486 "); 154 break; 155 case 0x500: 156 /* Check the particular flavor of 586 */ 157 strcat(cpu_model, "Pentium"); 158 switch (cpu_id & 0xf0) { 159 case 0x00: 160 strcat(cpu_model, " A-step"); 161 break; 162 case 0x10: 163 strcat(cpu_model, "/P5"); 164 break; 165 case 0x20: 166 strcat(cpu_model, "/P54C"); 167 break; 168 case 0x30: 169 strcat(cpu_model, "/P54T Overdrive"); 170 break; 171 case 0x40: 172 strcat(cpu_model, "/P55C"); 173 break; 174 case 0x70: 175 strcat(cpu_model, "/P54C"); 176 break; 177 case 0x80: 178 strcat(cpu_model, "/P55C (quarter-micron)"); 179 break; 180 default: 181 /* nothing */ 182 break; 183 } 184 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 185 /* 186 * XXX - If/when Intel fixes the bug, this 187 * should also check the version of the 188 * CPU, not just that it's a Pentium. 189 */ 190 has_f00f_bug = 1; 191 #endif 192 break; 193 case 0x600: 194 /* Check the particular flavor of 686 */ 195 switch (cpu_id & 0xf0) { 196 case 0x00: 197 strcat(cpu_model, "Pentium Pro A-step"); 198 break; 199 case 0x10: 200 strcat(cpu_model, "Pentium Pro"); 201 break; 202 case 0x30: 203 case 0x50: 204 case 0x60: 205 strcat(cpu_model, 206 "Pentium II/Pentium II Xeon/Celeron"); 207 cpu = CPU_PII; 208 break; 209 case 0x70: 210 case 0x80: 211 case 0xa0: 212 strcat(cpu_model, 213 "Pentium III/Pentium III Xeon/Celeron"); 214 cpu = CPU_PIII; 215 break; 216 default: 217 strcat(cpu_model, "Unknown 80686"); 218 break; 219 } 220 break; 221 case 0xf00: 222 strcat(cpu_model, "Pentium 4"); 223 cpu = CPU_P4; 224 break; 225 default: 226 strcat(cpu_model, "unknown"); 227 break; 228 } 229 230 switch (cpu_id & 0xff0) { 231 case 0x400: 232 strcat(cpu_model, "DX"); break; 233 case 0x410: 234 strcat(cpu_model, "DX"); break; 235 case 0x420: 236 strcat(cpu_model, "SX"); break; 237 case 0x430: 238 strcat(cpu_model, "DX2"); break; 239 case 0x440: 240 strcat(cpu_model, "SL"); break; 241 case 0x450: 242 strcat(cpu_model, "SX2"); break; 243 case 0x470: 244 strcat(cpu_model, "DX2 Write-Back Enhanced"); 245 break; 246 case 0x480: 247 strcat(cpu_model, "DX4"); break; 248 break; 249 } 250 } 251 } else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) { 252 /* 253 * Values taken from AMD Processor Recognition 254 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 255 * (also describes ``Features'' encodings. 256 */ 257 strcpy(cpu_model, "AMD "); 258 switch (cpu_id & 0xFF0) { 259 case 0x410: 260 strcat(cpu_model, "Standard Am486DX"); 261 break; 262 case 0x430: 263 strcat(cpu_model, "Am486DX2/4 Write-Through"); 264 break; 265 case 0x470: 266 strcat(cpu_model, "Enhanced Am486DX4 Write-Back"); 267 break; 268 case 0x480: 269 strcat(cpu_model, "Enhanced Am486DX4 Write-Through"); 270 break; 271 case 0x490: 272 strcat(cpu_model, "Enhanced Am486DX4 Write-Back"); 273 break; 274 case 0x4E0: 275 strcat(cpu_model, "Am5x86 Write-Through"); 276 break; 277 case 0x4F0: 278 strcat(cpu_model, "Am5x86 Write-Back"); 279 break; 280 case 0x500: 281 strcat(cpu_model, "K5 model 0"); 282 tsc_is_broken = 1; 283 break; 284 case 0x510: 285 strcat(cpu_model, "K5 model 1"); 286 break; 287 case 0x520: 288 strcat(cpu_model, "K5 PR166 (model 2)"); 289 break; 290 case 0x530: 291 strcat(cpu_model, "K5 PR200 (model 3)"); 292 break; 293 case 0x560: 294 strcat(cpu_model, "K6"); 295 break; 296 case 0x570: 297 strcat(cpu_model, "K6 266 (model 1)"); 298 break; 299 case 0x580: 300 strcat(cpu_model, "K6-2"); 301 break; 302 case 0x590: 303 strcat(cpu_model, "K6-III"); 304 break; 305 default: 306 strcat(cpu_model, "Unknown"); 307 break; 308 } 309 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 310 if ((cpu_id & 0xf00) == 0x500) { 311 if (((cpu_id & 0x0f0) > 0) 312 && ((cpu_id & 0x0f0) < 0x60) 313 && ((cpu_id & 0x00f) > 3)) 314 enable_K5_wt_alloc(); 315 else if (((cpu_id & 0x0f0) > 0x80) 316 || (((cpu_id & 0x0f0) == 0x80) 317 && (cpu_id & 0x00f) > 0x07)) 318 enable_K6_2_wt_alloc(); 319 else if ((cpu_id & 0x0f0) > 0x50) 320 enable_K6_wt_alloc(); 321 } 322 #endif 323 do_cpuid(0x80000000, regs); 324 nreg = regs[0]; 325 if (nreg >= 0x80000004) { 326 do_cpuid(0x80000002, regs); 327 memcpy(cpu_model, regs, sizeof regs); 328 do_cpuid(0x80000003, regs); 329 memcpy(cpu_model+16, regs, sizeof regs); 330 do_cpuid(0x80000004, regs); 331 memcpy(cpu_model+32, regs, sizeof regs); 332 } 333 } else if (strcmp(cpu_vendor,"CyrixInstead") == 0) { 334 strcpy(cpu_model, "Cyrix "); 335 switch (cpu_id & 0xff0) { 336 case 0x440: 337 strcat(cpu_model, "MediaGX"); 338 break; 339 case 0x520: 340 strcat(cpu_model, "6x86"); 341 break; 342 case 0x540: 343 cpu_class = CPUCLASS_586; 344 strcat(cpu_model, "GXm"); 345 break; 346 case 0x600: 347 strcat(cpu_model, "6x86MX"); 348 break; 349 default: 350 /* 351 * Even though CPU supports the cpuid 352 * instruction, it can be disabled. 353 * Therefore, this routine supports all Cyrix 354 * CPUs. 355 */ 356 switch (cyrix_did & 0xf0) { 357 case 0x00: 358 switch (cyrix_did & 0x0f) { 359 case 0x00: 360 strcat(cpu_model, "486SLC"); 361 break; 362 case 0x01: 363 strcat(cpu_model, "486DLC"); 364 break; 365 case 0x02: 366 strcat(cpu_model, "486SLC2"); 367 break; 368 case 0x03: 369 strcat(cpu_model, "486DLC2"); 370 break; 371 case 0x04: 372 strcat(cpu_model, "486SRx"); 373 break; 374 case 0x05: 375 strcat(cpu_model, "486DRx"); 376 break; 377 case 0x06: 378 strcat(cpu_model, "486SRx2"); 379 break; 380 case 0x07: 381 strcat(cpu_model, "486DRx2"); 382 break; 383 case 0x08: 384 strcat(cpu_model, "486SRu"); 385 break; 386 case 0x09: 387 strcat(cpu_model, "486DRu"); 388 break; 389 case 0x0a: 390 strcat(cpu_model, "486SRu2"); 391 break; 392 case 0x0b: 393 strcat(cpu_model, "486DRu2"); 394 break; 395 default: 396 strcat(cpu_model, "Unknown"); 397 break; 398 } 399 break; 400 case 0x10: 401 switch (cyrix_did & 0x0f) { 402 case 0x00: 403 strcat(cpu_model, "486S"); 404 break; 405 case 0x01: 406 strcat(cpu_model, "486S2"); 407 break; 408 case 0x02: 409 strcat(cpu_model, "486Se"); 410 break; 411 case 0x03: 412 strcat(cpu_model, "486S2e"); 413 break; 414 case 0x0a: 415 strcat(cpu_model, "486DX"); 416 break; 417 case 0x0b: 418 strcat(cpu_model, "486DX2"); 419 break; 420 case 0x0f: 421 strcat(cpu_model, "486DX4"); 422 break; 423 default: 424 strcat(cpu_model, "Unknown"); 425 break; 426 } 427 break; 428 case 0x20: 429 if ((cyrix_did & 0x0f) < 8) 430 strcat(cpu_model, "6x86"); /* Where did you get it? */ 431 else 432 strcat(cpu_model, "5x86"); 433 break; 434 case 0x30: 435 strcat(cpu_model, "6x86"); 436 break; 437 case 0x40: 438 if ((cyrix_did & 0xf000) == 0x3000) { 439 cpu_class = CPUCLASS_586; 440 strcat(cpu_model, "GXm"); 441 } else 442 strcat(cpu_model, "MediaGX"); 443 break; 444 case 0x50: 445 strcat(cpu_model, "6x86MX"); 446 break; 447 case 0xf0: 448 switch (cyrix_did & 0x0f) { 449 case 0x0d: 450 strcat(cpu_model, "Overdrive CPU"); 451 case 0x0e: 452 strcpy(cpu_model, "Texas Instruments 486SXL"); 453 break; 454 case 0x0f: 455 strcat(cpu_model, "486SLC/DLC"); 456 break; 457 default: 458 strcat(cpu_model, "Unknown"); 459 break; 460 } 461 break; 462 default: 463 strcat(cpu_model, "Unknown"); 464 break; 465 } 466 break; 467 } 468 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) { 469 strcpy(cpu_model, "Rise "); 470 switch (cpu_id & 0xff0) { 471 case 0x500: 472 strcat(cpu_model, "mP6"); 473 break; 474 default: 475 strcat(cpu_model, "Unknown"); 476 } 477 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { 478 strcpy(cpu_model, "IDT "); 479 switch (cpu_id & 0xff0) { 480 case 0x540: 481 strcat(cpu_model, "WinChip C6"); 482 tsc_is_broken = 1; 483 break; 484 case 0x580: 485 strcat(cpu_model, "WinChip 2"); 486 break; 487 default: 488 strcat(cpu_model, "Unknown"); 489 } 490 } else if (strcmp(cpu_vendor, "IBM") == 0) 491 strcpy(cpu_model, "Blue Lightning CPU"); 492 #endif 493 494 printf("%s (", cpu_model); 495 switch(cpu_class) { 496 case CPUCLASS_286: 497 printf("286"); 498 break; 499 #if defined(I386_CPU) 500 case CPUCLASS_386: 501 printf("386"); 502 break; 503 #endif 504 #if defined(I486_CPU) 505 case CPUCLASS_486: 506 printf("486"); 507 bzero = i486_bzero; 508 break; 509 #endif 510 #if defined(I586_CPU) 511 case CPUCLASS_586: 512 printf("%d.%02d-MHz ", 513 (tsc_freq + 4999) / 1000000, 514 ((tsc_freq + 4999) / 10000) % 100); 515 printf("586"); 516 break; 517 #endif 518 #if defined(I686_CPU) 519 case CPUCLASS_686: 520 printf("%d.%02d-MHz ", 521 (tsc_freq + 4999) / 1000000, 522 ((tsc_freq + 4999) / 10000) % 100); 523 printf("686"); 524 break; 525 #endif 526 default: 527 printf("unknown"); /* will panic below... */ 528 } 529 printf("-class CPU)\n"); 530 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 531 if(*cpu_vendor) 532 printf(" Origin = \"%s\"",cpu_vendor); 533 if(cpu_id) 534 printf(" Id = 0x%x", cpu_id); 535 536 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 537 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 538 strcmp(cpu_vendor, "RiseRiseRise") == 0 || 539 strcmp(cpu_vendor, "CentaurHauls") == 0 || 540 ((strcmp(cpu_vendor, "CyrixInstead") == 0) && 541 ((cpu_id & 0xf00) > 0x500))) { 542 printf(" Stepping = %u", cpu_id & 0xf); 543 if (strcmp(cpu_vendor, "CyrixInstead") == 0) 544 printf(" DIR=0x%04x", cyrix_did); 545 if (cpu_high > 0) { 546 /* 547 * Here we should probably set up flags indicating 548 * whether or not various features are available. 549 * The interesting ones are probably VME, PSE, PAE, 550 * and PGE. The code already assumes without bothering 551 * to check that all CPUs >= Pentium have a TSC and 552 * MSRs. 553 */ 554 printf("\n Features=0x%b", cpu_feature, 555 "\020" 556 "\001FPU" /* Integral FPU */ 557 "\002VME" /* Extended VM86 mode support */ 558 "\003DE" /* Debugging Extensions (CR4.DE) */ 559 "\004PSE" /* 4MByte page tables */ 560 "\005TSC" /* Timestamp counter */ 561 "\006MSR" /* Machine specific registers */ 562 "\007PAE" /* Physical address extension */ 563 "\010MCE" /* Machine Check support */ 564 "\011CX8" /* CMPEXCH8 instruction */ 565 "\012APIC" /* SMP local APIC */ 566 "\013oldMTRR" 567 "\014SEP" /* Fast System Call */ 568 "\015MTRR" /* Memory Type Range Registers */ 569 "\016PGE" /* PG_G (global bit) support */ 570 "\017MCA" /* Machine Check Architecture */ 571 "\020CMOV" /* CMOV instruction */ 572 "\021PAT" /* Page attributes table */ 573 "\022PSE36" /* 36 bit address space support */ 574 "\023PN" /* Processor Serial number */ 575 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 576 "\025<b20>" 577 "\026DTS" /* Debug Trace Store */ 578 "\027ACPI" /* ACPI support */ 579 "\030MMX" /* MMX instructions */ 580 "\031FXSR" /* FXSAVE/FXRSTOR */ 581 "\032SSE" /* Streaming SIMD Extensions */ 582 "\033SSE2" /* Streaming SIMD Extensions #2 */ 583 "\034SS" /* Self snoop */ 584 "\035<b28>" 585 "\036ACC" /* Auto Clock Correction (TCC/ACPI) */ 586 "\037<b30>" 587 "\040<b31>" 588 ); 589 } 590 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 591 nreg >= 0x80000001) 592 print_AMD_features(regs); 593 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 594 printf(" DIR=0x%04x", cyrix_did); 595 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 596 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 597 #ifndef CYRIX_CACHE_REALLY_WORKS 598 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 599 printf("\n CPU cache: write-through mode"); 600 #endif 601 } 602 /* Avoid ugly blank lines: only print newline when we have to. */ 603 if (*cpu_vendor || cpu_id) 604 printf("\n"); 605 606 #endif 607 if (!bootverbose) 608 return; 609 610 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 611 print_AMD_info(nreg); 612 #ifdef I686_CPU 613 /* 614 * XXX - Do PPro CPUID level=2 stuff here? 615 * 616 * No, but maybe in a print_Intel_info() function called from here. 617 */ 618 #endif 619 } 620 621 void 622 panicifcpuunsupported(void) 623 { 624 625 /* 626 * Now that we have told the user what they have, 627 * let them know if that machine type isn't configured. 628 */ 629 switch (cpu_class) { 630 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 631 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 632 #error This kernel is not configured for one of the supported CPUs 633 #endif 634 #if !defined(I386_CPU) 635 case CPUCLASS_386: 636 #endif 637 #if !defined(I486_CPU) 638 case CPUCLASS_486: 639 #endif 640 #if !defined(I586_CPU) 641 case CPUCLASS_586: 642 #endif 643 #if !defined(I686_CPU) 644 case CPUCLASS_686: 645 #endif 646 panic("CPU class not configured"); 647 default: 648 break; 649 } 650 } 651 652 653 static volatile u_int trap_by_rdmsr; 654 655 /* 656 * Special exception 6 handler. 657 * The rdmsr instruction generates invalid opcodes fault on 486-class 658 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 659 * function identblue() when this handler is called. Stacked eip should 660 * be advanced. 661 */ 662 inthand_t bluetrap6; 663 __asm 664 (" \n\ 665 .text \n\ 666 .p2align 2,0x90 \n\ 667 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 668 " __XSTRING(CNAME(bluetrap6)) ": \n\ 669 ss \n\ 670 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 671 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 672 iret \n\ 673 "); 674 675 /* 676 * Special exception 13 handler. 677 * Accessing non-existent MSR generates general protection fault. 678 */ 679 inthand_t bluetrap13; 680 __asm 681 (" \n\ 682 .text \n\ 683 .p2align 2,0x90 \n\ 684 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 685 " __XSTRING(CNAME(bluetrap13)) ": \n\ 686 ss \n\ 687 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 688 popl %eax /* discard error code */ \n\ 689 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 690 iret \n\ 691 "); 692 693 /* 694 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 695 * support cpuid instruction. This function should be called after 696 * loading interrupt descriptor table register. 697 * 698 * I don't like this method that handles fault, but I couldn't get 699 * information for any other methods. Does blue giant know? 700 */ 701 static int 702 identblue(void) 703 { 704 705 trap_by_rdmsr = 0; 706 707 /* 708 * Cyrix 486-class CPU does not support rdmsr instruction. 709 * The rdmsr instruction generates invalid opcode fault, and exception 710 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 711 * bluetrap6() set the magic number to trap_by_rdmsr. 712 */ 713 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 714 715 /* 716 * Certain BIOS disables cpuid instructnion of Cyrix 6x86MX CPU. 717 * In this case, rdmsr generates general protection fault, and 718 * exception will be trapped by bluetrap13(). 719 */ 720 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 721 722 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 723 724 if (trap_by_rdmsr == 0xa8c1d) 725 return IDENTBLUE_CYRIX486; 726 else if (trap_by_rdmsr == 0xa89c4) 727 return IDENTBLUE_CYRIXM2; 728 return IDENTBLUE_IBMCPU; 729 } 730 731 732 /* 733 * identifycyrix() set lower 16 bits of cyrix_did as follows: 734 * 735 * F E D C B A 9 8 7 6 5 4 3 2 1 0 736 * +-------+-------+---------------+ 737 * | SID | RID | Device ID | 738 * | (DIR 1) | (DIR 0) | 739 * +-------+-------+---------------+ 740 */ 741 static void 742 identifycyrix(void) 743 { 744 u_int eflags; 745 int ccr2_test = 0, dir_test = 0; 746 u_char ccr2, ccr3; 747 748 eflags = read_eflags(); 749 disable_intr(); 750 751 ccr2 = read_cyrix_reg(CCR2); 752 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 753 read_cyrix_reg(CCR2); 754 if (read_cyrix_reg(CCR2) != ccr2) 755 ccr2_test = 1; 756 write_cyrix_reg(CCR2, ccr2); 757 758 ccr3 = read_cyrix_reg(CCR3); 759 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 760 read_cyrix_reg(CCR3); 761 if (read_cyrix_reg(CCR3) != ccr3) 762 dir_test = 1; /* CPU supports DIRs. */ 763 write_cyrix_reg(CCR3, ccr3); 764 765 if (dir_test) { 766 /* Device ID registers are available. */ 767 cyrix_did = read_cyrix_reg(DIR1) << 8; 768 cyrix_did += read_cyrix_reg(DIR0); 769 } else if (ccr2_test) 770 cyrix_did = 0x0010; /* 486S A-step */ 771 else 772 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 773 774 write_eflags(eflags); 775 } 776 777 /* 778 * Final stage of CPU identification. -- Should I check TI? 779 */ 780 void 781 finishidentcpu(void) 782 { 783 int isblue = 0; 784 u_char ccr3; 785 u_int regs[4]; 786 787 if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 788 if (cpu == CPU_486) { 789 /* 790 * These conditions are equivalent to: 791 * - CPU does not support cpuid instruction. 792 * - Cyrix/IBM CPU is detected. 793 */ 794 isblue = identblue(); 795 if (isblue == IDENTBLUE_IBMCPU) { 796 strcpy(cpu_vendor, "IBM"); 797 cpu = CPU_BLUE; 798 return; 799 } 800 } 801 switch (cpu_id & 0xf00) { 802 case 0x600: 803 /* 804 * Cyrix's datasheet does not describe DIRs. 805 * Therefor, I assume it does not have them 806 * and use the result of the cpuid instruction. 807 * XXX they seem to have it for now at least. -Peter 808 */ 809 identifycyrix(); 810 cpu = CPU_M2; 811 break; 812 default: 813 identifycyrix(); 814 /* 815 * This routine contains a trick. 816 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 817 */ 818 switch (cyrix_did & 0x00f0) { 819 case 0x00: 820 case 0xf0: 821 cpu = CPU_486DLC; 822 break; 823 case 0x10: 824 cpu = CPU_CY486DX; 825 break; 826 case 0x20: 827 if ((cyrix_did & 0x000f) < 8) 828 cpu = CPU_M1; 829 else 830 cpu = CPU_M1SC; 831 break; 832 case 0x30: 833 cpu = CPU_M1; 834 break; 835 case 0x40: 836 /* MediaGX CPU */ 837 cpu = CPU_M1SC; 838 break; 839 default: 840 /* M2 and later CPUs are treated as M2. */ 841 cpu = CPU_M2; 842 843 /* 844 * enable cpuid instruction. 845 */ 846 ccr3 = read_cyrix_reg(CCR3); 847 write_cyrix_reg(CCR3, CCR3_MAPEN0); 848 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 849 write_cyrix_reg(CCR3, ccr3); 850 851 do_cpuid(0, regs); 852 cpu_high = regs[0]; /* eax */ 853 do_cpuid(1, regs); 854 cpu_id = regs[0]; /* eax */ 855 cpu_feature = regs[3]; /* edx */ 856 break; 857 } 858 } 859 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 860 /* 861 * There are BlueLightning CPUs that do not change 862 * undefined flags by dividing 5 by 2. In this case, 863 * the CPU identification routine in locore.s leaves 864 * cpu_vendor null string and puts CPU_486 into the 865 * cpu. 866 */ 867 isblue = identblue(); 868 if (isblue == IDENTBLUE_IBMCPU) { 869 strcpy(cpu_vendor, "IBM"); 870 cpu = CPU_BLUE; 871 return; 872 } 873 } 874 } 875 876 /* 877 * This routine is called specifically to set up cpu_class before 878 * startrtclock() uses it. Probably this should be rearranged so that 879 * startrtclock() doesn't need to run until after identifycpu() has been 880 * called. Another alternative formulation would be for this routine 881 * to do all the identification work, and make identifycpu() into a 882 * printing-only routine. 883 */ 884 void 885 earlysetcpuclass(void) 886 { 887 888 cpu_class = i386_cpus[cpu].cpu_class; 889 } 890 891 static void 892 print_AMD_assoc(int i) 893 { 894 if (i == 255) 895 printf(", fully associative\n"); 896 else 897 printf(", %d-way associative\n", i); 898 } 899 900 static void 901 print_AMD_info(u_int amd_maxregs) 902 { 903 quad_t amd_whcr; 904 905 if (amd_maxregs >= 0x80000005) { 906 u_int regs[4]; 907 908 do_cpuid(0x80000005, regs); 909 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); 910 print_AMD_assoc(regs[1] >> 24); 911 printf("Instruction TLB: %d entries", regs[1] & 0xff); 912 print_AMD_assoc((regs[1] >> 8) & 0xff); 913 printf("L1 data cache: %d kbytes", regs[2] >> 24); 914 printf(", %d bytes/line", regs[2] & 0xff); 915 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 916 print_AMD_assoc((regs[2] >> 16) & 0xff); 917 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 918 printf(", %d bytes/line", regs[3] & 0xff); 919 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 920 print_AMD_assoc((regs[3] >> 16) & 0xff); 921 if (amd_maxregs >= 0x80000006) { /* K6-III only */ 922 do_cpuid(0x80000006, regs); 923 printf("L2 internal cache: %d kbytes", regs[2] >> 16); 924 printf(", %d bytes/line", regs[2] & 0xff); 925 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 926 print_AMD_assoc((regs[2] >> 12) & 0x0f); 927 } 928 } 929 if (((cpu_id & 0xf00) == 0x500) 930 && (((cpu_id & 0x0f0) > 0x80) 931 || (((cpu_id & 0x0f0) == 0x80) 932 && (cpu_id & 0x00f) > 0x07))) { 933 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 934 amd_whcr = rdmsr(0xc0000082); 935 if (!(amd_whcr & (0x3ff << 22))) { 936 printf("Write Allocate Disable\n"); 937 } else { 938 printf("Write Allocate Enable Limit: %dM bytes\n", 939 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 940 printf("Write Allocate 15-16M bytes: %s\n", 941 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 942 } 943 } else if (((cpu_id & 0xf00) == 0x500) 944 && ((cpu_id & 0x0f0) > 0x50)) { 945 /* K6, K6-2(old core) */ 946 amd_whcr = rdmsr(0xc0000082); 947 if (!(amd_whcr & (0x7f << 1))) { 948 printf("Write Allocate Disable\n"); 949 } else { 950 printf("Write Allocate Enable Limit: %dM bytes\n", 951 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 952 printf("Write Allocate 15-16M bytes: %s\n", 953 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 954 printf("Hardware Write Allocate Control: %s\n", 955 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 956 } 957 } 958 } 959 960 static void 961 print_AMD_features(u_int *regs) 962 { 963 /* 964 * Values taken from AMD Processor Recognition 965 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf 966 */ 967 do_cpuid(0x80000001, regs); 968 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature, 969 "\020" /* in hex */ 970 "\001FPU" /* Integral FPU */ 971 "\002VME" /* Extended VM86 mode support */ 972 "\003DE" /* Debug extensions */ 973 "\004PSE" /* 4MByte page tables */ 974 "\005TSC" /* Timestamp counter */ 975 "\006MSR" /* Machine specific registers */ 976 "\007PAE" /* Physical address extension */ 977 "\010MCE" /* Machine Check support */ 978 "\011CX8" /* CMPEXCH8 instruction */ 979 "\012APIC" /* SMP local APIC */ 980 "\013<b10>" 981 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */ 982 "\015MTRR" /* Memory Type Range Registers */ 983 "\016PGE" /* PG_G (global bit) support */ 984 "\017MCA" /* Machine Check Architecture */ 985 "\020ICMOV" /* CMOV instruction */ 986 "\021PAT" /* Page attributes table */ 987 "\022PGE36" /* 36 bit address space support */ 988 "\023<b18>" 989 "\024<b19>" 990 "\025<b20>" 991 "\026<b21>" 992 "\027AMIE" /* AMD MMX Instruction Extensions */ 993 "\030MMX" 994 "\031FXSAVE" /* FXSAVE/FXRSTOR */ 995 "\032<b25>" 996 "\033<b26>" 997 "\034<b27>" 998 "\035<b28>" 999 "\036<b29>" 1000 "\037DSP" /* AMD 3DNow! Instruction Extensions */ 1001 "\0403DNow!" 1002 ); 1003 }
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