1 /*
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: releng/5.0/sys/i386/i386/identcpu.c 102934 2002-09-04 19:43:22Z phk $
42 */
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <sys/power.h>
52
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
59
60 #include <i386/isa/icu.h>
61 #include <i386/isa/intr_machdep.h>
62
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
66
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
75 #endif
76 void panicifcpuunsupported(void);
77
78 static void identifycyrix(void);
79 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
80 static void print_AMD_features(u_int *regs);
81 #endif
82 static void print_AMD_info(u_int amd_maxregs);
83 static void print_AMD_assoc(int i);
84 static void print_transmeta_info(void);
85 static void setup_tmx86_longrun(void);
86
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 int cpu_class = CPUCLASS_386; /* least common denominator */
89 char machine[] = "i386";
90 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
91 machine, 0, "Machine class");
92
93 static char cpu_model[128];
94 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
95 cpu_model, 0, "Machine model");
96
97 static struct cpu_nameclass i386_cpus[] = {
98 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
99 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
100 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
101 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
102 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
103 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
104 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
105 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
106 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
107 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
108 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
109 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
110 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
111 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
112 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
113 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
114 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
115 };
116
117 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
118 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
119 #endif
120
121 void
122 printcpuinfo(void)
123 {
124 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
125 u_int regs[4];
126 #endif
127 u_int nreg = 0;
128 cpu_class = i386_cpus[cpu].cpu_class;
129 printf("CPU: ");
130 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
131
132 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
133 if (strcmp(cpu_vendor,"GenuineIntel") == 0) {
134 if ((cpu_id & 0xf00) > 0x300) {
135 cpu_model[0] = '\0';
136
137 switch (cpu_id & 0x3000) {
138 case 0x1000:
139 strcpy(cpu_model, "Overdrive ");
140 break;
141 case 0x2000:
142 strcpy(cpu_model, "Dual ");
143 break;
144 }
145
146 switch (cpu_id & 0xf00) {
147 case 0x400:
148 strcat(cpu_model, "i486 ");
149 /* Check the particular flavor of 486 */
150 switch (cpu_id & 0xf0) {
151 case 0x00:
152 case 0x10:
153 strcat(cpu_model, "DX");
154 break;
155 case 0x20:
156 strcat(cpu_model, "SX");
157 break;
158 case 0x30:
159 strcat(cpu_model, "DX2");
160 break;
161 case 0x40:
162 strcat(cpu_model, "SL");
163 break;
164 case 0x50:
165 strcat(cpu_model, "SX2");
166 break;
167 case 0x70:
168 strcat(cpu_model,
169 "DX2 Write-Back Enhanced");
170 break;
171 case 0x80:
172 strcat(cpu_model, "DX4");
173 break;
174 }
175 break;
176 case 0x500:
177 /* Check the particular flavor of 586 */
178 strcat(cpu_model, "Pentium");
179 switch (cpu_id & 0xf0) {
180 case 0x00:
181 strcat(cpu_model, " A-step");
182 break;
183 case 0x10:
184 strcat(cpu_model, "/P5");
185 break;
186 case 0x20:
187 strcat(cpu_model, "/P54C");
188 break;
189 case 0x30:
190 strcat(cpu_model, "/P54T Overdrive");
191 break;
192 case 0x40:
193 strcat(cpu_model, "/P55C");
194 break;
195 case 0x70:
196 strcat(cpu_model, "/P54C");
197 break;
198 case 0x80:
199 strcat(cpu_model, "/P55C (quarter-micron)");
200 break;
201 default:
202 /* nothing */
203 break;
204 }
205 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
206 /*
207 * XXX - If/when Intel fixes the bug, this
208 * should also check the version of the
209 * CPU, not just that it's a Pentium.
210 */
211 has_f00f_bug = 1;
212 #endif
213 break;
214 case 0x600:
215 /* Check the particular flavor of 686 */
216 switch (cpu_id & 0xf0) {
217 case 0x00:
218 strcat(cpu_model, "Pentium Pro A-step");
219 break;
220 case 0x10:
221 strcat(cpu_model, "Pentium Pro");
222 break;
223 case 0x30:
224 case 0x50:
225 case 0x60:
226 strcat(cpu_model,
227 "Pentium II/Pentium II Xeon/Celeron");
228 cpu = CPU_PII;
229 break;
230 case 0x70:
231 case 0x80:
232 case 0xa0:
233 case 0xb0:
234 strcat(cpu_model,
235 "Pentium III/Pentium III Xeon/Celeron");
236 cpu = CPU_PIII;
237 break;
238 default:
239 strcat(cpu_model, "Unknown 80686");
240 break;
241 }
242 break;
243 case 0xf00:
244 strcat(cpu_model, "Pentium 4");
245 cpu = CPU_P4;
246 break;
247 default:
248 strcat(cpu_model, "unknown");
249 break;
250 }
251
252 }
253 } else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) {
254 /*
255 * Values taken from AMD Processor Recognition
256 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
257 * (also describes ``Features'' encodings.
258 */
259 strcpy(cpu_model, "AMD ");
260 switch (cpu_id & 0xFF0) {
261 case 0x410:
262 strcat(cpu_model, "Standard Am486DX");
263 break;
264 case 0x430:
265 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
266 break;
267 case 0x470:
268 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
269 break;
270 case 0x480:
271 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
272 break;
273 case 0x490:
274 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
275 break;
276 case 0x4E0:
277 strcat(cpu_model, "Am5x86 Write-Through");
278 break;
279 case 0x4F0:
280 strcat(cpu_model, "Am5x86 Write-Back");
281 break;
282 case 0x500:
283 strcat(cpu_model, "K5 model 0");
284 tsc_is_broken = 1;
285 break;
286 case 0x510:
287 strcat(cpu_model, "K5 model 1");
288 break;
289 case 0x520:
290 strcat(cpu_model, "K5 PR166 (model 2)");
291 break;
292 case 0x530:
293 strcat(cpu_model, "K5 PR200 (model 3)");
294 break;
295 case 0x560:
296 strcat(cpu_model, "K6");
297 break;
298 case 0x570:
299 strcat(cpu_model, "K6 266 (model 1)");
300 break;
301 case 0x580:
302 strcat(cpu_model, "K6-2");
303 break;
304 case 0x590:
305 strcat(cpu_model, "K6-III");
306 break;
307 default:
308 strcat(cpu_model, "Unknown");
309 break;
310 }
311 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
312 if ((cpu_id & 0xf00) == 0x500) {
313 if (((cpu_id & 0x0f0) > 0)
314 && ((cpu_id & 0x0f0) < 0x60)
315 && ((cpu_id & 0x00f) > 3))
316 enable_K5_wt_alloc();
317 else if (((cpu_id & 0x0f0) > 0x80)
318 || (((cpu_id & 0x0f0) == 0x80)
319 && (cpu_id & 0x00f) > 0x07))
320 enable_K6_2_wt_alloc();
321 else if ((cpu_id & 0x0f0) > 0x50)
322 enable_K6_wt_alloc();
323 }
324 #endif
325 do_cpuid(0x80000000, regs);
326 nreg = regs[0];
327 if (nreg >= 0x80000004) {
328 do_cpuid(0x80000002, regs);
329 memcpy(cpu_model, regs, sizeof regs);
330 do_cpuid(0x80000003, regs);
331 memcpy(cpu_model+16, regs, sizeof regs);
332 do_cpuid(0x80000004, regs);
333 memcpy(cpu_model+32, regs, sizeof regs);
334 }
335 } else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
336 strcpy(cpu_model, "Cyrix ");
337 switch (cpu_id & 0xff0) {
338 case 0x440:
339 strcat(cpu_model, "MediaGX");
340 break;
341 case 0x520:
342 strcat(cpu_model, "6x86");
343 break;
344 case 0x540:
345 cpu_class = CPUCLASS_586;
346 strcat(cpu_model, "GXm");
347 break;
348 case 0x600:
349 strcat(cpu_model, "6x86MX");
350 break;
351 default:
352 /*
353 * Even though CPU supports the cpuid
354 * instruction, it can be disabled.
355 * Therefore, this routine supports all Cyrix
356 * CPUs.
357 */
358 switch (cyrix_did & 0xf0) {
359 case 0x00:
360 switch (cyrix_did & 0x0f) {
361 case 0x00:
362 strcat(cpu_model, "486SLC");
363 break;
364 case 0x01:
365 strcat(cpu_model, "486DLC");
366 break;
367 case 0x02:
368 strcat(cpu_model, "486SLC2");
369 break;
370 case 0x03:
371 strcat(cpu_model, "486DLC2");
372 break;
373 case 0x04:
374 strcat(cpu_model, "486SRx");
375 break;
376 case 0x05:
377 strcat(cpu_model, "486DRx");
378 break;
379 case 0x06:
380 strcat(cpu_model, "486SRx2");
381 break;
382 case 0x07:
383 strcat(cpu_model, "486DRx2");
384 break;
385 case 0x08:
386 strcat(cpu_model, "486SRu");
387 break;
388 case 0x09:
389 strcat(cpu_model, "486DRu");
390 break;
391 case 0x0a:
392 strcat(cpu_model, "486SRu2");
393 break;
394 case 0x0b:
395 strcat(cpu_model, "486DRu2");
396 break;
397 default:
398 strcat(cpu_model, "Unknown");
399 break;
400 }
401 break;
402 case 0x10:
403 switch (cyrix_did & 0x0f) {
404 case 0x00:
405 strcat(cpu_model, "486S");
406 break;
407 case 0x01:
408 strcat(cpu_model, "486S2");
409 break;
410 case 0x02:
411 strcat(cpu_model, "486Se");
412 break;
413 case 0x03:
414 strcat(cpu_model, "486S2e");
415 break;
416 case 0x0a:
417 strcat(cpu_model, "486DX");
418 break;
419 case 0x0b:
420 strcat(cpu_model, "486DX2");
421 break;
422 case 0x0f:
423 strcat(cpu_model, "486DX4");
424 break;
425 default:
426 strcat(cpu_model, "Unknown");
427 break;
428 }
429 break;
430 case 0x20:
431 if ((cyrix_did & 0x0f) < 8)
432 strcat(cpu_model, "6x86"); /* Where did you get it? */
433 else
434 strcat(cpu_model, "5x86");
435 break;
436 case 0x30:
437 strcat(cpu_model, "6x86");
438 break;
439 case 0x40:
440 if ((cyrix_did & 0xf000) == 0x3000) {
441 cpu_class = CPUCLASS_586;
442 strcat(cpu_model, "GXm");
443 } else
444 strcat(cpu_model, "MediaGX");
445 break;
446 case 0x50:
447 strcat(cpu_model, "6x86MX");
448 break;
449 case 0xf0:
450 switch (cyrix_did & 0x0f) {
451 case 0x0d:
452 strcat(cpu_model, "Overdrive CPU");
453 case 0x0e:
454 strcpy(cpu_model, "Texas Instruments 486SXL");
455 break;
456 case 0x0f:
457 strcat(cpu_model, "486SLC/DLC");
458 break;
459 default:
460 strcat(cpu_model, "Unknown");
461 break;
462 }
463 break;
464 default:
465 strcat(cpu_model, "Unknown");
466 break;
467 }
468 break;
469 }
470 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
471 strcpy(cpu_model, "Rise ");
472 switch (cpu_id & 0xff0) {
473 case 0x500:
474 strcat(cpu_model, "mP6");
475 break;
476 default:
477 strcat(cpu_model, "Unknown");
478 }
479 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
480 switch (cpu_id & 0xff0) {
481 case 0x540:
482 strcpy(cpu_model, "IDT WinChip C6");
483 tsc_is_broken = 1;
484 break;
485 case 0x580:
486 strcpy(cpu_model, "IDT WinChip 2");
487 break;
488 case 0x670:
489 strcpy(cpu_model, "VIA C3 Samuel 2");
490 break;
491 default:
492 strcpy(cpu_model, "VIA/IDT Unknown");
493 }
494 } else if (strcmp(cpu_vendor, "IBM") == 0) {
495 strcpy(cpu_model, "Blue Lightning CPU");
496 } else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
497 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
498 do_cpuid(0x80000000, regs);
499 nreg = regs[0];
500 if (nreg >= 0x80000004) {
501 do_cpuid(0x80000002, regs);
502 memcpy(cpu_model, regs, sizeof regs);
503 do_cpuid(0x80000003, regs);
504 memcpy(cpu_model+16, regs, sizeof regs);
505 do_cpuid(0x80000004, regs);
506 memcpy(cpu_model+32, regs, sizeof regs);
507 }
508 cpu_model[64] = '\0';
509 }
510 #endif
511
512 printf("%s (", cpu_model);
513 switch(cpu_class) {
514 case CPUCLASS_286:
515 printf("286");
516 break;
517 #if defined(I386_CPU)
518 case CPUCLASS_386:
519 printf("386");
520 break;
521 #endif
522 #if defined(I486_CPU)
523 case CPUCLASS_486:
524 printf("486");
525 bzero = i486_bzero;
526 break;
527 #endif
528 #if defined(I586_CPU)
529 case CPUCLASS_586:
530 printf("%d.%02d-MHz ",
531 (tsc_freq + 4999) / 1000000,
532 ((tsc_freq + 4999) / 10000) % 100);
533 printf("586");
534 break;
535 #endif
536 #if defined(I686_CPU)
537 case CPUCLASS_686:
538 printf("%d.%02d-MHz ",
539 (tsc_freq + 4999) / 1000000,
540 ((tsc_freq + 4999) / 10000) % 100);
541 printf("686");
542 break;
543 #endif
544 default:
545 printf("Unknown"); /* will panic below... */
546 }
547 printf("-class CPU)\n");
548 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
549 if(*cpu_vendor)
550 printf(" Origin = \"%s\"",cpu_vendor);
551 if(cpu_id)
552 printf(" Id = 0x%x", cpu_id);
553
554 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
555 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
556 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
557 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
558 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
559 ((cpu_id & 0xf00) > 0x500))) {
560 printf(" Stepping = %u", cpu_id & 0xf);
561 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
562 printf(" DIR=0x%04x", cyrix_did);
563 if (cpu_high > 0) {
564 /*
565 * Here we should probably set up flags indicating
566 * whether or not various features are available.
567 * The interesting ones are probably VME, PSE, PAE,
568 * and PGE. The code already assumes without bothering
569 * to check that all CPUs >= Pentium have a TSC and
570 * MSRs.
571 */
572 printf("\n Features=0x%b", cpu_feature,
573 "\020"
574 "\001FPU" /* Integral FPU */
575 "\002VME" /* Extended VM86 mode support */
576 "\003DE" /* Debugging Extensions (CR4.DE) */
577 "\004PSE" /* 4MByte page tables */
578 "\005TSC" /* Timestamp counter */
579 "\006MSR" /* Machine specific registers */
580 "\007PAE" /* Physical address extension */
581 "\010MCE" /* Machine Check support */
582 "\011CX8" /* CMPEXCH8 instruction */
583 "\012APIC" /* SMP local APIC */
584 "\013oldMTRR" /* Previous implementation of MTRR */
585 "\014SEP" /* Fast System Call */
586 "\015MTRR" /* Memory Type Range Registers */
587 "\016PGE" /* PG_G (global bit) support */
588 "\017MCA" /* Machine Check Architecture */
589 "\020CMOV" /* CMOV instruction */
590 "\021PAT" /* Page attributes table */
591 "\022PSE36" /* 36 bit address space support */
592 "\023PN" /* Processor Serial number */
593 "\024CLFLUSH" /* Has the CLFLUSH instruction */
594 "\025<b20>"
595 "\026DTS" /* Debug Trace Store */
596 "\027ACPI" /* ACPI support */
597 "\030MMX" /* MMX instructions */
598 "\031FXSR" /* FXSAVE/FXRSTOR */
599 "\032SSE" /* Streaming SIMD Extensions */
600 "\033SSE2" /* Streaming SIMD Extensions #2 */
601 "\034SS" /* Self snoop */
602 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
603 "\036TM" /* Thermal Monitor clock slowdown */
604 "\037IA64" /* CPU can execute IA64 instructions */
605 "\040<b31>"
606 );
607 }
608 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
609 nreg >= 0x80000001)
610 print_AMD_features(regs);
611 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
612 printf(" DIR=0x%04x", cyrix_did);
613 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
614 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
615 #ifndef CYRIX_CACHE_REALLY_WORKS
616 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
617 printf("\n CPU cache: write-through mode");
618 #endif
619 }
620 /* Avoid ugly blank lines: only print newline when we have to. */
621 if (*cpu_vendor || cpu_id)
622 printf("\n");
623
624 #endif
625 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
626 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
627 setup_tmx86_longrun();
628 }
629
630 if (!bootverbose)
631 return;
632
633 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
634 print_AMD_info(nreg);
635 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
636 strcmp(cpu_vendor, "TransmetaCPU") == 0)
637 print_transmeta_info();
638
639 #ifdef I686_CPU
640 /*
641 * XXX - Do PPro CPUID level=2 stuff here?
642 *
643 * No, but maybe in a print_Intel_info() function called from here.
644 */
645 #endif
646 }
647
648 void
649 panicifcpuunsupported(void)
650 {
651
652 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
653 #error This kernel is not configured for one of the supported CPUs
654 #endif
655 #if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
656 #error I386_CPU is mutually exclusive with the other cpu types.
657 #endif
658 /*
659 * Now that we have told the user what they have,
660 * let them know if that machine type isn't configured.
661 */
662 switch (cpu_class) {
663 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
664 #if !defined(I386_CPU)
665 case CPUCLASS_386:
666 #endif
667 #if !defined(I486_CPU)
668 case CPUCLASS_486:
669 #endif
670 #if !defined(I586_CPU)
671 case CPUCLASS_586:
672 #endif
673 #if !defined(I686_CPU)
674 case CPUCLASS_686:
675 #endif
676 panic("CPU class not configured");
677 default:
678 break;
679 }
680 }
681
682
683 static volatile u_int trap_by_rdmsr;
684
685 /*
686 * Special exception 6 handler.
687 * The rdmsr instruction generates invalid opcodes fault on 486-class
688 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
689 * function identblue() when this handler is called. Stacked eip should
690 * be advanced.
691 */
692 inthand_t bluetrap6;
693 __asm
694 (" \
695 .text; \
696 .p2align 2,0x90; \
697 .type " __XSTRING(CNAME(bluetrap6)) ",@function; \
698 " __XSTRING(CNAME(bluetrap6)) ": \
699 ss; \
700 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "; \
701 addl $2, (%esp); /* rdmsr is a 2-byte instruction */ \
702 iret \
703 ");
704
705 /*
706 * Special exception 13 handler.
707 * Accessing non-existent MSR generates general protection fault.
708 */
709 inthand_t bluetrap13;
710 __asm
711 (" \
712 .text; \
713 .p2align 2,0x90; \
714 .type " __XSTRING(CNAME(bluetrap13)) ",@function; \
715 " __XSTRING(CNAME(bluetrap13)) ": \
716 ss; \
717 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "; \
718 popl %eax; /* discard errorcode. */ \
719 addl $2, (%esp); /* rdmsr is a 2-bytes instruction. */ \
720 iret; \
721 ");
722
723 /*
724 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
725 * support cpuid instruction. This function should be called after
726 * loading interrupt descriptor table register.
727 *
728 * I don't like this method that handles fault, but I couldn't get
729 * information for any other methods. Does blue giant know?
730 */
731 static int
732 identblue(void)
733 {
734
735 trap_by_rdmsr = 0;
736
737 /*
738 * Cyrix 486-class CPU does not support rdmsr instruction.
739 * The rdmsr instruction generates invalid opcode fault, and exception
740 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
741 * bluetrap6() set the magic number to trap_by_rdmsr.
742 */
743 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
744
745 /*
746 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
747 * In this case, rdmsr generates general protection fault, and
748 * exception will be trapped by bluetrap13().
749 */
750 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
751
752 rdmsr(0x1002); /* Cyrix CPU generates fault. */
753
754 if (trap_by_rdmsr == 0xa8c1d)
755 return IDENTBLUE_CYRIX486;
756 else if (trap_by_rdmsr == 0xa89c4)
757 return IDENTBLUE_CYRIXM2;
758 return IDENTBLUE_IBMCPU;
759 }
760
761
762 /*
763 * identifycyrix() set lower 16 bits of cyrix_did as follows:
764 *
765 * F E D C B A 9 8 7 6 5 4 3 2 1 0
766 * +-------+-------+---------------+
767 * | SID | RID | Device ID |
768 * | (DIR 1) | (DIR 0) |
769 * +-------+-------+---------------+
770 */
771 static void
772 identifycyrix(void)
773 {
774 u_int eflags;
775 int ccr2_test = 0, dir_test = 0;
776 u_char ccr2, ccr3;
777
778 eflags = read_eflags();
779 disable_intr();
780
781 ccr2 = read_cyrix_reg(CCR2);
782 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
783 read_cyrix_reg(CCR2);
784 if (read_cyrix_reg(CCR2) != ccr2)
785 ccr2_test = 1;
786 write_cyrix_reg(CCR2, ccr2);
787
788 ccr3 = read_cyrix_reg(CCR3);
789 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
790 read_cyrix_reg(CCR3);
791 if (read_cyrix_reg(CCR3) != ccr3)
792 dir_test = 1; /* CPU supports DIRs. */
793 write_cyrix_reg(CCR3, ccr3);
794
795 if (dir_test) {
796 /* Device ID registers are available. */
797 cyrix_did = read_cyrix_reg(DIR1) << 8;
798 cyrix_did += read_cyrix_reg(DIR0);
799 } else if (ccr2_test)
800 cyrix_did = 0x0010; /* 486S A-step */
801 else
802 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
803
804 write_eflags(eflags);
805 }
806
807 /*
808 * Final stage of CPU identification. -- Should I check TI?
809 */
810 void
811 finishidentcpu(void)
812 {
813 int isblue = 0;
814 u_char ccr3;
815 u_int regs[4];
816
817 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
818 if (cpu == CPU_486) {
819 /*
820 * These conditions are equivalent to:
821 * - CPU does not support cpuid instruction.
822 * - Cyrix/IBM CPU is detected.
823 */
824 isblue = identblue();
825 if (isblue == IDENTBLUE_IBMCPU) {
826 strcpy(cpu_vendor, "IBM");
827 cpu = CPU_BLUE;
828 return;
829 }
830 }
831 switch (cpu_id & 0xf00) {
832 case 0x600:
833 /*
834 * Cyrix's datasheet does not describe DIRs.
835 * Therefor, I assume it does not have them
836 * and use the result of the cpuid instruction.
837 * XXX they seem to have it for now at least. -Peter
838 */
839 identifycyrix();
840 cpu = CPU_M2;
841 break;
842 default:
843 identifycyrix();
844 /*
845 * This routine contains a trick.
846 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
847 */
848 switch (cyrix_did & 0x00f0) {
849 case 0x00:
850 case 0xf0:
851 cpu = CPU_486DLC;
852 break;
853 case 0x10:
854 cpu = CPU_CY486DX;
855 break;
856 case 0x20:
857 if ((cyrix_did & 0x000f) < 8)
858 cpu = CPU_M1;
859 else
860 cpu = CPU_M1SC;
861 break;
862 case 0x30:
863 cpu = CPU_M1;
864 break;
865 case 0x40:
866 /* MediaGX CPU */
867 cpu = CPU_M1SC;
868 break;
869 default:
870 /* M2 and later CPUs are treated as M2. */
871 cpu = CPU_M2;
872
873 /*
874 * enable cpuid instruction.
875 */
876 ccr3 = read_cyrix_reg(CCR3);
877 write_cyrix_reg(CCR3, CCR3_MAPEN0);
878 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
879 write_cyrix_reg(CCR3, ccr3);
880
881 do_cpuid(0, regs);
882 cpu_high = regs[0]; /* eax */
883 do_cpuid(1, regs);
884 cpu_id = regs[0]; /* eax */
885 cpu_feature = regs[3]; /* edx */
886 break;
887 }
888 }
889 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
890 /*
891 * There are BlueLightning CPUs that do not change
892 * undefined flags by dividing 5 by 2. In this case,
893 * the CPU identification routine in locore.s leaves
894 * cpu_vendor null string and puts CPU_486 into the
895 * cpu.
896 */
897 isblue = identblue();
898 if (isblue == IDENTBLUE_IBMCPU) {
899 strcpy(cpu_vendor, "IBM");
900 cpu = CPU_BLUE;
901 return;
902 }
903 }
904 }
905
906 /*
907 * This routine is called specifically to set up cpu_class before
908 * startrtclock() uses it. Probably this should be rearranged so that
909 * startrtclock() doesn't need to run until after identifycpu() has been
910 * called. Another alternative formulation would be for this routine
911 * to do all the identification work, and make identifycpu() into a
912 * printing-only routine.
913 */
914 void
915 earlysetcpuclass(void)
916 {
917
918 cpu_class = i386_cpus[cpu].cpu_class;
919 }
920
921 static void
922 print_AMD_assoc(int i)
923 {
924 if (i == 255)
925 printf(", fully associative\n");
926 else
927 printf(", %d-way associative\n", i);
928 }
929
930 static void
931 print_AMD_info(u_int amd_maxregs)
932 {
933 quad_t amd_whcr;
934
935 if (amd_maxregs >= 0x80000005) {
936 u_int regs[4];
937
938 do_cpuid(0x80000005, regs);
939 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
940 print_AMD_assoc(regs[1] >> 24);
941 printf("Instruction TLB: %d entries", regs[1] & 0xff);
942 print_AMD_assoc((regs[1] >> 8) & 0xff);
943 printf("L1 data cache: %d kbytes", regs[2] >> 24);
944 printf(", %d bytes/line", regs[2] & 0xff);
945 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
946 print_AMD_assoc((regs[2] >> 16) & 0xff);
947 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
948 printf(", %d bytes/line", regs[3] & 0xff);
949 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
950 print_AMD_assoc((regs[3] >> 16) & 0xff);
951 if (amd_maxregs >= 0x80000006) { /* K6-III only */
952 do_cpuid(0x80000006, regs);
953 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
954 printf(", %d bytes/line", regs[2] & 0xff);
955 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
956 print_AMD_assoc((regs[2] >> 12) & 0x0f);
957 }
958 }
959 if (((cpu_id & 0xf00) == 0x500)
960 && (((cpu_id & 0x0f0) > 0x80)
961 || (((cpu_id & 0x0f0) == 0x80)
962 && (cpu_id & 0x00f) > 0x07))) {
963 /* K6-2(new core [Stepping 8-F]), K6-III or later */
964 amd_whcr = rdmsr(0xc0000082);
965 if (!(amd_whcr & (0x3ff << 22))) {
966 printf("Write Allocate Disable\n");
967 } else {
968 printf("Write Allocate Enable Limit: %dM bytes\n",
969 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
970 printf("Write Allocate 15-16M bytes: %s\n",
971 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
972 }
973 } else if (((cpu_id & 0xf00) == 0x500)
974 && ((cpu_id & 0x0f0) > 0x50)) {
975 /* K6, K6-2(old core) */
976 amd_whcr = rdmsr(0xc0000082);
977 if (!(amd_whcr & (0x7f << 1))) {
978 printf("Write Allocate Disable\n");
979 } else {
980 printf("Write Allocate Enable Limit: %dM bytes\n",
981 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
982 printf("Write Allocate 15-16M bytes: %s\n",
983 (amd_whcr & 0x0001) ? "Enable" : "Disable");
984 printf("Hardware Write Allocate Control: %s\n",
985 (amd_whcr & 0x0100) ? "Enable" : "Disable");
986 }
987 }
988 }
989
990 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
991 static void
992 print_AMD_features(u_int *regs)
993 {
994 /*
995 * Values taken from AMD Processor Recognition
996 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
997 */
998 do_cpuid(0x80000001, regs);
999 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1000 "\020" /* in hex */
1001 "\001FPU" /* Integral FPU */
1002 "\002VME" /* Extended VM86 mode support */
1003 "\003DE" /* Debug extensions */
1004 "\004PSE" /* 4MByte page tables */
1005 "\005TSC" /* Timestamp counter */
1006 "\006MSR" /* Machine specific registers */
1007 "\007PAE" /* Physical address extension */
1008 "\010MCE" /* Machine Check support */
1009 "\011CX8" /* CMPEXCH8 instruction */
1010 "\012APIC" /* SMP local APIC */
1011 "\013<b10>"
1012 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1013 "\015MTRR" /* Memory Type Range Registers */
1014 "\016PGE" /* PG_G (global bit) support */
1015 "\017MCA" /* Machine Check Architecture */
1016 "\020ICMOV" /* CMOV instruction */
1017 "\021PAT" /* Page attributes table */
1018 "\022PGE36" /* 36 bit address space support */
1019 "\023RSVD" /* Reserved, unknown */
1020 "\024MP" /* Multiprocessor Capable */
1021 "\025<b20>"
1022 "\026<b21>"
1023 "\027AMIE" /* AMD MMX Instruction Extensions */
1024 "\030MMX"
1025 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1026 "\032<b25>"
1027 "\033<b26>"
1028 "\034<b27>"
1029 "\035<b28>"
1030 "\036<b29>"
1031 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1032 "\0403DNow!"
1033 );
1034 }
1035 #endif
1036
1037 /*
1038 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1039 */
1040
1041 #define MSR_TMx86_LONGRUN 0x80868010
1042 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1043
1044 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1045 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1046 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1047
1048 #define LONGRUN_MODE_MINFREQUENCY 0x00
1049 #define LONGRUN_MODE_ECONOMY 0x01
1050 #define LONGRUN_MODE_PERFORMANCE 0x02
1051 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1052 #define LONGRUN_MODE_UNKNOWN 0x04
1053 #define LONGRUN_MODE_MAX 0x04
1054
1055 union msrinfo {
1056 u_int64_t msr;
1057 u_int32_t regs[2];
1058 };
1059
1060 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1061 /* MSR low, MSR high, flags bit0 */
1062 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1063 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1064 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1065 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1066 };
1067
1068 static u_int
1069 tmx86_get_longrun_mode(void)
1070 {
1071 u_long eflags;
1072 union msrinfo msrinfo;
1073 u_int low, high, flags, mode;
1074
1075 eflags = read_eflags();
1076 disable_intr();
1077
1078 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1079 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1080 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1081 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1082
1083 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1084 if (low == longrun_modes[mode][0] &&
1085 high == longrun_modes[mode][1] &&
1086 flags == longrun_modes[mode][2]) {
1087 goto out;
1088 }
1089 }
1090 mode = LONGRUN_MODE_UNKNOWN;
1091 out:
1092 write_eflags(eflags);
1093 return (mode);
1094 }
1095
1096 static u_int
1097 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1098 {
1099 u_long eflags;
1100 u_int regs[4];
1101
1102 eflags = read_eflags();
1103 disable_intr();
1104
1105 do_cpuid(0x80860007, regs);
1106 *frequency = regs[0];
1107 *voltage = regs[1];
1108 *percentage = regs[2];
1109
1110 write_eflags(eflags);
1111 return (1);
1112 }
1113
1114 static u_int
1115 tmx86_set_longrun_mode(u_int mode)
1116 {
1117 u_long eflags;
1118 union msrinfo msrinfo;
1119
1120 if (mode >= LONGRUN_MODE_UNKNOWN) {
1121 return (0);
1122 }
1123
1124 eflags = read_eflags();
1125 disable_intr();
1126
1127 /* Write LongRun mode values to Model Specific Register. */
1128 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1129 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1130 longrun_modes[mode][0]);
1131 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1132 longrun_modes[mode][1]);
1133 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1134
1135 /* Write LongRun mode flags to Model Specific Register. */
1136 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1137 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1138 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1139
1140 write_eflags(eflags);
1141 return (1);
1142 }
1143
1144 static u_int crusoe_longrun;
1145 static u_int crusoe_frequency;
1146 static u_int crusoe_voltage;
1147 static u_int crusoe_percentage;
1148 static u_int crusoe_performance_longrun = LONGRUN_MODE_PERFORMANCE;
1149 static u_int crusoe_economy_longrun = LONGRUN_MODE_ECONOMY;
1150 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1151 static struct sysctl_oid *crusoe_sysctl_tree;
1152
1153 static void
1154 tmx86_longrun_power_profile(void *arg)
1155 {
1156 int state;
1157 u_int new;
1158
1159 state = power_profile_get_state();
1160 if (state != POWER_PROFILE_PERFORMANCE &&
1161 state != POWER_PROFILE_ECONOMY) {
1162 return;
1163 }
1164
1165 switch (state) {
1166 case POWER_PROFILE_PERFORMANCE:
1167 new =crusoe_performance_longrun;
1168 break;
1169 case POWER_PROFILE_ECONOMY:
1170 new = crusoe_economy_longrun;
1171 break;
1172 default:
1173 new = tmx86_get_longrun_mode();
1174 break;
1175 }
1176
1177 if (tmx86_get_longrun_mode() != new) {
1178 tmx86_set_longrun_mode(new);
1179 }
1180 }
1181
1182 static int
1183 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1184 {
1185 u_int mode;
1186 int error;
1187
1188 crusoe_longrun = tmx86_get_longrun_mode();
1189 mode = crusoe_longrun;
1190 error = sysctl_handle_int(oidp, &mode, 0, req);
1191 if (error || !req->newptr) {
1192 return (error);
1193 }
1194 if (mode >= LONGRUN_MODE_UNKNOWN) {
1195 error = EINVAL;
1196 return (error);
1197 }
1198 if (crusoe_longrun != mode) {
1199 crusoe_longrun = mode;
1200 tmx86_set_longrun_mode(crusoe_longrun);
1201 }
1202
1203 return (error);
1204 }
1205
1206 static int
1207 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1208 {
1209 u_int val;
1210 int error;
1211
1212 tmx86_get_longrun_status(&crusoe_frequency,
1213 &crusoe_voltage, &crusoe_percentage);
1214 val = *(u_int *)oidp->oid_arg1;
1215 error = sysctl_handle_int(oidp, &val, 0, req);
1216 return (error);
1217 }
1218
1219 static int
1220 tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS)
1221 {
1222 u_int32_t *argp;
1223 u_int32_t arg;
1224 int error;
1225
1226 argp = (u_int32_t *)oidp->oid_arg1;
1227 arg = *argp;
1228 error = sysctl_handle_int(oidp, &arg, 0, req);
1229
1230 /* error or no new value */
1231 if ((error != 0) || (req->newptr == NULL))
1232 return (error);
1233
1234 /* range check */
1235 if (arg >= LONGRUN_MODE_UNKNOWN)
1236 return (EINVAL);
1237
1238 /* set new value and possibly switch */
1239 *argp = arg;
1240
1241 tmx86_longrun_power_profile(NULL);
1242
1243 return (0);
1244
1245 }
1246
1247 static void
1248 setup_tmx86_longrun(void)
1249 {
1250 static int done = 0;
1251
1252 if (done)
1253 return;
1254 done++;
1255
1256 sysctl_ctx_init(&crusoe_sysctl_ctx);
1257 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1258 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1259 "crusoe", CTLFLAG_RD, 0,
1260 "Transmeta Crusoe LongRun support");
1261 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1262 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1263 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1264 "LongRun mode [0-3]");
1265 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1266 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1267 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1268 "Current frequency (MHz)");
1269 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1270 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1271 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1272 "Current voltage (mV)");
1273 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1274 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1275 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1276 "Processing performance (%)");
1277 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1278 OID_AUTO, "performance_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
1279 &crusoe_performance_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
1280 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1281 OID_AUTO, "economy_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
1282 &crusoe_economy_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
1283
1284 /* register performance profile change handler */
1285 EVENTHANDLER_REGISTER(power_profile_change, tmx86_longrun_power_profile, NULL, 0);
1286
1287 }
1288
1289 static void
1290 print_transmeta_info()
1291 {
1292 u_int regs[4], nreg = 0;
1293
1294 do_cpuid(0x80860000, regs);
1295 nreg = regs[0];
1296 if (nreg >= 0x80860001) {
1297 do_cpuid(0x80860001, regs);
1298 printf(" Processor revision %u.%u.%u.%u\n",
1299 (regs[1] >> 24) & 0xff,
1300 (regs[1] >> 16) & 0xff,
1301 (regs[1] >> 8) & 0xff,
1302 regs[1] & 0xff);
1303 }
1304 if (nreg >= 0x80860002) {
1305 do_cpuid(0x80860002, regs);
1306 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1307 (regs[1] >> 24) & 0xff,
1308 (regs[1] >> 16) & 0xff,
1309 (regs[1] >> 8) & 0xff,
1310 regs[1] & 0xff,
1311 regs[2]);
1312 }
1313 if (nreg >= 0x80860006) {
1314 char info[65];
1315 do_cpuid(0x80860003, (u_int*) &info[0]);
1316 do_cpuid(0x80860004, (u_int*) &info[16]);
1317 do_cpuid(0x80860005, (u_int*) &info[32]);
1318 do_cpuid(0x80860006, (u_int*) &info[48]);
1319 info[64] = 0;
1320 printf(" %s\n", info);
1321 }
1322
1323 crusoe_longrun = tmx86_get_longrun_mode();
1324 tmx86_get_longrun_status(&crusoe_frequency,
1325 &crusoe_voltage, &crusoe_percentage);
1326 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1327 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1328 }
Cache object: ec154577cb702ea921b4f7351301bfed
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