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sys/i386/i386/identcpu.c
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1 /* 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * Copyright (c) 2001 Tamotsu Hattori. 6 * Copyright (c) 2001 Mitsuru IWASAKI. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 41 * $FreeBSD: releng/5.1/sys/i386/i386/identcpu.c 114291 2003-04-30 12:23:58Z markm $ 42 */ 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/sysctl.h> 51 #include <sys/power.h> 52 53 #include <machine/asmacros.h> 54 #include <machine/clock.h> 55 #include <machine/cputypes.h> 56 #include <machine/segments.h> 57 #include <machine/specialreg.h> 58 #include <machine/md_var.h> 59 60 #include <i386/isa/icu.h> 61 #include <i386/isa/intr_machdep.h> 62 63 #define IDENTBLUE_CYRIX486 0 64 #define IDENTBLUE_IBMCPU 1 65 #define IDENTBLUE_CYRIXM2 2 66 67 /* XXX - should be in header file: */ 68 void printcpuinfo(void); 69 void finishidentcpu(void); 70 void earlysetcpuclass(void); 71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 72 void enable_K5_wt_alloc(void); 73 void enable_K6_wt_alloc(void); 74 void enable_K6_2_wt_alloc(void); 75 #endif 76 void panicifcpuunsupported(void); 77 78 static void identifycyrix(void); 79 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 80 static void print_AMD_features(void); 81 #endif 82 static void print_AMD_info(void); 83 static void print_AMD_assoc(int i); 84 static void print_transmeta_info(void); 85 static void setup_tmx86_longrun(void); 86 87 int cpu_class; 88 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 89 u_int cyrix_did; /* Device ID of Cyrix CPU */ 90 char machine[] = "i386"; 91 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 92 machine, 0, "Machine class"); 93 94 static char cpu_model[128]; 95 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 96 cpu_model, 0, "Machine model"); 97 98 static int hw_clockrate; 99 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 100 &hw_clockrate, 0, "CPU instruction clock rate"); 101 102 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 103 static char cpu_brand[48]; 104 105 #define MAX_BRAND_INDEX 8 106 107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 108 NULL, /* No brand */ 109 "Intel Celeron", 110 "Intel Pentium III", 111 "Intel Pentium III Xeon", 112 NULL, 113 NULL, 114 NULL, 115 NULL, 116 "Intel Pentium 4" 117 }; 118 #endif 119 120 static struct cpu_nameclass i386_cpus[] = { 121 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 122 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 123 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 124 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 125 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 126 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 127 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 128 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 129 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 130 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 131 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 132 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 133 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 134 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 135 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 136 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 137 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 138 }; 139 140 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 141 int has_f00f_bug = 0; /* Initialized so that it can be patched. */ 142 #endif 143 144 void 145 printcpuinfo(void) 146 { 147 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 148 u_int regs[4], i; 149 char *brand; 150 #endif 151 152 cpu_class = i386_cpus[cpu].cpu_class; 153 printf("CPU: "); 154 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); 155 156 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 157 /* Check for extended CPUID information and a processor name. */ 158 if (cpu_high > 0 && 159 (strcmp(cpu_vendor, "GenuineIntel") == 0 || 160 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 161 strcmp(cpu_vendor, "GenuineTMx86") == 0 || 162 strcmp(cpu_vendor, "TransmetaCPU") == 0)) { 163 do_cpuid(0x80000000, regs); 164 if (regs[0] >= 0x80000000) { 165 cpu_exthigh = regs[0]; 166 if (cpu_exthigh >= 0x80000004) { 167 brand = cpu_brand; 168 for (i = 0x80000002; i < 0x80000005; i++) { 169 do_cpuid(i, regs); 170 memcpy(brand, regs, sizeof(regs)); 171 brand += sizeof(regs); 172 } 173 } 174 } 175 } 176 177 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 178 if ((cpu_id & 0xf00) > 0x300) { 179 u_int brand_index; 180 181 cpu_model[0] = '\0'; 182 183 switch (cpu_id & 0x3000) { 184 case 0x1000: 185 strcpy(cpu_model, "Overdrive "); 186 break; 187 case 0x2000: 188 strcpy(cpu_model, "Dual "); 189 break; 190 } 191 192 switch (cpu_id & 0xf00) { 193 case 0x400: 194 strcat(cpu_model, "i486 "); 195 /* Check the particular flavor of 486 */ 196 switch (cpu_id & 0xf0) { 197 case 0x00: 198 case 0x10: 199 strcat(cpu_model, "DX"); 200 break; 201 case 0x20: 202 strcat(cpu_model, "SX"); 203 break; 204 case 0x30: 205 strcat(cpu_model, "DX2"); 206 break; 207 case 0x40: 208 strcat(cpu_model, "SL"); 209 break; 210 case 0x50: 211 strcat(cpu_model, "SX2"); 212 break; 213 case 0x70: 214 strcat(cpu_model, 215 "DX2 Write-Back Enhanced"); 216 break; 217 case 0x80: 218 strcat(cpu_model, "DX4"); 219 break; 220 } 221 break; 222 case 0x500: 223 /* Check the particular flavor of 586 */ 224 strcat(cpu_model, "Pentium"); 225 switch (cpu_id & 0xf0) { 226 case 0x00: 227 strcat(cpu_model, " A-step"); 228 break; 229 case 0x10: 230 strcat(cpu_model, "/P5"); 231 break; 232 case 0x20: 233 strcat(cpu_model, "/P54C"); 234 break; 235 case 0x30: 236 strcat(cpu_model, "/P54T Overdrive"); 237 break; 238 case 0x40: 239 strcat(cpu_model, "/P55C"); 240 break; 241 case 0x70: 242 strcat(cpu_model, "/P54C"); 243 break; 244 case 0x80: 245 strcat(cpu_model, "/P55C (quarter-micron)"); 246 break; 247 default: 248 /* nothing */ 249 break; 250 } 251 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 252 /* 253 * XXX - If/when Intel fixes the bug, this 254 * should also check the version of the 255 * CPU, not just that it's a Pentium. 256 */ 257 has_f00f_bug = 1; 258 #endif 259 break; 260 case 0x600: 261 /* Check the particular flavor of 686 */ 262 switch (cpu_id & 0xf0) { 263 case 0x00: 264 strcat(cpu_model, "Pentium Pro A-step"); 265 break; 266 case 0x10: 267 strcat(cpu_model, "Pentium Pro"); 268 break; 269 case 0x30: 270 case 0x50: 271 case 0x60: 272 strcat(cpu_model, 273 "Pentium II/Pentium II Xeon/Celeron"); 274 cpu = CPU_PII; 275 break; 276 case 0x70: 277 case 0x80: 278 case 0xa0: 279 case 0xb0: 280 strcat(cpu_model, 281 "Pentium III/Pentium III Xeon/Celeron"); 282 cpu = CPU_PIII; 283 break; 284 default: 285 strcat(cpu_model, "Unknown 80686"); 286 break; 287 } 288 break; 289 case 0xf00: 290 strcat(cpu_model, "Pentium 4"); 291 cpu = CPU_P4; 292 break; 293 default: 294 strcat(cpu_model, "unknown"); 295 break; 296 } 297 298 /* 299 * If we didn't get a brand name from the extended 300 * CPUID, try to look it up in the brand table. 301 */ 302 if (cpu_high > 0 && *cpu_brand == '\0') { 303 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 304 if (brand_index <= MAX_BRAND_INDEX && 305 cpu_brandtable[brand_index] != NULL) 306 strcpy(cpu_brand, 307 cpu_brandtable[brand_index]); 308 } 309 } 310 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 311 /* 312 * Values taken from AMD Processor Recognition 313 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 314 * (also describes ``Features'' encodings. 315 */ 316 strcpy(cpu_model, "AMD "); 317 switch (cpu_id & 0xFF0) { 318 case 0x410: 319 strcat(cpu_model, "Standard Am486DX"); 320 break; 321 case 0x430: 322 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 323 break; 324 case 0x470: 325 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 326 break; 327 case 0x480: 328 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 329 break; 330 case 0x490: 331 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 332 break; 333 case 0x4E0: 334 strcat(cpu_model, "Am5x86 Write-Through"); 335 break; 336 case 0x4F0: 337 strcat(cpu_model, "Am5x86 Write-Back"); 338 break; 339 case 0x500: 340 strcat(cpu_model, "K5 model 0"); 341 tsc_is_broken = 1; 342 break; 343 case 0x510: 344 strcat(cpu_model, "K5 model 1"); 345 break; 346 case 0x520: 347 strcat(cpu_model, "K5 PR166 (model 2)"); 348 break; 349 case 0x530: 350 strcat(cpu_model, "K5 PR200 (model 3)"); 351 break; 352 case 0x560: 353 strcat(cpu_model, "K6"); 354 break; 355 case 0x570: 356 strcat(cpu_model, "K6 266 (model 1)"); 357 break; 358 case 0x580: 359 strcat(cpu_model, "K6-2"); 360 break; 361 case 0x590: 362 strcat(cpu_model, "K6-III"); 363 break; 364 default: 365 strcat(cpu_model, "Unknown"); 366 break; 367 } 368 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 369 if ((cpu_id & 0xf00) == 0x500) { 370 if (((cpu_id & 0x0f0) > 0) 371 && ((cpu_id & 0x0f0) < 0x60) 372 && ((cpu_id & 0x00f) > 3)) 373 enable_K5_wt_alloc(); 374 else if (((cpu_id & 0x0f0) > 0x80) 375 || (((cpu_id & 0x0f0) == 0x80) 376 && (cpu_id & 0x00f) > 0x07)) 377 enable_K6_2_wt_alloc(); 378 else if ((cpu_id & 0x0f0) > 0x50) 379 enable_K6_wt_alloc(); 380 } 381 #endif 382 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 383 strcpy(cpu_model, "Cyrix "); 384 switch (cpu_id & 0xff0) { 385 case 0x440: 386 strcat(cpu_model, "MediaGX"); 387 break; 388 case 0x520: 389 strcat(cpu_model, "6x86"); 390 break; 391 case 0x540: 392 cpu_class = CPUCLASS_586; 393 strcat(cpu_model, "GXm"); 394 break; 395 case 0x600: 396 strcat(cpu_model, "6x86MX"); 397 break; 398 default: 399 /* 400 * Even though CPU supports the cpuid 401 * instruction, it can be disabled. 402 * Therefore, this routine supports all Cyrix 403 * CPUs. 404 */ 405 switch (cyrix_did & 0xf0) { 406 case 0x00: 407 switch (cyrix_did & 0x0f) { 408 case 0x00: 409 strcat(cpu_model, "486SLC"); 410 break; 411 case 0x01: 412 strcat(cpu_model, "486DLC"); 413 break; 414 case 0x02: 415 strcat(cpu_model, "486SLC2"); 416 break; 417 case 0x03: 418 strcat(cpu_model, "486DLC2"); 419 break; 420 case 0x04: 421 strcat(cpu_model, "486SRx"); 422 break; 423 case 0x05: 424 strcat(cpu_model, "486DRx"); 425 break; 426 case 0x06: 427 strcat(cpu_model, "486SRx2"); 428 break; 429 case 0x07: 430 strcat(cpu_model, "486DRx2"); 431 break; 432 case 0x08: 433 strcat(cpu_model, "486SRu"); 434 break; 435 case 0x09: 436 strcat(cpu_model, "486DRu"); 437 break; 438 case 0x0a: 439 strcat(cpu_model, "486SRu2"); 440 break; 441 case 0x0b: 442 strcat(cpu_model, "486DRu2"); 443 break; 444 default: 445 strcat(cpu_model, "Unknown"); 446 break; 447 } 448 break; 449 case 0x10: 450 switch (cyrix_did & 0x0f) { 451 case 0x00: 452 strcat(cpu_model, "486S"); 453 break; 454 case 0x01: 455 strcat(cpu_model, "486S2"); 456 break; 457 case 0x02: 458 strcat(cpu_model, "486Se"); 459 break; 460 case 0x03: 461 strcat(cpu_model, "486S2e"); 462 break; 463 case 0x0a: 464 strcat(cpu_model, "486DX"); 465 break; 466 case 0x0b: 467 strcat(cpu_model, "486DX2"); 468 break; 469 case 0x0f: 470 strcat(cpu_model, "486DX4"); 471 break; 472 default: 473 strcat(cpu_model, "Unknown"); 474 break; 475 } 476 break; 477 case 0x20: 478 if ((cyrix_did & 0x0f) < 8) 479 strcat(cpu_model, "6x86"); /* Where did you get it? */ 480 else 481 strcat(cpu_model, "5x86"); 482 break; 483 case 0x30: 484 strcat(cpu_model, "6x86"); 485 break; 486 case 0x40: 487 if ((cyrix_did & 0xf000) == 0x3000) { 488 cpu_class = CPUCLASS_586; 489 strcat(cpu_model, "GXm"); 490 } else 491 strcat(cpu_model, "MediaGX"); 492 break; 493 case 0x50: 494 strcat(cpu_model, "6x86MX"); 495 break; 496 case 0xf0: 497 switch (cyrix_did & 0x0f) { 498 case 0x0d: 499 strcat(cpu_model, "Overdrive CPU"); 500 case 0x0e: 501 strcpy(cpu_model, "Texas Instruments 486SXL"); 502 break; 503 case 0x0f: 504 strcat(cpu_model, "486SLC/DLC"); 505 break; 506 default: 507 strcat(cpu_model, "Unknown"); 508 break; 509 } 510 break; 511 default: 512 strcat(cpu_model, "Unknown"); 513 break; 514 } 515 break; 516 } 517 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) { 518 strcpy(cpu_model, "Rise "); 519 switch (cpu_id & 0xff0) { 520 case 0x500: 521 strcat(cpu_model, "mP6"); 522 break; 523 default: 524 strcat(cpu_model, "Unknown"); 525 } 526 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { 527 switch (cpu_id & 0xff0) { 528 case 0x540: 529 strcpy(cpu_model, "IDT WinChip C6"); 530 tsc_is_broken = 1; 531 break; 532 case 0x580: 533 strcpy(cpu_model, "IDT WinChip 2"); 534 break; 535 case 0x670: 536 strcpy(cpu_model, "VIA C3 Samuel 2"); 537 break; 538 default: 539 strcpy(cpu_model, "VIA/IDT Unknown"); 540 } 541 } else if (strcmp(cpu_vendor, "IBM") == 0) { 542 strcpy(cpu_model, "Blue Lightning CPU"); 543 } 544 545 /* 546 * Replace cpu_model with cpu_brand minus leading spaces if 547 * we have one. 548 */ 549 brand = cpu_brand; 550 while (*brand == ' ') 551 ++brand; 552 if (*brand != '\0') 553 strcpy(cpu_model, brand); 554 555 #endif 556 557 printf("%s (", cpu_model); 558 switch(cpu_class) { 559 case CPUCLASS_286: 560 printf("286"); 561 break; 562 #if defined(I386_CPU) 563 case CPUCLASS_386: 564 printf("386"); 565 break; 566 #endif 567 #if defined(I486_CPU) 568 case CPUCLASS_486: 569 printf("486"); 570 bzero_vector = i486_bzero; 571 break; 572 #endif 573 #if defined(I586_CPU) 574 case CPUCLASS_586: 575 hw_clockrate = (tsc_freq + 5000) / 1000000; 576 printf("%jd.%02d-MHz ", 577 (intmax_t)(tsc_freq + 4999) / 1000000, 578 (u_int)((tsc_freq + 4999) / 10000) % 100); 579 printf("586"); 580 break; 581 #endif 582 #if defined(I686_CPU) 583 case CPUCLASS_686: 584 hw_clockrate = (tsc_freq + 5000) / 1000000; 585 printf("%jd.%02d-MHz ", 586 (intmax_t)(tsc_freq + 4999) / 1000000, 587 (u_int)((tsc_freq + 4999) / 10000) % 100); 588 printf("686"); 589 break; 590 #endif 591 default: 592 printf("Unknown"); /* will panic below... */ 593 } 594 printf("-class CPU)\n"); 595 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 596 if(*cpu_vendor) 597 printf(" Origin = \"%s\"",cpu_vendor); 598 if(cpu_id) 599 printf(" Id = 0x%x", cpu_id); 600 601 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 602 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 603 strcmp(cpu_vendor, "RiseRiseRise") == 0 || 604 strcmp(cpu_vendor, "CentaurHauls") == 0 || 605 ((strcmp(cpu_vendor, "CyrixInstead") == 0) && 606 ((cpu_id & 0xf00) > 0x500))) { 607 printf(" Stepping = %u", cpu_id & 0xf); 608 if (strcmp(cpu_vendor, "CyrixInstead") == 0) 609 printf(" DIR=0x%04x", cyrix_did); 610 if (cpu_high > 0) { 611 /* 612 * Here we should probably set up flags indicating 613 * whether or not various features are available. 614 * The interesting ones are probably VME, PSE, PAE, 615 * and PGE. The code already assumes without bothering 616 * to check that all CPUs >= Pentium have a TSC and 617 * MSRs. 618 */ 619 printf("\n Features=0x%b", cpu_feature, 620 "\020" 621 "\001FPU" /* Integral FPU */ 622 "\002VME" /* Extended VM86 mode support */ 623 "\003DE" /* Debugging Extensions (CR4.DE) */ 624 "\004PSE" /* 4MByte page tables */ 625 "\005TSC" /* Timestamp counter */ 626 "\006MSR" /* Machine specific registers */ 627 "\007PAE" /* Physical address extension */ 628 "\010MCE" /* Machine Check support */ 629 "\011CX8" /* CMPEXCH8 instruction */ 630 "\012APIC" /* SMP local APIC */ 631 "\013oldMTRR" /* Previous implementation of MTRR */ 632 "\014SEP" /* Fast System Call */ 633 "\015MTRR" /* Memory Type Range Registers */ 634 "\016PGE" /* PG_G (global bit) support */ 635 "\017MCA" /* Machine Check Architecture */ 636 "\020CMOV" /* CMOV instruction */ 637 "\021PAT" /* Page attributes table */ 638 "\022PSE36" /* 36 bit address space support */ 639 "\023PN" /* Processor Serial number */ 640 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 641 "\025<b20>" 642 "\026DTS" /* Debug Trace Store */ 643 "\027ACPI" /* ACPI support */ 644 "\030MMX" /* MMX instructions */ 645 "\031FXSR" /* FXSAVE/FXRSTOR */ 646 "\032SSE" /* Streaming SIMD Extensions */ 647 "\033SSE2" /* Streaming SIMD Extensions #2 */ 648 "\034SS" /* Self snoop */ 649 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 650 "\036TM" /* Thermal Monitor clock slowdown */ 651 "\037IA64" /* CPU can execute IA64 instructions */ 652 "\040PBE" /* Pending Break Enable */ 653 ); 654 655 /* 656 * If this CPU supports hyperthreading then mention 657 * the number of logical CPU's it contains. 658 */ 659 if (cpu_feature & CPUID_HTT && 660 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1) 661 printf("\n Hyperthreading: %d logical CPUs", 662 (cpu_procinfo & CPUID_HTT_CORES) >> 16); 663 } 664 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 665 cpu_exthigh >= 0x80000001) 666 print_AMD_features(); 667 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 668 printf(" DIR=0x%04x", cyrix_did); 669 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 670 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 671 #ifndef CYRIX_CACHE_REALLY_WORKS 672 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 673 printf("\n CPU cache: write-through mode"); 674 #endif 675 } 676 /* Avoid ugly blank lines: only print newline when we have to. */ 677 if (*cpu_vendor || cpu_id) 678 printf("\n"); 679 680 #endif 681 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 || 682 strcmp(cpu_vendor, "TransmetaCPU") == 0) { 683 setup_tmx86_longrun(); 684 } 685 686 if (!bootverbose) 687 return; 688 689 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 690 print_AMD_info(); 691 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 || 692 strcmp(cpu_vendor, "TransmetaCPU") == 0) 693 print_transmeta_info(); 694 695 #ifdef I686_CPU 696 /* 697 * XXX - Do PPro CPUID level=2 stuff here? 698 * 699 * No, but maybe in a print_Intel_info() function called from here. 700 */ 701 #endif 702 } 703 704 void 705 panicifcpuunsupported(void) 706 { 707 708 #if !defined(lint) 709 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 710 #error This kernel is not configured for one of the supported CPUs 711 #endif 712 #else /* lint */ 713 #endif /* lint */ 714 #if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)) 715 #error I386_CPU is mutually exclusive with the other cpu types. 716 #endif 717 /* 718 * Now that we have told the user what they have, 719 * let them know if that machine type isn't configured. 720 */ 721 switch (cpu_class) { 722 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 723 #if !defined(I386_CPU) 724 case CPUCLASS_386: 725 #endif 726 #if !defined(I486_CPU) 727 case CPUCLASS_486: 728 #endif 729 #if !defined(I586_CPU) 730 case CPUCLASS_586: 731 #endif 732 #if !defined(I686_CPU) 733 case CPUCLASS_686: 734 #endif 735 panic("CPU class not configured"); 736 default: 737 break; 738 } 739 } 740 741 742 static volatile u_int trap_by_rdmsr; 743 744 /* 745 * Special exception 6 handler. 746 * The rdmsr instruction generates invalid opcodes fault on 486-class 747 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 748 * function identblue() when this handler is called. Stacked eip should 749 * be advanced. 750 */ 751 inthand_t bluetrap6; 752 #ifdef __GNUC__ 753 __asm 754 (" \ 755 .text; \ 756 .p2align 2,0x90; \ 757 .type " __XSTRING(CNAME(bluetrap6)) ",@function; \ 758 " __XSTRING(CNAME(bluetrap6)) ": \ 759 ss; \ 760 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "; \ 761 addl $2, (%esp); /* rdmsr is a 2-byte instruction */ \ 762 iret \ 763 "); 764 #endif 765 766 /* 767 * Special exception 13 handler. 768 * Accessing non-existent MSR generates general protection fault. 769 */ 770 inthand_t bluetrap13; 771 #ifdef __GNUC__ 772 __asm 773 (" \ 774 .text; \ 775 .p2align 2,0x90; \ 776 .type " __XSTRING(CNAME(bluetrap13)) ",@function; \ 777 " __XSTRING(CNAME(bluetrap13)) ": \ 778 ss; \ 779 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "; \ 780 popl %eax; /* discard errorcode. */ \ 781 addl $2, (%esp); /* rdmsr is a 2-bytes instruction. */ \ 782 iret; \ 783 "); 784 #endif 785 786 /* 787 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 788 * support cpuid instruction. This function should be called after 789 * loading interrupt descriptor table register. 790 * 791 * I don't like this method that handles fault, but I couldn't get 792 * information for any other methods. Does blue giant know? 793 */ 794 static int 795 identblue(void) 796 { 797 798 trap_by_rdmsr = 0; 799 800 /* 801 * Cyrix 486-class CPU does not support rdmsr instruction. 802 * The rdmsr instruction generates invalid opcode fault, and exception 803 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 804 * bluetrap6() set the magic number to trap_by_rdmsr. 805 */ 806 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 807 808 /* 809 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 810 * In this case, rdmsr generates general protection fault, and 811 * exception will be trapped by bluetrap13(). 812 */ 813 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 814 815 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 816 817 if (trap_by_rdmsr == 0xa8c1d) 818 return IDENTBLUE_CYRIX486; 819 else if (trap_by_rdmsr == 0xa89c4) 820 return IDENTBLUE_CYRIXM2; 821 return IDENTBLUE_IBMCPU; 822 } 823 824 825 /* 826 * identifycyrix() set lower 16 bits of cyrix_did as follows: 827 * 828 * F E D C B A 9 8 7 6 5 4 3 2 1 0 829 * +-------+-------+---------------+ 830 * | SID | RID | Device ID | 831 * | (DIR 1) | (DIR 0) | 832 * +-------+-------+---------------+ 833 */ 834 static void 835 identifycyrix(void) 836 { 837 u_int eflags; 838 int ccr2_test = 0, dir_test = 0; 839 u_char ccr2, ccr3; 840 841 eflags = read_eflags(); 842 disable_intr(); 843 844 ccr2 = read_cyrix_reg(CCR2); 845 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 846 read_cyrix_reg(CCR2); 847 if (read_cyrix_reg(CCR2) != ccr2) 848 ccr2_test = 1; 849 write_cyrix_reg(CCR2, ccr2); 850 851 ccr3 = read_cyrix_reg(CCR3); 852 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 853 read_cyrix_reg(CCR3); 854 if (read_cyrix_reg(CCR3) != ccr3) 855 dir_test = 1; /* CPU supports DIRs. */ 856 write_cyrix_reg(CCR3, ccr3); 857 858 if (dir_test) { 859 /* Device ID registers are available. */ 860 cyrix_did = read_cyrix_reg(DIR1) << 8; 861 cyrix_did += read_cyrix_reg(DIR0); 862 } else if (ccr2_test) 863 cyrix_did = 0x0010; /* 486S A-step */ 864 else 865 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 866 867 write_eflags(eflags); 868 } 869 870 /* 871 * Final stage of CPU identification. -- Should I check TI? 872 */ 873 void 874 finishidentcpu(void) 875 { 876 int isblue = 0; 877 u_char ccr3; 878 u_int regs[4]; 879 880 if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 881 if (cpu == CPU_486) { 882 /* 883 * These conditions are equivalent to: 884 * - CPU does not support cpuid instruction. 885 * - Cyrix/IBM CPU is detected. 886 */ 887 isblue = identblue(); 888 if (isblue == IDENTBLUE_IBMCPU) { 889 strcpy(cpu_vendor, "IBM"); 890 cpu = CPU_BLUE; 891 return; 892 } 893 } 894 switch (cpu_id & 0xf00) { 895 case 0x600: 896 /* 897 * Cyrix's datasheet does not describe DIRs. 898 * Therefor, I assume it does not have them 899 * and use the result of the cpuid instruction. 900 * XXX they seem to have it for now at least. -Peter 901 */ 902 identifycyrix(); 903 cpu = CPU_M2; 904 break; 905 default: 906 identifycyrix(); 907 /* 908 * This routine contains a trick. 909 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 910 */ 911 switch (cyrix_did & 0x00f0) { 912 case 0x00: 913 case 0xf0: 914 cpu = CPU_486DLC; 915 break; 916 case 0x10: 917 cpu = CPU_CY486DX; 918 break; 919 case 0x20: 920 if ((cyrix_did & 0x000f) < 8) 921 cpu = CPU_M1; 922 else 923 cpu = CPU_M1SC; 924 break; 925 case 0x30: 926 cpu = CPU_M1; 927 break; 928 case 0x40: 929 /* MediaGX CPU */ 930 cpu = CPU_M1SC; 931 break; 932 default: 933 /* M2 and later CPUs are treated as M2. */ 934 cpu = CPU_M2; 935 936 /* 937 * enable cpuid instruction. 938 */ 939 ccr3 = read_cyrix_reg(CCR3); 940 write_cyrix_reg(CCR3, CCR3_MAPEN0); 941 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 942 write_cyrix_reg(CCR3, ccr3); 943 944 do_cpuid(0, regs); 945 cpu_high = regs[0]; /* eax */ 946 do_cpuid(1, regs); 947 cpu_id = regs[0]; /* eax */ 948 cpu_feature = regs[3]; /* edx */ 949 break; 950 } 951 } 952 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 953 /* 954 * There are BlueLightning CPUs that do not change 955 * undefined flags by dividing 5 by 2. In this case, 956 * the CPU identification routine in locore.s leaves 957 * cpu_vendor null string and puts CPU_486 into the 958 * cpu. 959 */ 960 isblue = identblue(); 961 if (isblue == IDENTBLUE_IBMCPU) { 962 strcpy(cpu_vendor, "IBM"); 963 cpu = CPU_BLUE; 964 return; 965 } 966 } 967 } 968 969 static void 970 print_AMD_assoc(int i) 971 { 972 if (i == 255) 973 printf(", fully associative\n"); 974 else 975 printf(", %d-way associative\n", i); 976 } 977 978 static void 979 print_AMD_info(void) 980 { 981 quad_t amd_whcr; 982 983 if (cpu_exthigh >= 0x80000005) { 984 u_int regs[4]; 985 986 do_cpuid(0x80000005, regs); 987 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); 988 print_AMD_assoc(regs[1] >> 24); 989 printf("Instruction TLB: %d entries", regs[1] & 0xff); 990 print_AMD_assoc((regs[1] >> 8) & 0xff); 991 printf("L1 data cache: %d kbytes", regs[2] >> 24); 992 printf(", %d bytes/line", regs[2] & 0xff); 993 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 994 print_AMD_assoc((regs[2] >> 16) & 0xff); 995 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 996 printf(", %d bytes/line", regs[3] & 0xff); 997 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 998 print_AMD_assoc((regs[3] >> 16) & 0xff); 999 if (cpu_exthigh >= 0x80000006) { /* K6-III only */ 1000 do_cpuid(0x80000006, regs); 1001 printf("L2 internal cache: %d kbytes", regs[2] >> 16); 1002 printf(", %d bytes/line", regs[2] & 0xff); 1003 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1004 print_AMD_assoc((regs[2] >> 12) & 0x0f); 1005 } 1006 } 1007 if (((cpu_id & 0xf00) == 0x500) 1008 && (((cpu_id & 0x0f0) > 0x80) 1009 || (((cpu_id & 0x0f0) == 0x80) 1010 && (cpu_id & 0x00f) > 0x07))) { 1011 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1012 amd_whcr = rdmsr(0xc0000082); 1013 if (!(amd_whcr & (0x3ff << 22))) { 1014 printf("Write Allocate Disable\n"); 1015 } else { 1016 printf("Write Allocate Enable Limit: %dM bytes\n", 1017 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1018 printf("Write Allocate 15-16M bytes: %s\n", 1019 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1020 } 1021 } else if (((cpu_id & 0xf00) == 0x500) 1022 && ((cpu_id & 0x0f0) > 0x50)) { 1023 /* K6, K6-2(old core) */ 1024 amd_whcr = rdmsr(0xc0000082); 1025 if (!(amd_whcr & (0x7f << 1))) { 1026 printf("Write Allocate Disable\n"); 1027 } else { 1028 printf("Write Allocate Enable Limit: %dM bytes\n", 1029 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1030 printf("Write Allocate 15-16M bytes: %s\n", 1031 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1032 printf("Hardware Write Allocate Control: %s\n", 1033 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1034 } 1035 } 1036 } 1037 1038 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU) 1039 static void 1040 print_AMD_features(void) 1041 { 1042 u_int regs[4]; 1043 1044 /* 1045 * Values taken from AMD Processor Recognition 1046 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf 1047 */ 1048 do_cpuid(0x80000001, regs); 1049 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature, 1050 "\020" /* in hex */ 1051 "\001FPU" /* Integral FPU */ 1052 "\002VME" /* Extended VM86 mode support */ 1053 "\003DE" /* Debug extensions */ 1054 "\004PSE" /* 4MByte page tables */ 1055 "\005TSC" /* Timestamp counter */ 1056 "\006MSR" /* Machine specific registers */ 1057 "\007PAE" /* Physical address extension */ 1058 "\010MCE" /* Machine Check support */ 1059 "\011CX8" /* CMPEXCH8 instruction */ 1060 "\012APIC" /* SMP local APIC */ 1061 "\013<b10>" 1062 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */ 1063 "\015MTRR" /* Memory Type Range Registers */ 1064 "\016PGE" /* PG_G (global bit) support */ 1065 "\017MCA" /* Machine Check Architecture */ 1066 "\020ICMOV" /* CMOV instruction */ 1067 "\021PAT" /* Page attributes table */ 1068 "\022PGE36" /* 36 bit address space support */ 1069 "\023RSVD" /* Reserved, unknown */ 1070 "\024MP" /* Multiprocessor Capable */ 1071 "\025<b20>" 1072 "\026<b21>" 1073 "\027AMIE" /* AMD MMX Instruction Extensions */ 1074 "\030MMX" 1075 "\031FXSAVE" /* FXSAVE/FXRSTOR */ 1076 "\032<b25>" 1077 "\033<b26>" 1078 "\034<b27>" 1079 "\035<b28>" 1080 "\036<b29>" 1081 "\037DSP" /* AMD 3DNow! Instruction Extensions */ 1082 "\0403DNow!" 1083 ); 1084 } 1085 #endif 1086 1087 /* 1088 * Transmeta Crusoe LongRun Support by Tamotsu Hattori. 1089 */ 1090 1091 #define MSR_TMx86_LONGRUN 0x80868010 1092 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011 1093 1094 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f) 1095 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80) 1096 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y)) 1097 1098 #define LONGRUN_MODE_MINFREQUENCY 0x00 1099 #define LONGRUN_MODE_ECONOMY 0x01 1100 #define LONGRUN_MODE_PERFORMANCE 0x02 1101 #define LONGRUN_MODE_MAXFREQUENCY 0x03 1102 #define LONGRUN_MODE_UNKNOWN 0x04 1103 #define LONGRUN_MODE_MAX 0x04 1104 1105 union msrinfo { 1106 u_int64_t msr; 1107 u_int32_t regs[2]; 1108 }; 1109 1110 static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = { 1111 /* MSR low, MSR high, flags bit0 */ 1112 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */ 1113 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */ 1114 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */ 1115 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */ 1116 }; 1117 1118 static u_int 1119 tmx86_get_longrun_mode(void) 1120 { 1121 u_long eflags; 1122 union msrinfo msrinfo; 1123 u_int low, high, flags, mode; 1124 1125 eflags = read_eflags(); 1126 disable_intr(); 1127 1128 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 1129 low = LONGRUN_MODE_MASK(msrinfo.regs[0]); 1130 high = LONGRUN_MODE_MASK(msrinfo.regs[1]); 1131 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01; 1132 1133 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) { 1134 if (low == longrun_modes[mode][0] && 1135 high == longrun_modes[mode][1] && 1136 flags == longrun_modes[mode][2]) { 1137 goto out; 1138 } 1139 } 1140 mode = LONGRUN_MODE_UNKNOWN; 1141 out: 1142 write_eflags(eflags); 1143 return (mode); 1144 } 1145 1146 static u_int 1147 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage) 1148 { 1149 u_long eflags; 1150 u_int regs[4]; 1151 1152 eflags = read_eflags(); 1153 disable_intr(); 1154 1155 do_cpuid(0x80860007, regs); 1156 *frequency = regs[0]; 1157 *voltage = regs[1]; 1158 *percentage = regs[2]; 1159 1160 write_eflags(eflags); 1161 return (1); 1162 } 1163 1164 static u_int 1165 tmx86_set_longrun_mode(u_int mode) 1166 { 1167 u_long eflags; 1168 union msrinfo msrinfo; 1169 1170 if (mode >= LONGRUN_MODE_UNKNOWN) { 1171 return (0); 1172 } 1173 1174 eflags = read_eflags(); 1175 disable_intr(); 1176 1177 /* Write LongRun mode values to Model Specific Register. */ 1178 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 1179 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0], 1180 longrun_modes[mode][0]); 1181 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1], 1182 longrun_modes[mode][1]); 1183 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); 1184 1185 /* Write LongRun mode flags to Model Specific Register. */ 1186 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); 1187 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2]; 1188 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); 1189 1190 write_eflags(eflags); 1191 return (1); 1192 } 1193 1194 static u_int crusoe_longrun; 1195 static u_int crusoe_frequency; 1196 static u_int crusoe_voltage; 1197 static u_int crusoe_percentage; 1198 static u_int crusoe_performance_longrun = LONGRUN_MODE_PERFORMANCE; 1199 static u_int crusoe_economy_longrun = LONGRUN_MODE_ECONOMY; 1200 static struct sysctl_ctx_list crusoe_sysctl_ctx; 1201 static struct sysctl_oid *crusoe_sysctl_tree; 1202 1203 static void 1204 tmx86_longrun_power_profile(void *arg) 1205 { 1206 int state; 1207 u_int new; 1208 1209 state = power_profile_get_state(); 1210 if (state != POWER_PROFILE_PERFORMANCE && 1211 state != POWER_PROFILE_ECONOMY) { 1212 return; 1213 } 1214 1215 switch (state) { 1216 case POWER_PROFILE_PERFORMANCE: 1217 new =crusoe_performance_longrun; 1218 break; 1219 case POWER_PROFILE_ECONOMY: 1220 new = crusoe_economy_longrun; 1221 break; 1222 default: 1223 new = tmx86_get_longrun_mode(); 1224 break; 1225 } 1226 1227 if (tmx86_get_longrun_mode() != new) { 1228 tmx86_set_longrun_mode(new); 1229 } 1230 } 1231 1232 static int 1233 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS) 1234 { 1235 u_int mode; 1236 int error; 1237 1238 crusoe_longrun = tmx86_get_longrun_mode(); 1239 mode = crusoe_longrun; 1240 error = sysctl_handle_int(oidp, &mode, 0, req); 1241 if (error || !req->newptr) { 1242 return (error); 1243 } 1244 if (mode >= LONGRUN_MODE_UNKNOWN) { 1245 error = EINVAL; 1246 return (error); 1247 } 1248 if (crusoe_longrun != mode) { 1249 crusoe_longrun = mode; 1250 tmx86_set_longrun_mode(crusoe_longrun); 1251 } 1252 1253 return (error); 1254 } 1255 1256 static int 1257 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS) 1258 { 1259 u_int val; 1260 int error; 1261 1262 tmx86_get_longrun_status(&crusoe_frequency, 1263 &crusoe_voltage, &crusoe_percentage); 1264 val = *(u_int *)oidp->oid_arg1; 1265 error = sysctl_handle_int(oidp, &val, 0, req); 1266 return (error); 1267 } 1268 1269 static int 1270 tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS) 1271 { 1272 u_int32_t *argp; 1273 u_int32_t arg; 1274 int error; 1275 1276 argp = (u_int32_t *)oidp->oid_arg1; 1277 arg = *argp; 1278 error = sysctl_handle_int(oidp, &arg, 0, req); 1279 1280 /* error or no new value */ 1281 if ((error != 0) || (req->newptr == NULL)) 1282 return (error); 1283 1284 /* range check */ 1285 if (arg >= LONGRUN_MODE_UNKNOWN) 1286 return (EINVAL); 1287 1288 /* set new value and possibly switch */ 1289 *argp = arg; 1290 1291 tmx86_longrun_power_profile(NULL); 1292 1293 return (0); 1294 1295 } 1296 1297 static void 1298 setup_tmx86_longrun(void) 1299 { 1300 static int done = 0; 1301 1302 if (done) 1303 return; 1304 done++; 1305 1306 sysctl_ctx_init(&crusoe_sysctl_ctx); 1307 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx, 1308 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 1309 "crusoe", CTLFLAG_RD, 0, 1310 "Transmeta Crusoe LongRun support"); 1311 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1312 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW, 1313 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I", 1314 "LongRun mode [0-3]"); 1315 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1316 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD, 1317 &crusoe_frequency, 0, tmx86_status_sysctl, "I", 1318 "Current frequency (MHz)"); 1319 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1320 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD, 1321 &crusoe_voltage, 0, tmx86_status_sysctl, "I", 1322 "Current voltage (mV)"); 1323 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1324 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD, 1325 &crusoe_percentage, 0, tmx86_status_sysctl, "I", 1326 "Processing performance (%)"); 1327 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1328 OID_AUTO, "performance_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW, 1329 &crusoe_performance_longrun, 0, tmx86_longrun_profile_sysctl, "I", ""); 1330 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 1331 OID_AUTO, "economy_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW, 1332 &crusoe_economy_longrun, 0, tmx86_longrun_profile_sysctl, "I", ""); 1333 1334 /* register performance profile change handler */ 1335 EVENTHANDLER_REGISTER(power_profile_change, tmx86_longrun_power_profile, NULL, 0); 1336 1337 } 1338 1339 static void 1340 print_transmeta_info() 1341 { 1342 u_int regs[4], nreg = 0; 1343 1344 do_cpuid(0x80860000, regs); 1345 nreg = regs[0]; 1346 if (nreg >= 0x80860001) { 1347 do_cpuid(0x80860001, regs); 1348 printf(" Processor revision %u.%u.%u.%u\n", 1349 (regs[1] >> 24) & 0xff, 1350 (regs[1] >> 16) & 0xff, 1351 (regs[1] >> 8) & 0xff, 1352 regs[1] & 0xff); 1353 } 1354 if (nreg >= 0x80860002) { 1355 do_cpuid(0x80860002, regs); 1356 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 1357 (regs[1] >> 24) & 0xff, 1358 (regs[1] >> 16) & 0xff, 1359 (regs[1] >> 8) & 0xff, 1360 regs[1] & 0xff, 1361 regs[2]); 1362 } 1363 if (nreg >= 0x80860006) { 1364 char info[65]; 1365 do_cpuid(0x80860003, (u_int*) &info[0]); 1366 do_cpuid(0x80860004, (u_int*) &info[16]); 1367 do_cpuid(0x80860005, (u_int*) &info[32]); 1368 do_cpuid(0x80860006, (u_int*) &info[48]); 1369 info[64] = 0; 1370 printf(" %s\n", info); 1371 } 1372 1373 crusoe_longrun = tmx86_get_longrun_mode(); 1374 tmx86_get_longrun_status(&crusoe_frequency, 1375 &crusoe_voltage, &crusoe_percentage); 1376 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun, 1377 crusoe_frequency, crusoe_voltage, crusoe_percentage); 1378 }
Cache object: bc0aaee2957a4314eab5f280740aa415
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