1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 */
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD: releng/5.2/sys/i386/i386/identcpu.c 122000 2003-11-03 22:38:00Z jhb $");
45
46 #include "opt_cpu.h"
47
48 #include <sys/param.h>
49 #include <sys/bus.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
54
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
62
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
66
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
75 #endif
76 void panicifcpuunsupported(void);
77
78 static void identifycyrix(void);
79 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
80 static void print_AMD_features(void);
81 #endif
82 static void print_AMD_info(void);
83 static void print_AMD_assoc(int i);
84 static void print_transmeta_info(void);
85 static void setup_tmx86_longrun(void);
86
87 int cpu_class;
88 u_int cpu_exthigh; /* Highest arg to extended CPUID */
89 u_int cyrix_did; /* Device ID of Cyrix CPU */
90 char machine[] = "i386";
91 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
92 machine, 0, "Machine class");
93
94 static char cpu_model[128];
95 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
96 cpu_model, 0, "Machine model");
97
98 static int hw_clockrate;
99 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
100 &hw_clockrate, 0, "CPU instruction clock rate");
101
102 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
103 static char cpu_brand[48];
104
105 #define MAX_BRAND_INDEX 8
106
107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
108 NULL, /* No brand */
109 "Intel Celeron",
110 "Intel Pentium III",
111 "Intel Pentium III Xeon",
112 NULL,
113 NULL,
114 NULL,
115 NULL,
116 "Intel Pentium 4"
117 };
118 #endif
119
120 static struct cpu_nameclass i386_cpus[] = {
121 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
122 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
123 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
124 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
125 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
126 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
127 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
128 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
129 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
130 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
131 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
132 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
133 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
134 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
135 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
136 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
137 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
138 };
139
140 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
141 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
142 #endif
143
144 void
145 printcpuinfo(void)
146 {
147 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
148 u_int regs[4], i;
149 char *brand;
150 #endif
151
152 cpu_class = i386_cpus[cpu].cpu_class;
153 printf("CPU: ");
154 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
155
156 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
157 /* Check for extended CPUID information and a processor name. */
158 if (cpu_high > 0 &&
159 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
160 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
161 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
162 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
163 strcmp(cpu_vendor, "Geode by NSC") == 0)) {
164 do_cpuid(0x80000000, regs);
165 if (regs[0] >= 0x80000000) {
166 cpu_exthigh = regs[0];
167 if (cpu_exthigh >= 0x80000004) {
168 brand = cpu_brand;
169 for (i = 0x80000002; i < 0x80000005; i++) {
170 do_cpuid(i, regs);
171 memcpy(brand, regs, sizeof(regs));
172 brand += sizeof(regs);
173 }
174 }
175 }
176 }
177
178 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
179 if ((cpu_id & 0xf00) > 0x300) {
180 u_int brand_index;
181
182 cpu_model[0] = '\0';
183
184 switch (cpu_id & 0x3000) {
185 case 0x1000:
186 strcpy(cpu_model, "Overdrive ");
187 break;
188 case 0x2000:
189 strcpy(cpu_model, "Dual ");
190 break;
191 }
192
193 switch (cpu_id & 0xf00) {
194 case 0x400:
195 strcat(cpu_model, "i486 ");
196 /* Check the particular flavor of 486 */
197 switch (cpu_id & 0xf0) {
198 case 0x00:
199 case 0x10:
200 strcat(cpu_model, "DX");
201 break;
202 case 0x20:
203 strcat(cpu_model, "SX");
204 break;
205 case 0x30:
206 strcat(cpu_model, "DX2");
207 break;
208 case 0x40:
209 strcat(cpu_model, "SL");
210 break;
211 case 0x50:
212 strcat(cpu_model, "SX2");
213 break;
214 case 0x70:
215 strcat(cpu_model,
216 "DX2 Write-Back Enhanced");
217 break;
218 case 0x80:
219 strcat(cpu_model, "DX4");
220 break;
221 }
222 break;
223 case 0x500:
224 /* Check the particular flavor of 586 */
225 strcat(cpu_model, "Pentium");
226 switch (cpu_id & 0xf0) {
227 case 0x00:
228 strcat(cpu_model, " A-step");
229 break;
230 case 0x10:
231 strcat(cpu_model, "/P5");
232 break;
233 case 0x20:
234 strcat(cpu_model, "/P54C");
235 break;
236 case 0x30:
237 strcat(cpu_model, "/P54T Overdrive");
238 break;
239 case 0x40:
240 strcat(cpu_model, "/P55C");
241 break;
242 case 0x70:
243 strcat(cpu_model, "/P54C");
244 break;
245 case 0x80:
246 strcat(cpu_model, "/P55C (quarter-micron)");
247 break;
248 default:
249 /* nothing */
250 break;
251 }
252 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
253 /*
254 * XXX - If/when Intel fixes the bug, this
255 * should also check the version of the
256 * CPU, not just that it's a Pentium.
257 */
258 has_f00f_bug = 1;
259 #endif
260 break;
261 case 0x600:
262 /* Check the particular flavor of 686 */
263 switch (cpu_id & 0xf0) {
264 case 0x00:
265 strcat(cpu_model, "Pentium Pro A-step");
266 break;
267 case 0x10:
268 strcat(cpu_model, "Pentium Pro");
269 break;
270 case 0x30:
271 case 0x50:
272 case 0x60:
273 strcat(cpu_model,
274 "Pentium II/Pentium II Xeon/Celeron");
275 cpu = CPU_PII;
276 break;
277 case 0x70:
278 case 0x80:
279 case 0xa0:
280 case 0xb0:
281 strcat(cpu_model,
282 "Pentium III/Pentium III Xeon/Celeron");
283 cpu = CPU_PIII;
284 break;
285 default:
286 strcat(cpu_model, "Unknown 80686");
287 break;
288 }
289 break;
290 case 0xf00:
291 strcat(cpu_model, "Pentium 4");
292 cpu = CPU_P4;
293 break;
294 default:
295 strcat(cpu_model, "unknown");
296 break;
297 }
298
299 /*
300 * If we didn't get a brand name from the extended
301 * CPUID, try to look it up in the brand table.
302 */
303 if (cpu_high > 0 && *cpu_brand == '\0') {
304 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
305 if (brand_index <= MAX_BRAND_INDEX &&
306 cpu_brandtable[brand_index] != NULL)
307 strcpy(cpu_brand,
308 cpu_brandtable[brand_index]);
309 }
310 }
311 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
312 /*
313 * Values taken from AMD Processor Recognition
314 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
315 * (also describes ``Features'' encodings.
316 */
317 strcpy(cpu_model, "AMD ");
318 switch (cpu_id & 0xFF0) {
319 case 0x410:
320 strcat(cpu_model, "Standard Am486DX");
321 break;
322 case 0x430:
323 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
324 break;
325 case 0x470:
326 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
327 break;
328 case 0x480:
329 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
330 break;
331 case 0x490:
332 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
333 break;
334 case 0x4E0:
335 strcat(cpu_model, "Am5x86 Write-Through");
336 break;
337 case 0x4F0:
338 strcat(cpu_model, "Am5x86 Write-Back");
339 break;
340 case 0x500:
341 strcat(cpu_model, "K5 model 0");
342 tsc_is_broken = 1;
343 break;
344 case 0x510:
345 strcat(cpu_model, "K5 model 1");
346 break;
347 case 0x520:
348 strcat(cpu_model, "K5 PR166 (model 2)");
349 break;
350 case 0x530:
351 strcat(cpu_model, "K5 PR200 (model 3)");
352 break;
353 case 0x560:
354 strcat(cpu_model, "K6");
355 break;
356 case 0x570:
357 strcat(cpu_model, "K6 266 (model 1)");
358 break;
359 case 0x580:
360 strcat(cpu_model, "K6-2");
361 break;
362 case 0x590:
363 strcat(cpu_model, "K6-III");
364 break;
365 default:
366 strcat(cpu_model, "Unknown");
367 break;
368 }
369 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
370 if ((cpu_id & 0xf00) == 0x500) {
371 if (((cpu_id & 0x0f0) > 0)
372 && ((cpu_id & 0x0f0) < 0x60)
373 && ((cpu_id & 0x00f) > 3))
374 enable_K5_wt_alloc();
375 else if (((cpu_id & 0x0f0) > 0x80)
376 || (((cpu_id & 0x0f0) == 0x80)
377 && (cpu_id & 0x00f) > 0x07))
378 enable_K6_2_wt_alloc();
379 else if ((cpu_id & 0x0f0) > 0x50)
380 enable_K6_wt_alloc();
381 }
382 #endif
383 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
384 strcpy(cpu_model, "Cyrix ");
385 switch (cpu_id & 0xff0) {
386 case 0x440:
387 strcat(cpu_model, "MediaGX");
388 break;
389 case 0x520:
390 strcat(cpu_model, "6x86");
391 break;
392 case 0x540:
393 cpu_class = CPUCLASS_586;
394 strcat(cpu_model, "GXm");
395 break;
396 case 0x600:
397 strcat(cpu_model, "6x86MX");
398 break;
399 default:
400 /*
401 * Even though CPU supports the cpuid
402 * instruction, it can be disabled.
403 * Therefore, this routine supports all Cyrix
404 * CPUs.
405 */
406 switch (cyrix_did & 0xf0) {
407 case 0x00:
408 switch (cyrix_did & 0x0f) {
409 case 0x00:
410 strcat(cpu_model, "486SLC");
411 break;
412 case 0x01:
413 strcat(cpu_model, "486DLC");
414 break;
415 case 0x02:
416 strcat(cpu_model, "486SLC2");
417 break;
418 case 0x03:
419 strcat(cpu_model, "486DLC2");
420 break;
421 case 0x04:
422 strcat(cpu_model, "486SRx");
423 break;
424 case 0x05:
425 strcat(cpu_model, "486DRx");
426 break;
427 case 0x06:
428 strcat(cpu_model, "486SRx2");
429 break;
430 case 0x07:
431 strcat(cpu_model, "486DRx2");
432 break;
433 case 0x08:
434 strcat(cpu_model, "486SRu");
435 break;
436 case 0x09:
437 strcat(cpu_model, "486DRu");
438 break;
439 case 0x0a:
440 strcat(cpu_model, "486SRu2");
441 break;
442 case 0x0b:
443 strcat(cpu_model, "486DRu2");
444 break;
445 default:
446 strcat(cpu_model, "Unknown");
447 break;
448 }
449 break;
450 case 0x10:
451 switch (cyrix_did & 0x0f) {
452 case 0x00:
453 strcat(cpu_model, "486S");
454 break;
455 case 0x01:
456 strcat(cpu_model, "486S2");
457 break;
458 case 0x02:
459 strcat(cpu_model, "486Se");
460 break;
461 case 0x03:
462 strcat(cpu_model, "486S2e");
463 break;
464 case 0x0a:
465 strcat(cpu_model, "486DX");
466 break;
467 case 0x0b:
468 strcat(cpu_model, "486DX2");
469 break;
470 case 0x0f:
471 strcat(cpu_model, "486DX4");
472 break;
473 default:
474 strcat(cpu_model, "Unknown");
475 break;
476 }
477 break;
478 case 0x20:
479 if ((cyrix_did & 0x0f) < 8)
480 strcat(cpu_model, "6x86"); /* Where did you get it? */
481 else
482 strcat(cpu_model, "5x86");
483 break;
484 case 0x30:
485 strcat(cpu_model, "6x86");
486 break;
487 case 0x40:
488 if ((cyrix_did & 0xf000) == 0x3000) {
489 cpu_class = CPUCLASS_586;
490 strcat(cpu_model, "GXm");
491 } else
492 strcat(cpu_model, "MediaGX");
493 break;
494 case 0x50:
495 strcat(cpu_model, "6x86MX");
496 break;
497 case 0xf0:
498 switch (cyrix_did & 0x0f) {
499 case 0x0d:
500 strcat(cpu_model, "Overdrive CPU");
501 break;
502 case 0x0e:
503 strcpy(cpu_model, "Texas Instruments 486SXL");
504 break;
505 case 0x0f:
506 strcat(cpu_model, "486SLC/DLC");
507 break;
508 default:
509 strcat(cpu_model, "Unknown");
510 break;
511 }
512 break;
513 default:
514 strcat(cpu_model, "Unknown");
515 break;
516 }
517 break;
518 }
519 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
520 strcpy(cpu_model, "Rise ");
521 switch (cpu_id & 0xff0) {
522 case 0x500:
523 strcat(cpu_model, "mP6");
524 break;
525 default:
526 strcat(cpu_model, "Unknown");
527 }
528 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
529 switch (cpu_id & 0xff0) {
530 case 0x540:
531 strcpy(cpu_model, "IDT WinChip C6");
532 tsc_is_broken = 1;
533 break;
534 case 0x580:
535 strcpy(cpu_model, "IDT WinChip 2");
536 break;
537 case 0x660:
538 strcpy(cpu_model, "VIA C3 Samuel");
539 break;
540 case 0x670:
541 if (cpu_id & 0x8)
542 strcpy(cpu_model, "VIA C3 Ezra");
543 else
544 strcpy(cpu_model, "VIA C3 Samuel 2");
545 break;
546 case 0x680:
547 strcpy(cpu_model, "VIA C3 Ezra-T");
548 break;
549 case 0x690:
550 strcpy(cpu_model, "VIA C3 Nehemiah");
551 break;
552 default:
553 strcpy(cpu_model, "VIA/IDT Unknown");
554 }
555 } else if (strcmp(cpu_vendor, "IBM") == 0) {
556 strcpy(cpu_model, "Blue Lightning CPU");
557 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
558 switch (cpu_id & 0xfff) {
559 case 0x540:
560 strcpy(cpu_model, "Geode SC1100");
561 tsc_is_broken = 1;
562 break;
563 default:
564 strcpy(cpu_model, "Geode/NSC unknown");
565 break;
566 }
567 }
568
569 /*
570 * Replace cpu_model with cpu_brand minus leading spaces if
571 * we have one.
572 */
573 brand = cpu_brand;
574 while (*brand == ' ')
575 ++brand;
576 if (*brand != '\0')
577 strcpy(cpu_model, brand);
578
579 #endif
580
581 printf("%s (", cpu_model);
582 switch(cpu_class) {
583 case CPUCLASS_286:
584 printf("286");
585 break;
586 #if defined(I386_CPU)
587 case CPUCLASS_386:
588 printf("386");
589 break;
590 #endif
591 #if defined(I486_CPU)
592 case CPUCLASS_486:
593 printf("486");
594 bzero_vector = i486_bzero;
595 break;
596 #endif
597 #if defined(I586_CPU)
598 case CPUCLASS_586:
599 hw_clockrate = (tsc_freq + 5000) / 1000000;
600 printf("%jd.%02d-MHz ",
601 (intmax_t)(tsc_freq + 4999) / 1000000,
602 (u_int)((tsc_freq + 4999) / 10000) % 100);
603 printf("586");
604 break;
605 #endif
606 #if defined(I686_CPU)
607 case CPUCLASS_686:
608 hw_clockrate = (tsc_freq + 5000) / 1000000;
609 printf("%jd.%02d-MHz ",
610 (intmax_t)(tsc_freq + 4999) / 1000000,
611 (u_int)((tsc_freq + 4999) / 10000) % 100);
612 printf("686");
613 break;
614 #endif
615 default:
616 printf("Unknown"); /* will panic below... */
617 }
618 printf("-class CPU)\n");
619 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
620 if(*cpu_vendor)
621 printf(" Origin = \"%s\"",cpu_vendor);
622 if(cpu_id)
623 printf(" Id = 0x%x", cpu_id);
624
625 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
626 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
627 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
628 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
629 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
630 ((cpu_id & 0xf00) > 0x500))) {
631 printf(" Stepping = %u", cpu_id & 0xf);
632 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
633 printf(" DIR=0x%04x", cyrix_did);
634 if (cpu_high > 0) {
635 /*
636 * Here we should probably set up flags indicating
637 * whether or not various features are available.
638 * The interesting ones are probably VME, PSE, PAE,
639 * and PGE. The code already assumes without bothering
640 * to check that all CPUs >= Pentium have a TSC and
641 * MSRs.
642 */
643 printf("\n Features=0x%b", cpu_feature,
644 "\020"
645 "\001FPU" /* Integral FPU */
646 "\002VME" /* Extended VM86 mode support */
647 "\003DE" /* Debugging Extensions (CR4.DE) */
648 "\004PSE" /* 4MByte page tables */
649 "\005TSC" /* Timestamp counter */
650 "\006MSR" /* Machine specific registers */
651 "\007PAE" /* Physical address extension */
652 "\010MCE" /* Machine Check support */
653 "\011CX8" /* CMPEXCH8 instruction */
654 "\012APIC" /* SMP local APIC */
655 "\013oldMTRR" /* Previous implementation of MTRR */
656 "\014SEP" /* Fast System Call */
657 "\015MTRR" /* Memory Type Range Registers */
658 "\016PGE" /* PG_G (global bit) support */
659 "\017MCA" /* Machine Check Architecture */
660 "\020CMOV" /* CMOV instruction */
661 "\021PAT" /* Page attributes table */
662 "\022PSE36" /* 36 bit address space support */
663 "\023PN" /* Processor Serial number */
664 "\024CLFLUSH" /* Has the CLFLUSH instruction */
665 "\025<b20>"
666 "\026DTS" /* Debug Trace Store */
667 "\027ACPI" /* ACPI support */
668 "\030MMX" /* MMX instructions */
669 "\031FXSR" /* FXSAVE/FXRSTOR */
670 "\032SSE" /* Streaming SIMD Extensions */
671 "\033SSE2" /* Streaming SIMD Extensions #2 */
672 "\034SS" /* Self snoop */
673 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
674 "\036TM" /* Thermal Monitor clock slowdown */
675 "\037IA64" /* CPU can execute IA64 instructions */
676 "\040PBE" /* Pending Break Enable */
677 );
678
679 /*
680 * If this CPU supports hyperthreading then mention
681 * the number of logical CPU's it contains.
682 */
683 if (cpu_feature & CPUID_HTT &&
684 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
685 printf("\n Hyperthreading: %d logical CPUs",
686 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
687 }
688 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
689 cpu_exthigh >= 0x80000001)
690 print_AMD_features();
691 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
692 printf(" DIR=0x%04x", cyrix_did);
693 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
694 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
695 #ifndef CYRIX_CACHE_REALLY_WORKS
696 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
697 printf("\n CPU cache: write-through mode");
698 #endif
699 }
700 /* Avoid ugly blank lines: only print newline when we have to. */
701 if (*cpu_vendor || cpu_id)
702 printf("\n");
703
704 #endif
705 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
706 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
707 setup_tmx86_longrun();
708 }
709
710 if (!bootverbose)
711 return;
712
713 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
714 print_AMD_info();
715 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
716 strcmp(cpu_vendor, "TransmetaCPU") == 0)
717 print_transmeta_info();
718
719 #ifdef I686_CPU
720 /*
721 * XXX - Do PPro CPUID level=2 stuff here?
722 *
723 * No, but maybe in a print_Intel_info() function called from here.
724 */
725 #endif
726 }
727
728 void
729 panicifcpuunsupported(void)
730 {
731
732 #if !defined(lint)
733 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
734 #error This kernel is not configured for one of the supported CPUs
735 #endif
736 #else /* lint */
737 #endif /* lint */
738 #if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
739 #error I386_CPU is mutually exclusive with the other cpu types.
740 #endif
741 /*
742 * Now that we have told the user what they have,
743 * let them know if that machine type isn't configured.
744 */
745 switch (cpu_class) {
746 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
747 #if !defined(I386_CPU)
748 case CPUCLASS_386:
749 #endif
750 #if !defined(I486_CPU)
751 case CPUCLASS_486:
752 #endif
753 #if !defined(I586_CPU)
754 case CPUCLASS_586:
755 #endif
756 #if !defined(I686_CPU)
757 case CPUCLASS_686:
758 #endif
759 panic("CPU class not configured");
760 default:
761 break;
762 }
763 }
764
765
766 static volatile u_int trap_by_rdmsr;
767
768 /*
769 * Special exception 6 handler.
770 * The rdmsr instruction generates invalid opcodes fault on 486-class
771 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
772 * function identblue() when this handler is called. Stacked eip should
773 * be advanced.
774 */
775 inthand_t bluetrap6;
776 #ifdef __GNUC__
777 __asm
778 (" \n\
779 .text \n\
780 .p2align 2,0x90 \n\
781 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
782 " __XSTRING(CNAME(bluetrap6)) ": \n\
783 ss \n\
784 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
785 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
786 iret \n\
787 ");
788 #endif
789
790 /*
791 * Special exception 13 handler.
792 * Accessing non-existent MSR generates general protection fault.
793 */
794 inthand_t bluetrap13;
795 #ifdef __GNUC__
796 __asm
797 (" \n\
798 .text \n\
799 .p2align 2,0x90 \n\
800 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
801 " __XSTRING(CNAME(bluetrap13)) ": \n\
802 ss \n\
803 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
804 popl %eax /* discard error code */ \n\
805 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
806 iret \n\
807 ");
808 #endif
809
810 /*
811 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
812 * support cpuid instruction. This function should be called after
813 * loading interrupt descriptor table register.
814 *
815 * I don't like this method that handles fault, but I couldn't get
816 * information for any other methods. Does blue giant know?
817 */
818 static int
819 identblue(void)
820 {
821
822 trap_by_rdmsr = 0;
823
824 /*
825 * Cyrix 486-class CPU does not support rdmsr instruction.
826 * The rdmsr instruction generates invalid opcode fault, and exception
827 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
828 * bluetrap6() set the magic number to trap_by_rdmsr.
829 */
830 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
831 GSEL(GCODE_SEL, SEL_KPL));
832
833 /*
834 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
835 * In this case, rdmsr generates general protection fault, and
836 * exception will be trapped by bluetrap13().
837 */
838 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
839 GSEL(GCODE_SEL, SEL_KPL));
840
841 rdmsr(0x1002); /* Cyrix CPU generates fault. */
842
843 if (trap_by_rdmsr == 0xa8c1d)
844 return IDENTBLUE_CYRIX486;
845 else if (trap_by_rdmsr == 0xa89c4)
846 return IDENTBLUE_CYRIXM2;
847 return IDENTBLUE_IBMCPU;
848 }
849
850
851 /*
852 * identifycyrix() set lower 16 bits of cyrix_did as follows:
853 *
854 * F E D C B A 9 8 7 6 5 4 3 2 1 0
855 * +-------+-------+---------------+
856 * | SID | RID | Device ID |
857 * | (DIR 1) | (DIR 0) |
858 * +-------+-------+---------------+
859 */
860 static void
861 identifycyrix(void)
862 {
863 u_int eflags;
864 int ccr2_test = 0, dir_test = 0;
865 u_char ccr2, ccr3;
866
867 eflags = read_eflags();
868 disable_intr();
869
870 ccr2 = read_cyrix_reg(CCR2);
871 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
872 read_cyrix_reg(CCR2);
873 if (read_cyrix_reg(CCR2) != ccr2)
874 ccr2_test = 1;
875 write_cyrix_reg(CCR2, ccr2);
876
877 ccr3 = read_cyrix_reg(CCR3);
878 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
879 read_cyrix_reg(CCR3);
880 if (read_cyrix_reg(CCR3) != ccr3)
881 dir_test = 1; /* CPU supports DIRs. */
882 write_cyrix_reg(CCR3, ccr3);
883
884 if (dir_test) {
885 /* Device ID registers are available. */
886 cyrix_did = read_cyrix_reg(DIR1) << 8;
887 cyrix_did += read_cyrix_reg(DIR0);
888 } else if (ccr2_test)
889 cyrix_did = 0x0010; /* 486S A-step */
890 else
891 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
892
893 write_eflags(eflags);
894 }
895
896 /*
897 * Final stage of CPU identification. -- Should I check TI?
898 */
899 void
900 finishidentcpu(void)
901 {
902 int isblue = 0;
903 u_char ccr3;
904 u_int regs[4];
905
906 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
907 if (cpu == CPU_486) {
908 /*
909 * These conditions are equivalent to:
910 * - CPU does not support cpuid instruction.
911 * - Cyrix/IBM CPU is detected.
912 */
913 isblue = identblue();
914 if (isblue == IDENTBLUE_IBMCPU) {
915 strcpy(cpu_vendor, "IBM");
916 cpu = CPU_BLUE;
917 return;
918 }
919 }
920 switch (cpu_id & 0xf00) {
921 case 0x600:
922 /*
923 * Cyrix's datasheet does not describe DIRs.
924 * Therefor, I assume it does not have them
925 * and use the result of the cpuid instruction.
926 * XXX they seem to have it for now at least. -Peter
927 */
928 identifycyrix();
929 cpu = CPU_M2;
930 break;
931 default:
932 identifycyrix();
933 /*
934 * This routine contains a trick.
935 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
936 */
937 switch (cyrix_did & 0x00f0) {
938 case 0x00:
939 case 0xf0:
940 cpu = CPU_486DLC;
941 break;
942 case 0x10:
943 cpu = CPU_CY486DX;
944 break;
945 case 0x20:
946 if ((cyrix_did & 0x000f) < 8)
947 cpu = CPU_M1;
948 else
949 cpu = CPU_M1SC;
950 break;
951 case 0x30:
952 cpu = CPU_M1;
953 break;
954 case 0x40:
955 /* MediaGX CPU */
956 cpu = CPU_M1SC;
957 break;
958 default:
959 /* M2 and later CPUs are treated as M2. */
960 cpu = CPU_M2;
961
962 /*
963 * enable cpuid instruction.
964 */
965 ccr3 = read_cyrix_reg(CCR3);
966 write_cyrix_reg(CCR3, CCR3_MAPEN0);
967 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
968 write_cyrix_reg(CCR3, ccr3);
969
970 do_cpuid(0, regs);
971 cpu_high = regs[0]; /* eax */
972 do_cpuid(1, regs);
973 cpu_id = regs[0]; /* eax */
974 cpu_feature = regs[3]; /* edx */
975 break;
976 }
977 }
978 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
979 /*
980 * There are BlueLightning CPUs that do not change
981 * undefined flags by dividing 5 by 2. In this case,
982 * the CPU identification routine in locore.s leaves
983 * cpu_vendor null string and puts CPU_486 into the
984 * cpu.
985 */
986 isblue = identblue();
987 if (isblue == IDENTBLUE_IBMCPU) {
988 strcpy(cpu_vendor, "IBM");
989 cpu = CPU_BLUE;
990 return;
991 }
992 }
993 }
994
995 static void
996 print_AMD_assoc(int i)
997 {
998 if (i == 255)
999 printf(", fully associative\n");
1000 else
1001 printf(", %d-way associative\n", i);
1002 }
1003
1004 static void
1005 print_AMD_info(void)
1006 {
1007 quad_t amd_whcr;
1008
1009 if (cpu_exthigh >= 0x80000005) {
1010 u_int regs[4];
1011
1012 do_cpuid(0x80000005, regs);
1013 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1014 print_AMD_assoc(regs[1] >> 24);
1015 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1016 print_AMD_assoc((regs[1] >> 8) & 0xff);
1017 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1018 printf(", %d bytes/line", regs[2] & 0xff);
1019 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1020 print_AMD_assoc((regs[2] >> 16) & 0xff);
1021 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1022 printf(", %d bytes/line", regs[3] & 0xff);
1023 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1024 print_AMD_assoc((regs[3] >> 16) & 0xff);
1025 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1026 do_cpuid(0x80000006, regs);
1027 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1028 printf(", %d bytes/line", regs[2] & 0xff);
1029 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1030 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1031 }
1032 }
1033 if (((cpu_id & 0xf00) == 0x500)
1034 && (((cpu_id & 0x0f0) > 0x80)
1035 || (((cpu_id & 0x0f0) == 0x80)
1036 && (cpu_id & 0x00f) > 0x07))) {
1037 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1038 amd_whcr = rdmsr(0xc0000082);
1039 if (!(amd_whcr & (0x3ff << 22))) {
1040 printf("Write Allocate Disable\n");
1041 } else {
1042 printf("Write Allocate Enable Limit: %dM bytes\n",
1043 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1044 printf("Write Allocate 15-16M bytes: %s\n",
1045 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1046 }
1047 } else if (((cpu_id & 0xf00) == 0x500)
1048 && ((cpu_id & 0x0f0) > 0x50)) {
1049 /* K6, K6-2(old core) */
1050 amd_whcr = rdmsr(0xc0000082);
1051 if (!(amd_whcr & (0x7f << 1))) {
1052 printf("Write Allocate Disable\n");
1053 } else {
1054 printf("Write Allocate Enable Limit: %dM bytes\n",
1055 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1056 printf("Write Allocate 15-16M bytes: %s\n",
1057 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1058 printf("Hardware Write Allocate Control: %s\n",
1059 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1060 }
1061 }
1062 }
1063
1064 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1065 static void
1066 print_AMD_features(void)
1067 {
1068 u_int regs[4];
1069
1070 /*
1071 * Values taken from AMD Processor Recognition
1072 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1073 */
1074 do_cpuid(0x80000001, regs);
1075 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1076 "\020" /* in hex */
1077 "\001FPU" /* Integral FPU */
1078 "\002VME" /* Extended VM86 mode support */
1079 "\003DE" /* Debug extensions */
1080 "\004PSE" /* 4MByte page tables */
1081 "\005TSC" /* Timestamp counter */
1082 "\006MSR" /* Machine specific registers */
1083 "\007PAE" /* Physical address extension */
1084 "\010MCE" /* Machine Check support */
1085 "\011CX8" /* CMPEXCH8 instruction */
1086 "\012APIC" /* SMP local APIC */
1087 "\013<b10>"
1088 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1089 "\015MTRR" /* Memory Type Range Registers */
1090 "\016PGE" /* PG_G (global bit) support */
1091 "\017MCA" /* Machine Check Architecture */
1092 "\020ICMOV" /* CMOV instruction */
1093 "\021PAT" /* Page attributes table */
1094 "\022PGE36" /* 36 bit address space support */
1095 "\023RSVD" /* Reserved, unknown */
1096 "\024MP" /* Multiprocessor Capable */
1097 "\025NX" /* Has EFER.NXE, NX (no execute pte bit) */
1098 "\026<b21>"
1099 "\027AMIE" /* AMD MMX Instruction Extensions */
1100 "\030MMX"
1101 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1102 "\032<b25>"
1103 "\033<b26>"
1104 "\034<b27>"
1105 "\035<b28>"
1106 "\036LM" /* Long mode */
1107 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1108 "\0403DNow!" /* AMD 3DNow! Instructions */
1109 );
1110 }
1111 #endif
1112
1113 /*
1114 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1115 */
1116
1117 #define MSR_TMx86_LONGRUN 0x80868010
1118 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1119
1120 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1121 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1122 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1123
1124 #define LONGRUN_MODE_MINFREQUENCY 0x00
1125 #define LONGRUN_MODE_ECONOMY 0x01
1126 #define LONGRUN_MODE_PERFORMANCE 0x02
1127 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1128 #define LONGRUN_MODE_UNKNOWN 0x04
1129 #define LONGRUN_MODE_MAX 0x04
1130
1131 union msrinfo {
1132 u_int64_t msr;
1133 u_int32_t regs[2];
1134 };
1135
1136 static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1137 /* MSR low, MSR high, flags bit0 */
1138 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1139 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1140 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1141 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1142 };
1143
1144 static u_int
1145 tmx86_get_longrun_mode(void)
1146 {
1147 u_long eflags;
1148 union msrinfo msrinfo;
1149 u_int low, high, flags, mode;
1150
1151 eflags = read_eflags();
1152 disable_intr();
1153
1154 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1155 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1156 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1157 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1158
1159 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1160 if (low == longrun_modes[mode][0] &&
1161 high == longrun_modes[mode][1] &&
1162 flags == longrun_modes[mode][2]) {
1163 goto out;
1164 }
1165 }
1166 mode = LONGRUN_MODE_UNKNOWN;
1167 out:
1168 write_eflags(eflags);
1169 return (mode);
1170 }
1171
1172 static u_int
1173 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1174 {
1175 u_long eflags;
1176 u_int regs[4];
1177
1178 eflags = read_eflags();
1179 disable_intr();
1180
1181 do_cpuid(0x80860007, regs);
1182 *frequency = regs[0];
1183 *voltage = regs[1];
1184 *percentage = regs[2];
1185
1186 write_eflags(eflags);
1187 return (1);
1188 }
1189
1190 static u_int
1191 tmx86_set_longrun_mode(u_int mode)
1192 {
1193 u_long eflags;
1194 union msrinfo msrinfo;
1195
1196 if (mode >= LONGRUN_MODE_UNKNOWN) {
1197 return (0);
1198 }
1199
1200 eflags = read_eflags();
1201 disable_intr();
1202
1203 /* Write LongRun mode values to Model Specific Register. */
1204 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1205 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1206 longrun_modes[mode][0]);
1207 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1208 longrun_modes[mode][1]);
1209 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1210
1211 /* Write LongRun mode flags to Model Specific Register. */
1212 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1213 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1214 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1215
1216 write_eflags(eflags);
1217 return (1);
1218 }
1219
1220 static u_int crusoe_longrun;
1221 static u_int crusoe_frequency;
1222 static u_int crusoe_voltage;
1223 static u_int crusoe_percentage;
1224 static u_int crusoe_performance_longrun = LONGRUN_MODE_PERFORMANCE;
1225 static u_int crusoe_economy_longrun = LONGRUN_MODE_ECONOMY;
1226 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1227 static struct sysctl_oid *crusoe_sysctl_tree;
1228
1229 static void
1230 tmx86_longrun_power_profile(void *arg)
1231 {
1232 int state;
1233 u_int new;
1234
1235 state = power_profile_get_state();
1236 if (state != POWER_PROFILE_PERFORMANCE &&
1237 state != POWER_PROFILE_ECONOMY) {
1238 return;
1239 }
1240
1241 switch (state) {
1242 case POWER_PROFILE_PERFORMANCE:
1243 new =crusoe_performance_longrun;
1244 break;
1245 case POWER_PROFILE_ECONOMY:
1246 new = crusoe_economy_longrun;
1247 break;
1248 default:
1249 new = tmx86_get_longrun_mode();
1250 break;
1251 }
1252
1253 if (tmx86_get_longrun_mode() != new) {
1254 tmx86_set_longrun_mode(new);
1255 }
1256 }
1257
1258 static int
1259 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1260 {
1261 u_int mode;
1262 int error;
1263
1264 crusoe_longrun = tmx86_get_longrun_mode();
1265 mode = crusoe_longrun;
1266 error = sysctl_handle_int(oidp, &mode, 0, req);
1267 if (error || !req->newptr) {
1268 return (error);
1269 }
1270 if (mode >= LONGRUN_MODE_UNKNOWN) {
1271 error = EINVAL;
1272 return (error);
1273 }
1274 if (crusoe_longrun != mode) {
1275 crusoe_longrun = mode;
1276 tmx86_set_longrun_mode(crusoe_longrun);
1277 }
1278
1279 return (error);
1280 }
1281
1282 static int
1283 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1284 {
1285 u_int val;
1286 int error;
1287
1288 tmx86_get_longrun_status(&crusoe_frequency,
1289 &crusoe_voltage, &crusoe_percentage);
1290 val = *(u_int *)oidp->oid_arg1;
1291 error = sysctl_handle_int(oidp, &val, 0, req);
1292 return (error);
1293 }
1294
1295 static int
1296 tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS)
1297 {
1298 u_int32_t *argp;
1299 u_int32_t arg;
1300 int error;
1301
1302 argp = (u_int32_t *)oidp->oid_arg1;
1303 arg = *argp;
1304 error = sysctl_handle_int(oidp, &arg, 0, req);
1305
1306 /* error or no new value */
1307 if ((error != 0) || (req->newptr == NULL))
1308 return (error);
1309
1310 /* range check */
1311 if (arg >= LONGRUN_MODE_UNKNOWN)
1312 return (EINVAL);
1313
1314 /* set new value and possibly switch */
1315 *argp = arg;
1316
1317 tmx86_longrun_power_profile(NULL);
1318
1319 return (0);
1320
1321 }
1322
1323 static void
1324 setup_tmx86_longrun(void)
1325 {
1326 static int done = 0;
1327
1328 if (done)
1329 return;
1330 done++;
1331
1332 sysctl_ctx_init(&crusoe_sysctl_ctx);
1333 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1334 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1335 "crusoe", CTLFLAG_RD, 0,
1336 "Transmeta Crusoe LongRun support");
1337 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1338 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1339 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1340 "LongRun mode [0-3]");
1341 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1342 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1343 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1344 "Current frequency (MHz)");
1345 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1346 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1347 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1348 "Current voltage (mV)");
1349 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1350 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1351 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1352 "Processing performance (%)");
1353 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1354 OID_AUTO, "performance_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
1355 &crusoe_performance_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
1356 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1357 OID_AUTO, "economy_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
1358 &crusoe_economy_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
1359
1360 /* register performance profile change handler */
1361 EVENTHANDLER_REGISTER(power_profile_change, tmx86_longrun_power_profile, NULL, 0);
1362
1363 }
1364
1365 static void
1366 print_transmeta_info()
1367 {
1368 u_int regs[4], nreg = 0;
1369
1370 do_cpuid(0x80860000, regs);
1371 nreg = regs[0];
1372 if (nreg >= 0x80860001) {
1373 do_cpuid(0x80860001, regs);
1374 printf(" Processor revision %u.%u.%u.%u\n",
1375 (regs[1] >> 24) & 0xff,
1376 (regs[1] >> 16) & 0xff,
1377 (regs[1] >> 8) & 0xff,
1378 regs[1] & 0xff);
1379 }
1380 if (nreg >= 0x80860002) {
1381 do_cpuid(0x80860002, regs);
1382 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1383 (regs[1] >> 24) & 0xff,
1384 (regs[1] >> 16) & 0xff,
1385 (regs[1] >> 8) & 0xff,
1386 regs[1] & 0xff,
1387 regs[2]);
1388 }
1389 if (nreg >= 0x80860006) {
1390 char info[65];
1391 do_cpuid(0x80860003, (u_int*) &info[0]);
1392 do_cpuid(0x80860004, (u_int*) &info[16]);
1393 do_cpuid(0x80860005, (u_int*) &info[32]);
1394 do_cpuid(0x80860006, (u_int*) &info[48]);
1395 info[64] = 0;
1396 printf(" %s\n", info);
1397 }
1398
1399 crusoe_longrun = tmx86_get_longrun_mode();
1400 tmx86_get_longrun_status(&crusoe_frequency,
1401 &crusoe_voltage, &crusoe_percentage);
1402 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1403 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1404 }
Cache object: f2f21c214187d029d3fae2ffd3090c2d
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