1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 */
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
45
46 #include "opt_cpu.h"
47
48 #include <sys/param.h>
49 #include <sys/bus.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
54
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
62
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
66
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
75 #endif
76 void panicifcpuunsupported(void);
77
78 static void identifycyrix(void);
79 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
80 static void print_AMD_features(void);
81 #endif
82 static void print_AMD_info(void);
83 static void print_AMD_assoc(int i);
84 static void print_transmeta_info(void);
85
86 int cpu_class;
87 u_int cpu_exthigh; /* Highest arg to extended CPUID */
88 u_int cyrix_did; /* Device ID of Cyrix CPU */
89 char machine[] = "i386";
90 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
91 machine, 0, "Machine class");
92
93 static char cpu_model[128];
94 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
95 cpu_model, 0, "Machine model");
96
97 static int hw_clockrate;
98 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
99 &hw_clockrate, 0, "CPU instruction clock rate");
100
101 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
102 static char cpu_brand[48];
103
104 #define MAX_BRAND_INDEX 8
105
106 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
107 NULL, /* No brand */
108 "Intel Celeron",
109 "Intel Pentium III",
110 "Intel Pentium III Xeon",
111 NULL,
112 NULL,
113 NULL,
114 NULL,
115 "Intel Pentium 4"
116 };
117 #endif
118
119 static struct {
120 char *cpu_name;
121 int cpu_class;
122 } i386_cpus[] = {
123 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
124 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
125 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
126 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
127 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
128 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
129 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
130 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
131 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
132 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
133 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
134 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
135 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
136 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
137 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
138 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
139 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
140 };
141
142 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
143 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
144 #endif
145
146 void
147 printcpuinfo(void)
148 {
149 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
150 u_int regs[4], i;
151 char *brand;
152 #endif
153
154 cpu_class = i386_cpus[cpu].cpu_class;
155 printf("CPU: ");
156 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
157
158 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
159 /* Check for extended CPUID information and a processor name. */
160 if (cpu_high > 0 &&
161 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
162 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
163 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
164 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
165 strcmp(cpu_vendor, "Geode by NSC") == 0)) {
166 do_cpuid(0x80000000, regs);
167 if (regs[0] >= 0x80000000) {
168 cpu_exthigh = regs[0];
169 if (cpu_exthigh >= 0x80000004) {
170 brand = cpu_brand;
171 for (i = 0x80000002; i < 0x80000005; i++) {
172 do_cpuid(i, regs);
173 memcpy(brand, regs, sizeof(regs));
174 brand += sizeof(regs);
175 }
176 }
177 }
178 }
179
180 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
181 if ((cpu_id & 0xf00) > 0x300) {
182 u_int brand_index;
183
184 cpu_model[0] = '\0';
185
186 switch (cpu_id & 0x3000) {
187 case 0x1000:
188 strcpy(cpu_model, "Overdrive ");
189 break;
190 case 0x2000:
191 strcpy(cpu_model, "Dual ");
192 break;
193 }
194
195 switch (cpu_id & 0xf00) {
196 case 0x400:
197 strcat(cpu_model, "i486 ");
198 /* Check the particular flavor of 486 */
199 switch (cpu_id & 0xf0) {
200 case 0x00:
201 case 0x10:
202 strcat(cpu_model, "DX");
203 break;
204 case 0x20:
205 strcat(cpu_model, "SX");
206 break;
207 case 0x30:
208 strcat(cpu_model, "DX2");
209 break;
210 case 0x40:
211 strcat(cpu_model, "SL");
212 break;
213 case 0x50:
214 strcat(cpu_model, "SX2");
215 break;
216 case 0x70:
217 strcat(cpu_model,
218 "DX2 Write-Back Enhanced");
219 break;
220 case 0x80:
221 strcat(cpu_model, "DX4");
222 break;
223 }
224 break;
225 case 0x500:
226 /* Check the particular flavor of 586 */
227 strcat(cpu_model, "Pentium");
228 switch (cpu_id & 0xf0) {
229 case 0x00:
230 strcat(cpu_model, " A-step");
231 break;
232 case 0x10:
233 strcat(cpu_model, "/P5");
234 break;
235 case 0x20:
236 strcat(cpu_model, "/P54C");
237 break;
238 case 0x30:
239 strcat(cpu_model, "/P54T Overdrive");
240 break;
241 case 0x40:
242 strcat(cpu_model, "/P55C");
243 break;
244 case 0x70:
245 strcat(cpu_model, "/P54C");
246 break;
247 case 0x80:
248 strcat(cpu_model, "/P55C (quarter-micron)");
249 break;
250 default:
251 /* nothing */
252 break;
253 }
254 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
255 /*
256 * XXX - If/when Intel fixes the bug, this
257 * should also check the version of the
258 * CPU, not just that it's a Pentium.
259 */
260 has_f00f_bug = 1;
261 #endif
262 break;
263 case 0x600:
264 /* Check the particular flavor of 686 */
265 switch (cpu_id & 0xf0) {
266 case 0x00:
267 strcat(cpu_model, "Pentium Pro A-step");
268 break;
269 case 0x10:
270 strcat(cpu_model, "Pentium Pro");
271 break;
272 case 0x30:
273 case 0x50:
274 case 0x60:
275 strcat(cpu_model,
276 "Pentium II/Pentium II Xeon/Celeron");
277 cpu = CPU_PII;
278 break;
279 case 0x70:
280 case 0x80:
281 case 0xa0:
282 case 0xb0:
283 strcat(cpu_model,
284 "Pentium III/Pentium III Xeon/Celeron");
285 cpu = CPU_PIII;
286 break;
287 default:
288 strcat(cpu_model, "Unknown 80686");
289 break;
290 }
291 break;
292 case 0xf00:
293 strcat(cpu_model, "Pentium 4");
294 cpu = CPU_P4;
295 break;
296 default:
297 strcat(cpu_model, "unknown");
298 break;
299 }
300
301 /*
302 * If we didn't get a brand name from the extended
303 * CPUID, try to look it up in the brand table.
304 */
305 if (cpu_high > 0 && *cpu_brand == '\0') {
306 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
307 if (brand_index <= MAX_BRAND_INDEX &&
308 cpu_brandtable[brand_index] != NULL)
309 strcpy(cpu_brand,
310 cpu_brandtable[brand_index]);
311 }
312 }
313 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
314 /*
315 * Values taken from AMD Processor Recognition
316 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
317 * (also describes ``Features'' encodings.
318 */
319 strcpy(cpu_model, "AMD ");
320 switch (cpu_id & 0xFF0) {
321 case 0x410:
322 strcat(cpu_model, "Standard Am486DX");
323 break;
324 case 0x430:
325 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
326 break;
327 case 0x470:
328 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
329 break;
330 case 0x480:
331 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
332 break;
333 case 0x490:
334 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
335 break;
336 case 0x4E0:
337 strcat(cpu_model, "Am5x86 Write-Through");
338 break;
339 case 0x4F0:
340 strcat(cpu_model, "Am5x86 Write-Back");
341 break;
342 case 0x500:
343 strcat(cpu_model, "K5 model 0");
344 tsc_is_broken = 1;
345 break;
346 case 0x510:
347 strcat(cpu_model, "K5 model 1");
348 break;
349 case 0x520:
350 strcat(cpu_model, "K5 PR166 (model 2)");
351 break;
352 case 0x530:
353 strcat(cpu_model, "K5 PR200 (model 3)");
354 break;
355 case 0x560:
356 strcat(cpu_model, "K6");
357 break;
358 case 0x570:
359 strcat(cpu_model, "K6 266 (model 1)");
360 break;
361 case 0x580:
362 strcat(cpu_model, "K6-2");
363 break;
364 case 0x590:
365 strcat(cpu_model, "K6-III");
366 break;
367 default:
368 strcat(cpu_model, "Unknown");
369 break;
370 }
371 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
372 if ((cpu_id & 0xf00) == 0x500) {
373 if (((cpu_id & 0x0f0) > 0)
374 && ((cpu_id & 0x0f0) < 0x60)
375 && ((cpu_id & 0x00f) > 3))
376 enable_K5_wt_alloc();
377 else if (((cpu_id & 0x0f0) > 0x80)
378 || (((cpu_id & 0x0f0) == 0x80)
379 && (cpu_id & 0x00f) > 0x07))
380 enable_K6_2_wt_alloc();
381 else if ((cpu_id & 0x0f0) > 0x50)
382 enable_K6_wt_alloc();
383 }
384 #endif
385 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
386 strcpy(cpu_model, "Cyrix ");
387 switch (cpu_id & 0xff0) {
388 case 0x440:
389 strcat(cpu_model, "MediaGX");
390 break;
391 case 0x520:
392 strcat(cpu_model, "6x86");
393 break;
394 case 0x540:
395 cpu_class = CPUCLASS_586;
396 strcat(cpu_model, "GXm");
397 break;
398 case 0x600:
399 strcat(cpu_model, "6x86MX");
400 break;
401 default:
402 /*
403 * Even though CPU supports the cpuid
404 * instruction, it can be disabled.
405 * Therefore, this routine supports all Cyrix
406 * CPUs.
407 */
408 switch (cyrix_did & 0xf0) {
409 case 0x00:
410 switch (cyrix_did & 0x0f) {
411 case 0x00:
412 strcat(cpu_model, "486SLC");
413 break;
414 case 0x01:
415 strcat(cpu_model, "486DLC");
416 break;
417 case 0x02:
418 strcat(cpu_model, "486SLC2");
419 break;
420 case 0x03:
421 strcat(cpu_model, "486DLC2");
422 break;
423 case 0x04:
424 strcat(cpu_model, "486SRx");
425 break;
426 case 0x05:
427 strcat(cpu_model, "486DRx");
428 break;
429 case 0x06:
430 strcat(cpu_model, "486SRx2");
431 break;
432 case 0x07:
433 strcat(cpu_model, "486DRx2");
434 break;
435 case 0x08:
436 strcat(cpu_model, "486SRu");
437 break;
438 case 0x09:
439 strcat(cpu_model, "486DRu");
440 break;
441 case 0x0a:
442 strcat(cpu_model, "486SRu2");
443 break;
444 case 0x0b:
445 strcat(cpu_model, "486DRu2");
446 break;
447 default:
448 strcat(cpu_model, "Unknown");
449 break;
450 }
451 break;
452 case 0x10:
453 switch (cyrix_did & 0x0f) {
454 case 0x00:
455 strcat(cpu_model, "486S");
456 break;
457 case 0x01:
458 strcat(cpu_model, "486S2");
459 break;
460 case 0x02:
461 strcat(cpu_model, "486Se");
462 break;
463 case 0x03:
464 strcat(cpu_model, "486S2e");
465 break;
466 case 0x0a:
467 strcat(cpu_model, "486DX");
468 break;
469 case 0x0b:
470 strcat(cpu_model, "486DX2");
471 break;
472 case 0x0f:
473 strcat(cpu_model, "486DX4");
474 break;
475 default:
476 strcat(cpu_model, "Unknown");
477 break;
478 }
479 break;
480 case 0x20:
481 if ((cyrix_did & 0x0f) < 8)
482 strcat(cpu_model, "6x86"); /* Where did you get it? */
483 else
484 strcat(cpu_model, "5x86");
485 break;
486 case 0x30:
487 strcat(cpu_model, "6x86");
488 break;
489 case 0x40:
490 if ((cyrix_did & 0xf000) == 0x3000) {
491 cpu_class = CPUCLASS_586;
492 strcat(cpu_model, "GXm");
493 } else
494 strcat(cpu_model, "MediaGX");
495 break;
496 case 0x50:
497 strcat(cpu_model, "6x86MX");
498 break;
499 case 0xf0:
500 switch (cyrix_did & 0x0f) {
501 case 0x0d:
502 strcat(cpu_model, "Overdrive CPU");
503 break;
504 case 0x0e:
505 strcpy(cpu_model, "Texas Instruments 486SXL");
506 break;
507 case 0x0f:
508 strcat(cpu_model, "486SLC/DLC");
509 break;
510 default:
511 strcat(cpu_model, "Unknown");
512 break;
513 }
514 break;
515 default:
516 strcat(cpu_model, "Unknown");
517 break;
518 }
519 break;
520 }
521 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
522 strcpy(cpu_model, "Rise ");
523 switch (cpu_id & 0xff0) {
524 case 0x500:
525 strcat(cpu_model, "mP6");
526 break;
527 default:
528 strcat(cpu_model, "Unknown");
529 }
530 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
531 switch (cpu_id & 0xff0) {
532 case 0x540:
533 strcpy(cpu_model, "IDT WinChip C6");
534 tsc_is_broken = 1;
535 break;
536 case 0x580:
537 strcpy(cpu_model, "IDT WinChip 2");
538 break;
539 case 0x660:
540 strcpy(cpu_model, "VIA C3 Samuel");
541 break;
542 case 0x670:
543 if (cpu_id & 0x8)
544 strcpy(cpu_model, "VIA C3 Ezra");
545 else
546 strcpy(cpu_model, "VIA C3 Samuel 2");
547 break;
548 case 0x680:
549 strcpy(cpu_model, "VIA C3 Ezra-T");
550 break;
551 case 0x690:
552 strcpy(cpu_model, "VIA C3 Nehemiah");
553 do_cpuid(0xc0000000, regs);
554 if (regs[0] == 0xc0000001) {
555 do_cpuid(0xc0000001, regs);
556 if ((cpu_id & 0xf) >= 3)
557 if ((regs[3] & 0x0c) == 0x0c)
558 strcat(cpu_model, "+RNG");
559 if ((cpu_id & 0xf) >= 8)
560 if ((regs[3] & 0xc0) == 0xc0)
561 strcat(cpu_model, "+ACE");
562 }
563 break;
564 default:
565 strcpy(cpu_model, "VIA/IDT Unknown");
566 }
567 } else if (strcmp(cpu_vendor, "IBM") == 0) {
568 strcpy(cpu_model, "Blue Lightning CPU");
569 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
570 switch (cpu_id & 0xfff) {
571 case 0x540:
572 strcpy(cpu_model, "Geode SC1100");
573 cpu = CPU_GEODE1100;
574 tsc_is_broken = 1;
575 break;
576 default:
577 strcpy(cpu_model, "Geode/NSC unknown");
578 break;
579 }
580 }
581
582 /*
583 * Replace cpu_model with cpu_brand minus leading spaces if
584 * we have one.
585 */
586 brand = cpu_brand;
587 while (*brand == ' ')
588 ++brand;
589 if (*brand != '\0')
590 strcpy(cpu_model, brand);
591
592 #endif
593
594 printf("%s (", cpu_model);
595 switch(cpu_class) {
596 case CPUCLASS_286:
597 printf("286");
598 break;
599 #if defined(I386_CPU)
600 case CPUCLASS_386:
601 printf("386");
602 break;
603 #endif
604 #if defined(I486_CPU)
605 case CPUCLASS_486:
606 printf("486");
607 bzero_vector = i486_bzero;
608 break;
609 #endif
610 #if defined(I586_CPU)
611 case CPUCLASS_586:
612 hw_clockrate = (tsc_freq + 5000) / 1000000;
613 printf("%jd.%02d-MHz ",
614 (intmax_t)(tsc_freq + 4999) / 1000000,
615 (u_int)((tsc_freq + 4999) / 10000) % 100);
616 printf("586");
617 break;
618 #endif
619 #if defined(I686_CPU)
620 case CPUCLASS_686:
621 hw_clockrate = (tsc_freq + 5000) / 1000000;
622 printf("%jd.%02d-MHz ",
623 (intmax_t)(tsc_freq + 4999) / 1000000,
624 (u_int)((tsc_freq + 4999) / 10000) % 100);
625 printf("686");
626 break;
627 #endif
628 default:
629 printf("Unknown"); /* will panic below... */
630 }
631 printf("-class CPU)\n");
632 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
633 if(*cpu_vendor)
634 printf(" Origin = \"%s\"",cpu_vendor);
635 if(cpu_id)
636 printf(" Id = 0x%x", cpu_id);
637
638 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
639 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
640 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
641 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
642 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
643 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
644 strcmp(cpu_vendor, "Geode by NSC") == 0 ||
645 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
646 ((cpu_id & 0xf00) > 0x500))) {
647 printf(" Stepping = %u", cpu_id & 0xf);
648 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
649 printf(" DIR=0x%04x", cyrix_did);
650 if (cpu_high > 0) {
651 /*
652 * Here we should probably set up flags indicating
653 * whether or not various features are available.
654 * The interesting ones are probably VME, PSE, PAE,
655 * and PGE. The code already assumes without bothering
656 * to check that all CPUs >= Pentium have a TSC and
657 * MSRs.
658 */
659 printf("\n Features=0x%b", cpu_feature,
660 "\020"
661 "\001FPU" /* Integral FPU */
662 "\002VME" /* Extended VM86 mode support */
663 "\003DE" /* Debugging Extensions (CR4.DE) */
664 "\004PSE" /* 4MByte page tables */
665 "\005TSC" /* Timestamp counter */
666 "\006MSR" /* Machine specific registers */
667 "\007PAE" /* Physical address extension */
668 "\010MCE" /* Machine Check support */
669 "\011CX8" /* CMPEXCH8 instruction */
670 "\012APIC" /* SMP local APIC */
671 "\013oldMTRR" /* Previous implementation of MTRR */
672 "\014SEP" /* Fast System Call */
673 "\015MTRR" /* Memory Type Range Registers */
674 "\016PGE" /* PG_G (global bit) support */
675 "\017MCA" /* Machine Check Architecture */
676 "\020CMOV" /* CMOV instruction */
677 "\021PAT" /* Page attributes table */
678 "\022PSE36" /* 36 bit address space support */
679 "\023PN" /* Processor Serial number */
680 "\024CLFLUSH" /* Has the CLFLUSH instruction */
681 "\025<b20>"
682 "\026DTS" /* Debug Trace Store */
683 "\027ACPI" /* ACPI support */
684 "\030MMX" /* MMX instructions */
685 "\031FXSR" /* FXSAVE/FXRSTOR */
686 "\032SSE" /* Streaming SIMD Extensions */
687 "\033SSE2" /* Streaming SIMD Extensions #2 */
688 "\034SS" /* Self snoop */
689 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
690 "\036TM" /* Thermal Monitor clock slowdown */
691 "\037IA64" /* CPU can execute IA64 instructions */
692 "\040PBE" /* Pending Break Enable */
693 );
694
695 /*
696 * If this CPU supports hyperthreading then mention
697 * the number of logical CPU's it contains.
698 */
699 if (cpu_feature & CPUID_HTT &&
700 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
701 printf("\n Hyperthreading: %d logical CPUs",
702 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
703 }
704 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
705 cpu_exthigh >= 0x80000001)
706 print_AMD_features();
707 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
708 printf(" DIR=0x%04x", cyrix_did);
709 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
710 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
711 #ifndef CYRIX_CACHE_REALLY_WORKS
712 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
713 printf("\n CPU cache: write-through mode");
714 #endif
715 }
716 /* Avoid ugly blank lines: only print newline when we have to. */
717 if (*cpu_vendor || cpu_id)
718 printf("\n");
719
720 #endif
721
722 if (!bootverbose)
723 return;
724
725 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
726 print_AMD_info();
727 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
728 strcmp(cpu_vendor, "TransmetaCPU") == 0)
729 print_transmeta_info();
730
731 #ifdef I686_CPU
732 /*
733 * XXX - Do PPro CPUID level=2 stuff here?
734 *
735 * No, but maybe in a print_Intel_info() function called from here.
736 */
737 #endif
738 }
739
740 void
741 panicifcpuunsupported(void)
742 {
743
744 #if !defined(lint)
745 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
746 #error This kernel is not configured for one of the supported CPUs
747 #endif
748 #else /* lint */
749 #endif /* lint */
750 #if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
751 #error I386_CPU is mutually exclusive with the other cpu types.
752 #endif
753 /*
754 * Now that we have told the user what they have,
755 * let them know if that machine type isn't configured.
756 */
757 switch (cpu_class) {
758 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
759 #if !defined(I386_CPU)
760 case CPUCLASS_386:
761 #endif
762 #if !defined(I486_CPU)
763 case CPUCLASS_486:
764 #endif
765 #if !defined(I586_CPU)
766 case CPUCLASS_586:
767 #endif
768 #if !defined(I686_CPU)
769 case CPUCLASS_686:
770 #endif
771 panic("CPU class not configured");
772 default:
773 break;
774 }
775 }
776
777
778 static volatile u_int trap_by_rdmsr;
779
780 /*
781 * Special exception 6 handler.
782 * The rdmsr instruction generates invalid opcodes fault on 486-class
783 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
784 * function identblue() when this handler is called. Stacked eip should
785 * be advanced.
786 */
787 inthand_t bluetrap6;
788 #if defined(__GNUC__) || defined(__INTEL_COMPILER)
789 __asm
790 (" \n\
791 .text \n\
792 .p2align 2,0x90 \n\
793 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
794 " __XSTRING(CNAME(bluetrap6)) ": \n\
795 ss \n\
796 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
797 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
798 iret \n\
799 ");
800 #endif
801
802 /*
803 * Special exception 13 handler.
804 * Accessing non-existent MSR generates general protection fault.
805 */
806 inthand_t bluetrap13;
807 #if defined(__GNUC__) || defined(__INTEL_COMPILER)
808 __asm
809 (" \n\
810 .text \n\
811 .p2align 2,0x90 \n\
812 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
813 " __XSTRING(CNAME(bluetrap13)) ": \n\
814 ss \n\
815 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
816 popl %eax /* discard error code */ \n\
817 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
818 iret \n\
819 ");
820 #endif
821
822 /*
823 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
824 * support cpuid instruction. This function should be called after
825 * loading interrupt descriptor table register.
826 *
827 * I don't like this method that handles fault, but I couldn't get
828 * information for any other methods. Does blue giant know?
829 */
830 static int
831 identblue(void)
832 {
833
834 trap_by_rdmsr = 0;
835
836 /*
837 * Cyrix 486-class CPU does not support rdmsr instruction.
838 * The rdmsr instruction generates invalid opcode fault, and exception
839 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
840 * bluetrap6() set the magic number to trap_by_rdmsr.
841 */
842 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
843 GSEL(GCODE_SEL, SEL_KPL));
844
845 /*
846 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
847 * In this case, rdmsr generates general protection fault, and
848 * exception will be trapped by bluetrap13().
849 */
850 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
851 GSEL(GCODE_SEL, SEL_KPL));
852
853 rdmsr(0x1002); /* Cyrix CPU generates fault. */
854
855 if (trap_by_rdmsr == 0xa8c1d)
856 return IDENTBLUE_CYRIX486;
857 else if (trap_by_rdmsr == 0xa89c4)
858 return IDENTBLUE_CYRIXM2;
859 return IDENTBLUE_IBMCPU;
860 }
861
862
863 /*
864 * identifycyrix() set lower 16 bits of cyrix_did as follows:
865 *
866 * F E D C B A 9 8 7 6 5 4 3 2 1 0
867 * +-------+-------+---------------+
868 * | SID | RID | Device ID |
869 * | (DIR 1) | (DIR 0) |
870 * +-------+-------+---------------+
871 */
872 static void
873 identifycyrix(void)
874 {
875 u_int eflags;
876 int ccr2_test = 0, dir_test = 0;
877 u_char ccr2, ccr3;
878
879 eflags = read_eflags();
880 disable_intr();
881
882 ccr2 = read_cyrix_reg(CCR2);
883 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
884 read_cyrix_reg(CCR2);
885 if (read_cyrix_reg(CCR2) != ccr2)
886 ccr2_test = 1;
887 write_cyrix_reg(CCR2, ccr2);
888
889 ccr3 = read_cyrix_reg(CCR3);
890 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
891 read_cyrix_reg(CCR3);
892 if (read_cyrix_reg(CCR3) != ccr3)
893 dir_test = 1; /* CPU supports DIRs. */
894 write_cyrix_reg(CCR3, ccr3);
895
896 if (dir_test) {
897 /* Device ID registers are available. */
898 cyrix_did = read_cyrix_reg(DIR1) << 8;
899 cyrix_did += read_cyrix_reg(DIR0);
900 } else if (ccr2_test)
901 cyrix_did = 0x0010; /* 486S A-step */
902 else
903 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
904
905 write_eflags(eflags);
906 }
907
908 /*
909 * Final stage of CPU identification. -- Should I check TI?
910 */
911 void
912 finishidentcpu(void)
913 {
914 int isblue = 0;
915 u_char ccr3;
916 u_int regs[4];
917
918 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
919 if (cpu == CPU_486) {
920 /*
921 * These conditions are equivalent to:
922 * - CPU does not support cpuid instruction.
923 * - Cyrix/IBM CPU is detected.
924 */
925 isblue = identblue();
926 if (isblue == IDENTBLUE_IBMCPU) {
927 strcpy(cpu_vendor, "IBM");
928 cpu = CPU_BLUE;
929 return;
930 }
931 }
932 switch (cpu_id & 0xf00) {
933 case 0x600:
934 /*
935 * Cyrix's datasheet does not describe DIRs.
936 * Therefor, I assume it does not have them
937 * and use the result of the cpuid instruction.
938 * XXX they seem to have it for now at least. -Peter
939 */
940 identifycyrix();
941 cpu = CPU_M2;
942 break;
943 default:
944 identifycyrix();
945 /*
946 * This routine contains a trick.
947 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
948 */
949 switch (cyrix_did & 0x00f0) {
950 case 0x00:
951 case 0xf0:
952 cpu = CPU_486DLC;
953 break;
954 case 0x10:
955 cpu = CPU_CY486DX;
956 break;
957 case 0x20:
958 if ((cyrix_did & 0x000f) < 8)
959 cpu = CPU_M1;
960 else
961 cpu = CPU_M1SC;
962 break;
963 case 0x30:
964 cpu = CPU_M1;
965 break;
966 case 0x40:
967 /* MediaGX CPU */
968 cpu = CPU_M1SC;
969 break;
970 default:
971 /* M2 and later CPUs are treated as M2. */
972 cpu = CPU_M2;
973
974 /*
975 * enable cpuid instruction.
976 */
977 ccr3 = read_cyrix_reg(CCR3);
978 write_cyrix_reg(CCR3, CCR3_MAPEN0);
979 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
980 write_cyrix_reg(CCR3, ccr3);
981
982 do_cpuid(0, regs);
983 cpu_high = regs[0]; /* eax */
984 do_cpuid(1, regs);
985 cpu_id = regs[0]; /* eax */
986 cpu_feature = regs[3]; /* edx */
987 break;
988 }
989 }
990 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
991 /*
992 * There are BlueLightning CPUs that do not change
993 * undefined flags by dividing 5 by 2. In this case,
994 * the CPU identification routine in locore.s leaves
995 * cpu_vendor null string and puts CPU_486 into the
996 * cpu.
997 */
998 isblue = identblue();
999 if (isblue == IDENTBLUE_IBMCPU) {
1000 strcpy(cpu_vendor, "IBM");
1001 cpu = CPU_BLUE;
1002 return;
1003 }
1004 }
1005 }
1006
1007 static void
1008 print_AMD_assoc(int i)
1009 {
1010 if (i == 255)
1011 printf(", fully associative\n");
1012 else
1013 printf(", %d-way associative\n", i);
1014 }
1015
1016 static void
1017 print_AMD_info(void)
1018 {
1019 quad_t amd_whcr;
1020
1021 if (cpu_exthigh >= 0x80000005) {
1022 u_int regs[4];
1023
1024 do_cpuid(0x80000005, regs);
1025 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1026 print_AMD_assoc(regs[1] >> 24);
1027 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1028 print_AMD_assoc((regs[1] >> 8) & 0xff);
1029 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1030 printf(", %d bytes/line", regs[2] & 0xff);
1031 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1032 print_AMD_assoc((regs[2] >> 16) & 0xff);
1033 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1034 printf(", %d bytes/line", regs[3] & 0xff);
1035 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1036 print_AMD_assoc((regs[3] >> 16) & 0xff);
1037 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1038 do_cpuid(0x80000006, regs);
1039 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1040 printf(", %d bytes/line", regs[2] & 0xff);
1041 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1042 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1043 }
1044 }
1045 if (((cpu_id & 0xf00) == 0x500)
1046 && (((cpu_id & 0x0f0) > 0x80)
1047 || (((cpu_id & 0x0f0) == 0x80)
1048 && (cpu_id & 0x00f) > 0x07))) {
1049 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1050 amd_whcr = rdmsr(0xc0000082);
1051 if (!(amd_whcr & (0x3ff << 22))) {
1052 printf("Write Allocate Disable\n");
1053 } else {
1054 printf("Write Allocate Enable Limit: %dM bytes\n",
1055 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1056 printf("Write Allocate 15-16M bytes: %s\n",
1057 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1058 }
1059 } else if (((cpu_id & 0xf00) == 0x500)
1060 && ((cpu_id & 0x0f0) > 0x50)) {
1061 /* K6, K6-2(old core) */
1062 amd_whcr = rdmsr(0xc0000082);
1063 if (!(amd_whcr & (0x7f << 1))) {
1064 printf("Write Allocate Disable\n");
1065 } else {
1066 printf("Write Allocate Enable Limit: %dM bytes\n",
1067 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1068 printf("Write Allocate 15-16M bytes: %s\n",
1069 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1070 printf("Hardware Write Allocate Control: %s\n",
1071 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1072 }
1073 }
1074 }
1075
1076 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1077 static void
1078 print_AMD_features(void)
1079 {
1080 u_int regs[4];
1081
1082 /*
1083 * Values taken from AMD Processor Recognition
1084 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1085 */
1086 do_cpuid(0x80000001, regs);
1087 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1088 "\020" /* in hex */
1089 "\001FPU" /* Integral FPU */
1090 "\002VME" /* Extended VM86 mode support */
1091 "\003DE" /* Debug extensions */
1092 "\004PSE" /* 4MByte page tables */
1093 "\005TSC" /* Timestamp counter */
1094 "\006MSR" /* Machine specific registers */
1095 "\007PAE" /* Physical address extension */
1096 "\010MCE" /* Machine Check support */
1097 "\011CX8" /* CMPEXCH8 instruction */
1098 "\012APIC" /* SMP local APIC */
1099 "\013<b10>"
1100 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1101 "\015MTRR" /* Memory Type Range Registers */
1102 "\016PGE" /* PG_G (global bit) support */
1103 "\017MCA" /* Machine Check Architecture */
1104 "\020ICMOV" /* CMOV instruction */
1105 "\021PAT" /* Page attributes table */
1106 "\022PGE36" /* 36 bit address space support */
1107 "\023RSVD" /* Reserved, unknown */
1108 "\024MP" /* Multiprocessor Capable */
1109 "\025NX" /* Has EFER.NXE, NX (no execute pte bit) */
1110 "\026<b21>"
1111 "\027AMIE" /* AMD MMX Instruction Extensions */
1112 "\030MMX"
1113 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1114 "\032<b25>"
1115 "\033<b26>"
1116 "\034<b27>"
1117 "\035<b28>"
1118 "\036LM" /* Long mode */
1119 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1120 "\0403DNow!" /* AMD 3DNow! Instructions */
1121 );
1122 }
1123 #endif
1124
1125 static void
1126 print_transmeta_info()
1127 {
1128 u_int regs[4], nreg = 0;
1129
1130 do_cpuid(0x80860000, regs);
1131 nreg = regs[0];
1132 if (nreg >= 0x80860001) {
1133 do_cpuid(0x80860001, regs);
1134 printf(" Processor revision %u.%u.%u.%u\n",
1135 (regs[1] >> 24) & 0xff,
1136 (regs[1] >> 16) & 0xff,
1137 (regs[1] >> 8) & 0xff,
1138 regs[1] & 0xff);
1139 }
1140 if (nreg >= 0x80860002) {
1141 do_cpuid(0x80860002, regs);
1142 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1143 (regs[1] >> 24) & 0xff,
1144 (regs[1] >> 16) & 0xff,
1145 (regs[1] >> 8) & 0xff,
1146 regs[1] & 0xff,
1147 regs[2]);
1148 }
1149 if (nreg >= 0x80860006) {
1150 char info[65];
1151 do_cpuid(0x80860003, (u_int*) &info[0]);
1152 do_cpuid(0x80860004, (u_int*) &info[16]);
1153 do_cpuid(0x80860005, (u_int*) &info[32]);
1154 do_cpuid(0x80860006, (u_int*) &info[48]);
1155 info[64] = 0;
1156 printf(" %s\n", info);
1157 }
1158 }
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