The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/identcpu.c

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    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/6.0/sys/i386/i386/identcpu.c 147691 2005-06-30 06:44:34Z peter $");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/systm.h>
   49 #include <sys/kernel.h>
   50 #include <sys/sysctl.h>
   51 #include <sys/power.h>
   52 
   53 #include <machine/asmacros.h>
   54 #include <machine/clock.h>
   55 #include <machine/cputypes.h>
   56 #include <machine/intr_machdep.h>
   57 #include <machine/md_var.h>
   58 #include <machine/segments.h>
   59 #include <machine/specialreg.h>
   60 
   61 #define IDENTBLUE_CYRIX486      0
   62 #define IDENTBLUE_IBMCPU        1
   63 #define IDENTBLUE_CYRIXM2       2
   64 
   65 /* XXX - should be in header file: */
   66 void printcpuinfo(void);
   67 void finishidentcpu(void);
   68 void earlysetcpuclass(void);
   69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   70 void    enable_K5_wt_alloc(void);
   71 void    enable_K6_wt_alloc(void);
   72 void    enable_K6_2_wt_alloc(void);
   73 #endif
   74 void panicifcpuunsupported(void);
   75 
   76 static void identifycyrix(void);
   77 static void print_AMD_info(void);
   78 static void print_AMD_assoc(int i);
   79 static void print_transmeta_info(void);
   80 
   81 int     cpu_class;
   82 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   83 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
   84 char machine[] = "i386";
   85 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   86     machine, 0, "Machine class");
   87 
   88 static char cpu_model[128];
   89 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   90     cpu_model, 0, "Machine model");
   91 
   92 static int hw_clockrate;
   93 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
   94     &hw_clockrate, 0, "CPU instruction clock rate");
   95 
   96 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
   97 static char cpu_brand[48];
   98 
   99 #define MAX_BRAND_INDEX 8
  100 
  101 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
  102         NULL,                   /* No brand */
  103         "Intel Celeron",
  104         "Intel Pentium III",
  105         "Intel Pentium III Xeon",
  106         NULL,
  107         NULL,
  108         NULL,
  109         NULL,
  110         "Intel Pentium 4"
  111 };
  112 #endif
  113 
  114 static struct {
  115         char    *cpu_name;
  116         int     cpu_class;
  117 } i386_cpus[] = {
  118         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
  119         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
  120         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
  121         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
  122         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
  123         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
  124         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
  125         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
  126         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
  127         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
  128         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
  129         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
  130         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
  131         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
  132         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
  133         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
  134         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
  135 };
  136 
  137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  138 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
  139 #endif
  140 
  141 void
  142 printcpuinfo(void)
  143 {
  144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  145         u_int regs[4], i;
  146         char *brand;
  147 #endif
  148 
  149         cpu_class = i386_cpus[cpu].cpu_class;
  150         printf("CPU: ");
  151         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
  152 
  153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  154         /* Check for extended CPUID information and a processor name. */
  155         if (cpu_high > 0 &&
  156             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  157             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  158             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  159             strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  160             strcmp(cpu_vendor, "Geode by NSC") == 0)) {
  161                 do_cpuid(0x80000000, regs);
  162                 if (regs[0] >= 0x80000000) {
  163                         cpu_exthigh = regs[0];
  164                         if (cpu_exthigh >= 0x80000004) {
  165                                 brand = cpu_brand;
  166                                 for (i = 0x80000002; i < 0x80000005; i++) {
  167                                         do_cpuid(i, regs);
  168                                         memcpy(brand, regs, sizeof(regs));
  169                                         brand += sizeof(regs);
  170                                 }
  171                         }
  172                 }
  173         }
  174 
  175         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
  176         if (cpu_exthigh >= 0x80000001 &&
  177             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  178              strcmp(cpu_vendor, "AuthenticAMD") == 0)) {
  179                 do_cpuid(0x80000001, regs);
  180                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
  181         }
  182 
  183         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  184                 if ((cpu_id & 0xf00) > 0x300) {
  185                         u_int brand_index;
  186 
  187                         cpu_model[0] = '\0';
  188 
  189                         switch (cpu_id & 0x3000) {
  190                         case 0x1000:
  191                                 strcpy(cpu_model, "Overdrive ");
  192                                 break;
  193                         case 0x2000:
  194                                 strcpy(cpu_model, "Dual ");
  195                                 break;
  196                         }
  197 
  198                         switch (cpu_id & 0xf00) {
  199                         case 0x400:
  200                                 strcat(cpu_model, "i486 ");
  201                                 /* Check the particular flavor of 486 */
  202                                 switch (cpu_id & 0xf0) {
  203                                 case 0x00:
  204                                 case 0x10:
  205                                         strcat(cpu_model, "DX");
  206                                         break;
  207                                 case 0x20:
  208                                         strcat(cpu_model, "SX");
  209                                         break;
  210                                 case 0x30:
  211                                         strcat(cpu_model, "DX2");
  212                                         break;
  213                                 case 0x40:
  214                                         strcat(cpu_model, "SL");
  215                                         break;
  216                                 case 0x50:
  217                                         strcat(cpu_model, "SX2");
  218                                         break;
  219                                 case 0x70:
  220                                         strcat(cpu_model,
  221                                             "DX2 Write-Back Enhanced");
  222                                         break;
  223                                 case 0x80:
  224                                         strcat(cpu_model, "DX4");
  225                                         break;
  226                                 }
  227                                 break;
  228                         case 0x500:
  229                                 /* Check the particular flavor of 586 */
  230                                 strcat(cpu_model, "Pentium");
  231                                 switch (cpu_id & 0xf0) {
  232                                 case 0x00:
  233                                         strcat(cpu_model, " A-step");
  234                                         break;
  235                                 case 0x10:
  236                                         strcat(cpu_model, "/P5");
  237                                         break;
  238                                 case 0x20:
  239                                         strcat(cpu_model, "/P54C");
  240                                         break;
  241                                 case 0x30:
  242                                         strcat(cpu_model, "/P54T Overdrive");
  243                                         break;
  244                                 case 0x40:
  245                                         strcat(cpu_model, "/P55C");
  246                                         break;
  247                                 case 0x70:
  248                                         strcat(cpu_model, "/P54C");
  249                                         break;
  250                                 case 0x80:
  251                                         strcat(cpu_model, "/P55C (quarter-micron)");
  252                                         break;
  253                                 default:
  254                                         /* nothing */
  255                                         break;
  256                                 }
  257 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  258                                 /*
  259                                  * XXX - If/when Intel fixes the bug, this
  260                                  * should also check the version of the
  261                                  * CPU, not just that it's a Pentium.
  262                                  */
  263                                 has_f00f_bug = 1;
  264 #endif
  265                                 break;
  266                         case 0x600:
  267                                 /* Check the particular flavor of 686 */
  268                                 switch (cpu_id & 0xf0) {
  269                                 case 0x00:
  270                                         strcat(cpu_model, "Pentium Pro A-step");
  271                                         break;
  272                                 case 0x10:
  273                                         strcat(cpu_model, "Pentium Pro");
  274                                         break;
  275                                 case 0x30:
  276                                 case 0x50:
  277                                 case 0x60:
  278                                         strcat(cpu_model,
  279                                 "Pentium II/Pentium II Xeon/Celeron");
  280                                         cpu = CPU_PII;
  281                                         break;
  282                                 case 0x70:
  283                                 case 0x80:
  284                                 case 0xa0:
  285                                 case 0xb0:
  286                                         strcat(cpu_model,
  287                                         "Pentium III/Pentium III Xeon/Celeron");
  288                                         cpu = CPU_PIII;
  289                                         break;
  290                                 default:
  291                                         strcat(cpu_model, "Unknown 80686");
  292                                         break;
  293                                 }
  294                                 break;
  295                         case 0xf00:
  296                                 strcat(cpu_model, "Pentium 4");
  297                                 cpu = CPU_P4;
  298                                 break;
  299                         default:
  300                                 strcat(cpu_model, "unknown");
  301                                 break;
  302                         }
  303 
  304                         /*
  305                          * If we didn't get a brand name from the extended
  306                          * CPUID, try to look it up in the brand table.
  307                          */
  308                         if (cpu_high > 0 && *cpu_brand == '\0') {
  309                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
  310                                 if (brand_index <= MAX_BRAND_INDEX &&
  311                                     cpu_brandtable[brand_index] != NULL)
  312                                         strcpy(cpu_brand,
  313                                             cpu_brandtable[brand_index]);
  314                         }
  315                 }
  316         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  317                 /*
  318                  * Values taken from AMD Processor Recognition
  319                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  320                  * (also describes ``Features'' encodings.
  321                  */
  322                 strcpy(cpu_model, "AMD ");
  323                 switch (cpu_id & 0xFF0) {
  324                 case 0x410:
  325                         strcat(cpu_model, "Standard Am486DX");
  326                         break;
  327                 case 0x430:
  328                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
  329                         break;
  330                 case 0x470:
  331                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
  332                         break;
  333                 case 0x480:
  334                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
  335                         break;
  336                 case 0x490:
  337                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
  338                         break;
  339                 case 0x4E0:
  340                         strcat(cpu_model, "Am5x86 Write-Through");
  341                         break;
  342                 case 0x4F0:
  343                         strcat(cpu_model, "Am5x86 Write-Back");
  344                         break;
  345                 case 0x500:
  346                         strcat(cpu_model, "K5 model 0");
  347                         tsc_is_broken = 1;
  348                         break;
  349                 case 0x510:
  350                         strcat(cpu_model, "K5 model 1");
  351                         break;
  352                 case 0x520:
  353                         strcat(cpu_model, "K5 PR166 (model 2)");
  354                         break;
  355                 case 0x530:
  356                         strcat(cpu_model, "K5 PR200 (model 3)");
  357                         break;
  358                 case 0x560:
  359                         strcat(cpu_model, "K6");
  360                         break;
  361                 case 0x570:
  362                         strcat(cpu_model, "K6 266 (model 1)");
  363                         break;
  364                 case 0x580:
  365                         strcat(cpu_model, "K6-2");
  366                         break;
  367                 case 0x590:
  368                         strcat(cpu_model, "K6-III");
  369                         break;
  370                 default:
  371                         strcat(cpu_model, "Unknown");
  372                         break;
  373                 }
  374 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  375                 if ((cpu_id & 0xf00) == 0x500) {
  376                         if (((cpu_id & 0x0f0) > 0)
  377                             && ((cpu_id & 0x0f0) < 0x60)
  378                             && ((cpu_id & 0x00f) > 3))
  379                                 enable_K5_wt_alloc();
  380                         else if (((cpu_id & 0x0f0) > 0x80)
  381                                  || (((cpu_id & 0x0f0) == 0x80)
  382                                      && (cpu_id & 0x00f) > 0x07))
  383                                 enable_K6_2_wt_alloc();
  384                         else if ((cpu_id & 0x0f0) > 0x50)
  385                                 enable_K6_wt_alloc();
  386                 }
  387 #endif
  388         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  389                 strcpy(cpu_model, "Cyrix ");
  390                 switch (cpu_id & 0xff0) {
  391                 case 0x440:
  392                         strcat(cpu_model, "MediaGX");
  393                         break;
  394                 case 0x520:
  395                         strcat(cpu_model, "6x86");
  396                         break;
  397                 case 0x540:
  398                         cpu_class = CPUCLASS_586;
  399                         strcat(cpu_model, "GXm");
  400                         break;
  401                 case 0x600:
  402                         strcat(cpu_model, "6x86MX");
  403                         break;
  404                 default:
  405                         /*
  406                          * Even though CPU supports the cpuid
  407                          * instruction, it can be disabled.
  408                          * Therefore, this routine supports all Cyrix
  409                          * CPUs.
  410                          */
  411                         switch (cyrix_did & 0xf0) {
  412                         case 0x00:
  413                                 switch (cyrix_did & 0x0f) {
  414                                 case 0x00:
  415                                         strcat(cpu_model, "486SLC");
  416                                         break;
  417                                 case 0x01:
  418                                         strcat(cpu_model, "486DLC");
  419                                         break;
  420                                 case 0x02:
  421                                         strcat(cpu_model, "486SLC2");
  422                                         break;
  423                                 case 0x03:
  424                                         strcat(cpu_model, "486DLC2");
  425                                         break;
  426                                 case 0x04:
  427                                         strcat(cpu_model, "486SRx");
  428                                         break;
  429                                 case 0x05:
  430                                         strcat(cpu_model, "486DRx");
  431                                         break;
  432                                 case 0x06:
  433                                         strcat(cpu_model, "486SRx2");
  434                                         break;
  435                                 case 0x07:
  436                                         strcat(cpu_model, "486DRx2");
  437                                         break;
  438                                 case 0x08:
  439                                         strcat(cpu_model, "486SRu");
  440                                         break;
  441                                 case 0x09:
  442                                         strcat(cpu_model, "486DRu");
  443                                         break;
  444                                 case 0x0a:
  445                                         strcat(cpu_model, "486SRu2");
  446                                         break;
  447                                 case 0x0b:
  448                                         strcat(cpu_model, "486DRu2");
  449                                         break;
  450                                 default:
  451                                         strcat(cpu_model, "Unknown");
  452                                         break;
  453                                 }
  454                                 break;
  455                         case 0x10:
  456                                 switch (cyrix_did & 0x0f) {
  457                                 case 0x00:
  458                                         strcat(cpu_model, "486S");
  459                                         break;
  460                                 case 0x01:
  461                                         strcat(cpu_model, "486S2");
  462                                         break;
  463                                 case 0x02:
  464                                         strcat(cpu_model, "486Se");
  465                                         break;
  466                                 case 0x03:
  467                                         strcat(cpu_model, "486S2e");
  468                                         break;
  469                                 case 0x0a:
  470                                         strcat(cpu_model, "486DX");
  471                                         break;
  472                                 case 0x0b:
  473                                         strcat(cpu_model, "486DX2");
  474                                         break;
  475                                 case 0x0f:
  476                                         strcat(cpu_model, "486DX4");
  477                                         break;
  478                                 default:
  479                                         strcat(cpu_model, "Unknown");
  480                                         break;
  481                                 }
  482                                 break;
  483                         case 0x20:
  484                                 if ((cyrix_did & 0x0f) < 8)
  485                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
  486                                 else
  487                                         strcat(cpu_model, "5x86");
  488                                 break;
  489                         case 0x30:
  490                                 strcat(cpu_model, "6x86");
  491                                 break;
  492                         case 0x40:
  493                                 if ((cyrix_did & 0xf000) == 0x3000) {
  494                                         cpu_class = CPUCLASS_586;
  495                                         strcat(cpu_model, "GXm");
  496                                 } else
  497                                         strcat(cpu_model, "MediaGX");
  498                                 break;
  499                         case 0x50:
  500                                 strcat(cpu_model, "6x86MX");
  501                                 break;
  502                         case 0xf0:
  503                                 switch (cyrix_did & 0x0f) {
  504                                 case 0x0d:
  505                                         strcat(cpu_model, "Overdrive CPU");
  506                                         break;
  507                                 case 0x0e:
  508                                         strcpy(cpu_model, "Texas Instruments 486SXL");
  509                                         break;
  510                                 case 0x0f:
  511                                         strcat(cpu_model, "486SLC/DLC");
  512                                         break;
  513                                 default:
  514                                         strcat(cpu_model, "Unknown");
  515                                         break;
  516                                 }
  517                                 break;
  518                         default:
  519                                 strcat(cpu_model, "Unknown");
  520                                 break;
  521                         }
  522                         break;
  523                 }
  524         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
  525                 strcpy(cpu_model, "Rise ");
  526                 switch (cpu_id & 0xff0) {
  527                 case 0x500:
  528                         strcat(cpu_model, "mP6");
  529                         break;
  530                 default:
  531                         strcat(cpu_model, "Unknown");
  532                 }
  533         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
  534                 switch (cpu_id & 0xff0) {
  535                 case 0x540:
  536                         strcpy(cpu_model, "IDT WinChip C6");
  537                         tsc_is_broken = 1;
  538                         break;
  539                 case 0x580:
  540                         strcpy(cpu_model, "IDT WinChip 2");
  541                         break;
  542                 case 0x660:
  543                         strcpy(cpu_model, "VIA C3 Samuel");
  544                         break;
  545                 case 0x670:
  546                         if (cpu_id & 0x8)
  547                                 strcpy(cpu_model, "VIA C3 Ezra");
  548                         else
  549                                 strcpy(cpu_model, "VIA C3 Samuel 2");
  550                         break;
  551                 case 0x680:
  552                         strcpy(cpu_model, "VIA C3 Ezra-T");
  553                         break;
  554                 case 0x690:
  555                         strcpy(cpu_model, "VIA C3 Nehemiah");
  556                         do_cpuid(0xc0000000, regs);
  557                         if (regs[0] == 0xc0000001) {
  558                                 do_cpuid(0xc0000001, regs);
  559                                 if ((cpu_id & 0xf) >= 3)
  560                                         if ((regs[3] & 0x0c) == 0x0c)
  561                                                 strcat(cpu_model, "+RNG");
  562                                 if ((cpu_id & 0xf) >= 8)
  563                                         if ((regs[3] & 0xc0) == 0xc0)
  564                                                 strcat(cpu_model, "+ACE");
  565                         }
  566                         break;
  567                 default:
  568                         strcpy(cpu_model, "VIA/IDT Unknown");
  569                 }
  570         } else if (strcmp(cpu_vendor, "IBM") == 0) {
  571                 strcpy(cpu_model, "Blue Lightning CPU");
  572         } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
  573                 switch (cpu_id & 0xfff) {
  574                 case 0x540:
  575                         strcpy(cpu_model, "Geode SC1100");
  576                         cpu = CPU_GEODE1100;
  577                         tsc_is_broken = 1;
  578                         break;
  579                 default:
  580                         strcpy(cpu_model, "Geode/NSC unknown");
  581                         break;
  582                 }
  583         }
  584 
  585         /*
  586          * Replace cpu_model with cpu_brand minus leading spaces if
  587          * we have one.
  588          */
  589         brand = cpu_brand;
  590         while (*brand == ' ')
  591                 ++brand;
  592         if (*brand != '\0')
  593                 strcpy(cpu_model, brand);
  594 
  595 #endif
  596 
  597         printf("%s (", cpu_model);
  598         switch(cpu_class) {
  599         case CPUCLASS_286:
  600                 printf("286");
  601                 break;
  602         case CPUCLASS_386:
  603                 printf("386");
  604                 break;
  605 #if defined(I486_CPU)
  606         case CPUCLASS_486:
  607                 printf("486");
  608                 bzero_vector = i486_bzero;
  609                 break;
  610 #endif
  611 #if defined(I586_CPU)
  612         case CPUCLASS_586:
  613                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  614                 printf("%jd.%02d-MHz ",
  615                        (intmax_t)(tsc_freq + 4999) / 1000000,
  616                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  617                 printf("586");
  618                 break;
  619 #endif
  620 #if defined(I686_CPU)
  621         case CPUCLASS_686:
  622                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  623                 printf("%jd.%02d-MHz ",
  624                        (intmax_t)(tsc_freq + 4999) / 1000000,
  625                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  626                 printf("686");
  627                 break;
  628 #endif
  629         default:
  630                 printf("Unknown");      /* will panic below... */
  631         }
  632         printf("-class CPU)\n");
  633 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  634         if(*cpu_vendor)
  635                 printf("  Origin = \"%s\"",cpu_vendor);
  636         if(cpu_id)
  637                 printf("  Id = 0x%x", cpu_id);
  638 
  639         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  640             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  641             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  642             strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  643             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
  644             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
  645             strcmp(cpu_vendor, "Geode by NSC") == 0 ||
  646                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
  647                  ((cpu_id & 0xf00) > 0x500))) {
  648                 printf("  Stepping = %u", cpu_id & 0xf);
  649                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
  650                         printf("  DIR=0x%04x", cyrix_did);
  651                 if (cpu_high > 0) {
  652                         /*
  653                          * Here we should probably set up flags indicating
  654                          * whether or not various features are available.
  655                          * The interesting ones are probably VME, PSE, PAE,
  656                          * and PGE.  The code already assumes without bothering
  657                          * to check that all CPUs >= Pentium have a TSC and
  658                          * MSRs.
  659                          */
  660                         printf("\n  Features=0x%b", cpu_feature,
  661                         "\020"
  662                         "\001FPU"       /* Integral FPU */
  663                         "\002VME"       /* Extended VM86 mode support */
  664                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  665                         "\004PSE"       /* 4MByte page tables */
  666                         "\005TSC"       /* Timestamp counter */
  667                         "\006MSR"       /* Machine specific registers */
  668                         "\007PAE"       /* Physical address extension */
  669                         "\010MCE"       /* Machine Check support */
  670                         "\011CX8"       /* CMPEXCH8 instruction */
  671                         "\012APIC"      /* SMP local APIC */
  672                         "\013oldMTRR"   /* Previous implementation of MTRR */
  673                         "\014SEP"       /* Fast System Call */
  674                         "\015MTRR"      /* Memory Type Range Registers */
  675                         "\016PGE"       /* PG_G (global bit) support */
  676                         "\017MCA"       /* Machine Check Architecture */
  677                         "\020CMOV"      /* CMOV instruction */
  678                         "\021PAT"       /* Page attributes table */
  679                         "\022PSE36"     /* 36 bit address space support */
  680                         "\023PN"        /* Processor Serial number */
  681                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  682                         "\025<b20>"
  683                         "\026DTS"       /* Debug Trace Store */
  684                         "\027ACPI"      /* ACPI support */
  685                         "\030MMX"       /* MMX instructions */
  686                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  687                         "\032SSE"       /* Streaming SIMD Extensions */
  688                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  689                         "\034SS"        /* Self snoop */
  690                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  691                         "\036TM"        /* Thermal Monitor clock slowdown */
  692                         "\037IA64"      /* CPU can execute IA64 instructions */
  693                         "\040PBE"       /* Pending Break Enable */
  694                         );
  695 
  696                         if (cpu_feature2 != 0) {
  697                                 printf("\n  Features2=0x%b", cpu_feature2,
  698                                 "\020"
  699                                 "\001SSE3"      /* SSE3 */
  700                                 "\002<b1>"
  701                                 "\003RSVD2"     /* "Reserved" bit 2 */
  702                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  703                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  704                                 "\006<b5>"      /* Machine specific registers */
  705                                 "\007<b6>"      /* Physical address extension */
  706                                 "\010EST"       /* Enhanced SpeedStep */
  707                                 "\011TM2"       /* Thermal Monitor 2 */
  708                                 "\012<b9>"
  709                                 "\013CNTX-ID"   /* L1 context ID available */
  710                                 "\014<b11>"
  711                                 "\015<b12>"
  712                                 "\016CX16"      /* CMPXCHG16B Instruction */
  713                                 "\017<b14>"
  714                                 "\020<b15>"
  715                                 "\021<b16>"
  716                                 "\022<b17>"
  717                                 "\023<b18>"
  718                                 "\024<b19>"
  719                                 "\025<b20>"
  720                                 "\026<b21>"
  721                                 "\027<b22>"
  722                                 "\030<b23>"
  723                                 "\031<b24>"
  724                                 "\032<b25>"
  725                                 "\033<b26>"
  726                                 "\034<b27>"
  727                                 "\035<b28>"
  728                                 "\036<b29>"
  729                                 "\037<b30>"
  730                                 "\040<b31>"
  731                                 );
  732                         }
  733                         if (amd_feature != 0) {
  734                                 printf("\n  AMD Features=0x%b", amd_feature,
  735                                 "\020"          /* in hex */
  736                                 "\001<s0>"      /* Same */
  737                                 "\002<s1>"      /* Same */
  738                                 "\003<s2>"      /* Same */
  739                                 "\004<s3>"      /* Same */
  740                                 "\005<s4>"      /* Same */
  741                                 "\006<s5>"      /* Same */
  742                                 "\007<s6>"      /* Same */
  743                                 "\010<s7>"      /* Same */
  744                                 "\011<s8>"      /* Same */
  745                                 "\012<s9>"      /* Same */
  746                                 "\013<b10>"     /* Undefined */
  747                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  748                                 "\015<s12>"     /* Same */
  749                                 "\016<s13>"     /* Same */
  750                                 "\017<s14>"     /* Same */
  751                                 "\020<s15>"     /* Same */
  752                                 "\021<s16>"     /* Same */
  753                                 "\022<s17>"     /* Same */
  754                                 "\023<b18>"     /* Reserved, unknown */
  755                                 "\024MP"        /* Multiprocessor Capable */
  756                                 "\025NX"        /* Has EFER.NXE, NX */
  757                                 "\026<b21>"     /* Undefined */
  758                                 "\027MMX+"      /* AMD MMX Extensions */
  759                                 "\030<s23>"     /* Same */
  760                                 "\031<s24>"     /* Same */
  761                                 "\032<b25>"     /* Undefined */
  762                                 "\033<b26>"     /* Undefined */
  763                                 "\034<b27>"     /* Undefined */
  764                                 "\035<b28>"     /* Undefined */
  765                                 "\036LM"        /* 64 bit long mode */
  766                                 "\0373DNow+"    /* AMD 3DNow! Extensions */
  767                                 "\0403DNow"     /* AMD 3DNow! */
  768                                 );
  769                         }
  770 
  771                         /*
  772                          * If this CPU supports hyperthreading then mention
  773                          * the number of logical CPU's it contains.
  774                          */
  775                         if (cpu_feature & CPUID_HTT &&
  776                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
  777                                 printf("\n  Hyperthreading: %d logical CPUs",
  778                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
  779                 }
  780         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  781                 printf("  DIR=0x%04x", cyrix_did);
  782                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
  783                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
  784 #ifndef CYRIX_CACHE_REALLY_WORKS
  785                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
  786                         printf("\n  CPU cache: write-through mode");
  787 #endif
  788         }
  789         /* Avoid ugly blank lines: only print newline when we have to. */
  790         if (*cpu_vendor || cpu_id)
  791                 printf("\n");
  792 
  793 #endif
  794 
  795         if (!bootverbose)
  796                 return;
  797 
  798         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  799                 print_AMD_info();
  800         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  801                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
  802                 print_transmeta_info();
  803 
  804 #ifdef I686_CPU
  805         /*
  806          * XXX - Do PPro CPUID level=2 stuff here?
  807          *
  808          * No, but maybe in a print_Intel_info() function called from here.
  809          */
  810 #endif
  811 }
  812 
  813 void
  814 panicifcpuunsupported(void)
  815 {
  816 
  817 #if !defined(lint)
  818 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
  819 #error This kernel is not configured for one of the supported CPUs
  820 #endif
  821 #else /* lint */
  822 #endif /* lint */
  823         /*
  824          * Now that we have told the user what they have,
  825          * let them know if that machine type isn't configured.
  826          */
  827         switch (cpu_class) {
  828         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
  829         case CPUCLASS_386:
  830 #if !defined(I486_CPU)
  831         case CPUCLASS_486:
  832 #endif
  833 #if !defined(I586_CPU)
  834         case CPUCLASS_586:
  835 #endif
  836 #if !defined(I686_CPU)
  837         case CPUCLASS_686:
  838 #endif
  839                 panic("CPU class not configured");
  840         default:
  841                 break;
  842         }
  843 }
  844 
  845 
  846 static  volatile u_int trap_by_rdmsr;
  847 
  848 /*
  849  * Special exception 6 handler.
  850  * The rdmsr instruction generates invalid opcodes fault on 486-class
  851  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
  852  * function identblue() when this handler is called.  Stacked eip should
  853  * be advanced.
  854  */
  855 inthand_t       bluetrap6;
  856 #ifdef __GNUCLIKE_ASM
  857 __asm
  858 ("                                                                      \n\
  859         .text                                                           \n\
  860         .p2align 2,0x90                                                 \n\
  861         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
  862 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
  863         ss                                                              \n\
  864         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  865         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  866         iret                                                            \n\
  867 ");
  868 #endif
  869 
  870 /*
  871  * Special exception 13 handler.
  872  * Accessing non-existent MSR generates general protection fault.
  873  */
  874 inthand_t       bluetrap13;
  875 #ifdef __GNUCLIKE_ASM
  876 __asm
  877 ("                                                                      \n\
  878         .text                                                           \n\
  879         .p2align 2,0x90                                                 \n\
  880         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
  881 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
  882         ss                                                              \n\
  883         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  884         popl    %eax            /* discard error code */                \n\
  885         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  886         iret                                                            \n\
  887 ");
  888 #endif
  889 
  890 /*
  891  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
  892  * support cpuid instruction.  This function should be called after
  893  * loading interrupt descriptor table register.
  894  *
  895  * I don't like this method that handles fault, but I couldn't get
  896  * information for any other methods.  Does blue giant know?
  897  */
  898 static int
  899 identblue(void)
  900 {
  901 
  902         trap_by_rdmsr = 0;
  903 
  904         /*
  905          * Cyrix 486-class CPU does not support rdmsr instruction.
  906          * The rdmsr instruction generates invalid opcode fault, and exception
  907          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
  908          * bluetrap6() set the magic number to trap_by_rdmsr.
  909          */
  910         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
  911             GSEL(GCODE_SEL, SEL_KPL));
  912 
  913         /*
  914          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
  915          * In this case, rdmsr generates general protection fault, and
  916          * exception will be trapped by bluetrap13().
  917          */
  918         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
  919             GSEL(GCODE_SEL, SEL_KPL));
  920 
  921         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
  922 
  923         if (trap_by_rdmsr == 0xa8c1d)
  924                 return IDENTBLUE_CYRIX486;
  925         else if (trap_by_rdmsr == 0xa89c4)
  926                 return IDENTBLUE_CYRIXM2;
  927         return IDENTBLUE_IBMCPU;
  928 }
  929 
  930 
  931 /*
  932  * identifycyrix() set lower 16 bits of cyrix_did as follows:
  933  *
  934  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
  935  * +-------+-------+---------------+
  936  * |  SID  |  RID  |   Device ID   |
  937  * |    (DIR 1)    |    (DIR 0)    |
  938  * +-------+-------+---------------+
  939  */
  940 static void
  941 identifycyrix(void)
  942 {
  943         u_int   eflags;
  944         int     ccr2_test = 0, dir_test = 0;
  945         u_char  ccr2, ccr3;
  946 
  947         eflags = read_eflags();
  948         disable_intr();
  949 
  950         ccr2 = read_cyrix_reg(CCR2);
  951         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
  952         read_cyrix_reg(CCR2);
  953         if (read_cyrix_reg(CCR2) != ccr2)
  954                 ccr2_test = 1;
  955         write_cyrix_reg(CCR2, ccr2);
  956 
  957         ccr3 = read_cyrix_reg(CCR3);
  958         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
  959         read_cyrix_reg(CCR3);
  960         if (read_cyrix_reg(CCR3) != ccr3)
  961                 dir_test = 1;                                   /* CPU supports DIRs. */
  962         write_cyrix_reg(CCR3, ccr3);
  963 
  964         if (dir_test) {
  965                 /* Device ID registers are available. */
  966                 cyrix_did = read_cyrix_reg(DIR1) << 8;
  967                 cyrix_did += read_cyrix_reg(DIR0);
  968         } else if (ccr2_test)
  969                 cyrix_did = 0x0010;             /* 486S A-step */
  970         else
  971                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
  972 
  973         write_eflags(eflags);
  974 }
  975 
  976 /*
  977  * Final stage of CPU identification. -- Should I check TI?
  978  */
  979 void
  980 finishidentcpu(void)
  981 {
  982         int     isblue = 0;
  983         u_char  ccr3;
  984         u_int   regs[4];
  985 
  986         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  987                 if (cpu == CPU_486) {
  988                         /*
  989                          * These conditions are equivalent to:
  990                          *     - CPU does not support cpuid instruction.
  991                          *     - Cyrix/IBM CPU is detected.
  992                          */
  993                         isblue = identblue();
  994                         if (isblue == IDENTBLUE_IBMCPU) {
  995                                 strcpy(cpu_vendor, "IBM");
  996                                 cpu = CPU_BLUE;
  997                                 return;
  998                         }
  999                 }
 1000                 switch (cpu_id & 0xf00) {
 1001                 case 0x600:
 1002                         /*
 1003                          * Cyrix's datasheet does not describe DIRs.
 1004                          * Therefor, I assume it does not have them
 1005                          * and use the result of the cpuid instruction.
 1006                          * XXX they seem to have it for now at least. -Peter
 1007                          */
 1008                         identifycyrix();
 1009                         cpu = CPU_M2;
 1010                         break;
 1011                 default:
 1012                         identifycyrix();
 1013                         /*
 1014                          * This routine contains a trick.
 1015                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 1016                          */
 1017                         switch (cyrix_did & 0x00f0) {
 1018                         case 0x00:
 1019                         case 0xf0:
 1020                                 cpu = CPU_486DLC;
 1021                                 break;
 1022                         case 0x10:
 1023                                 cpu = CPU_CY486DX;
 1024                                 break;
 1025                         case 0x20:
 1026                                 if ((cyrix_did & 0x000f) < 8)
 1027                                         cpu = CPU_M1;
 1028                                 else
 1029                                         cpu = CPU_M1SC;
 1030                                 break;
 1031                         case 0x30:
 1032                                 cpu = CPU_M1;
 1033                                 break;
 1034                         case 0x40:
 1035                                 /* MediaGX CPU */
 1036                                 cpu = CPU_M1SC;
 1037                                 break;
 1038                         default:
 1039                                 /* M2 and later CPUs are treated as M2. */
 1040                                 cpu = CPU_M2;
 1041 
 1042                                 /*
 1043                                  * enable cpuid instruction.
 1044                                  */
 1045                                 ccr3 = read_cyrix_reg(CCR3);
 1046                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 1047                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 1048                                 write_cyrix_reg(CCR3, ccr3);
 1049 
 1050                                 do_cpuid(0, regs);
 1051                                 cpu_high = regs[0];     /* eax */
 1052                                 do_cpuid(1, regs);
 1053                                 cpu_id = regs[0];       /* eax */
 1054                                 cpu_feature = regs[3];  /* edx */
 1055                                 break;
 1056                         }
 1057                 }
 1058         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 1059                 /*
 1060                  * There are BlueLightning CPUs that do not change
 1061                  * undefined flags by dividing 5 by 2.  In this case,
 1062                  * the CPU identification routine in locore.s leaves
 1063                  * cpu_vendor null string and puts CPU_486 into the
 1064                  * cpu.
 1065                  */
 1066                 isblue = identblue();
 1067                 if (isblue == IDENTBLUE_IBMCPU) {
 1068                         strcpy(cpu_vendor, "IBM");
 1069                         cpu = CPU_BLUE;
 1070                         return;
 1071                 }
 1072         }
 1073 }
 1074 
 1075 static void
 1076 print_AMD_assoc(int i)
 1077 {
 1078         if (i == 255)
 1079                 printf(", fully associative\n");
 1080         else
 1081                 printf(", %d-way associative\n", i);
 1082 }
 1083 
 1084 static void
 1085 print_AMD_info(void)
 1086 {
 1087         quad_t amd_whcr;
 1088 
 1089         if (cpu_exthigh >= 0x80000005) {
 1090                 u_int regs[4];
 1091 
 1092                 do_cpuid(0x80000005, regs);
 1093                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
 1094                 print_AMD_assoc(regs[1] >> 24);
 1095                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
 1096                 print_AMD_assoc((regs[1] >> 8) & 0xff);
 1097                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
 1098                 printf(", %d bytes/line", regs[2] & 0xff);
 1099                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 1100                 print_AMD_assoc((regs[2] >> 16) & 0xff);
 1101                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 1102                 printf(", %d bytes/line", regs[3] & 0xff);
 1103                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 1104                 print_AMD_assoc((regs[3] >> 16) & 0xff);
 1105                 if (cpu_exthigh >= 0x80000006) {        /* K6-III only */
 1106                         do_cpuid(0x80000006, regs);
 1107                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
 1108                         printf(", %d bytes/line", regs[2] & 0xff);
 1109                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 1110                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
 1111                 }
 1112         }
 1113         if (((cpu_id & 0xf00) == 0x500)
 1114             && (((cpu_id & 0x0f0) > 0x80)
 1115                 || (((cpu_id & 0x0f0) == 0x80)
 1116                     && (cpu_id & 0x00f) > 0x07))) {
 1117                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
 1118                 amd_whcr = rdmsr(0xc0000082);
 1119                 if (!(amd_whcr & (0x3ff << 22))) {
 1120                         printf("Write Allocate Disable\n");
 1121                 } else {
 1122                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1123                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
 1124                         printf("Write Allocate 15-16M bytes: %s\n",
 1125                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
 1126                 }
 1127         } else if (((cpu_id & 0xf00) == 0x500)
 1128                    && ((cpu_id & 0x0f0) > 0x50)) {
 1129                 /* K6, K6-2(old core) */
 1130                 amd_whcr = rdmsr(0xc0000082);
 1131                 if (!(amd_whcr & (0x7f << 1))) {
 1132                         printf("Write Allocate Disable\n");
 1133                 } else {
 1134                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1135                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
 1136                         printf("Write Allocate 15-16M bytes: %s\n",
 1137                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
 1138                         printf("Hardware Write Allocate Control: %s\n",
 1139                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
 1140                 }
 1141         }
 1142 }
 1143 
 1144 static void
 1145 print_transmeta_info()
 1146 {
 1147         u_int regs[4], nreg = 0;
 1148 
 1149         do_cpuid(0x80860000, regs);
 1150         nreg = regs[0];
 1151         if (nreg >= 0x80860001) {
 1152                 do_cpuid(0x80860001, regs);
 1153                 printf("  Processor revision %u.%u.%u.%u\n",
 1154                        (regs[1] >> 24) & 0xff,
 1155                        (regs[1] >> 16) & 0xff,
 1156                        (regs[1] >> 8) & 0xff,
 1157                        regs[1] & 0xff);
 1158         }
 1159         if (nreg >= 0x80860002) {
 1160                 do_cpuid(0x80860002, regs);
 1161                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
 1162                        (regs[1] >> 24) & 0xff,
 1163                        (regs[1] >> 16) & 0xff,
 1164                        (regs[1] >> 8) & 0xff,
 1165                        regs[1] & 0xff,
 1166                        regs[2]);
 1167         }
 1168         if (nreg >= 0x80860006) {
 1169                 char info[65];
 1170                 do_cpuid(0x80860003, (u_int*) &info[0]);
 1171                 do_cpuid(0x80860004, (u_int*) &info[16]);
 1172                 do_cpuid(0x80860005, (u_int*) &info[32]);
 1173                 do_cpuid(0x80860006, (u_int*) &info[48]);
 1174                 info[64] = 0;
 1175                 printf("  %s\n", info);
 1176         }
 1177 }

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