1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/6.1/sys/i386/i386/identcpu.c 157998 2006-04-24 18:24:31Z jkim $");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <sys/power.h>
52
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/md_var.h>
58 #include <machine/segments.h>
59 #include <machine/specialreg.h>
60
61 #define IDENTBLUE_CYRIX486 0
62 #define IDENTBLUE_IBMCPU 1
63 #define IDENTBLUE_CYRIXM2 2
64
65 /* XXX - should be in header file: */
66 void printcpuinfo(void);
67 void finishidentcpu(void);
68 void earlysetcpuclass(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
73 #endif
74 void panicifcpuunsupported(void);
75
76 static void identifycyrix(void);
77 static void print_AMD_info(void);
78 static void print_AMD_assoc(int i);
79 static void print_transmeta_info(void);
80
81 int cpu_class;
82 u_int cpu_exthigh; /* Highest arg to extended CPUID */
83 u_int cyrix_did; /* Device ID of Cyrix CPU */
84 char machine[] = "i386";
85 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
86 machine, 0, "Machine class");
87
88 static char cpu_model[128];
89 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
90 cpu_model, 0, "Machine model");
91
92 static int hw_clockrate;
93 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
94 &hw_clockrate, 0, "CPU instruction clock rate");
95
96 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
97 static char cpu_brand[48];
98
99 #define MAX_BRAND_INDEX 8
100
101 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
102 NULL, /* No brand */
103 "Intel Celeron",
104 "Intel Pentium III",
105 "Intel Pentium III Xeon",
106 NULL,
107 NULL,
108 NULL,
109 NULL,
110 "Intel Pentium 4"
111 };
112 #endif
113
114 static struct {
115 char *cpu_name;
116 int cpu_class;
117 } i386_cpus[] = {
118 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
119 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
120 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
121 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
122 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
123 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
124 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
125 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
126 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
127 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
128 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
129 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
130 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
131 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
132 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
133 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
134 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
135 };
136
137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
138 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
139 #endif
140
141 void
142 printcpuinfo(void)
143 {
144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
145 u_int regs[4], i;
146 char *brand;
147 #endif
148
149 cpu_class = i386_cpus[cpu].cpu_class;
150 printf("CPU: ");
151 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
152
153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
154 /* Check for extended CPUID information and a processor name. */
155 if (cpu_high > 0 &&
156 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
157 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
158 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
159 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
160 strcmp(cpu_vendor, "Geode by NSC") == 0)) {
161 do_cpuid(0x80000000, regs);
162 if (regs[0] >= 0x80000000) {
163 cpu_exthigh = regs[0];
164 if (cpu_exthigh >= 0x80000004) {
165 brand = cpu_brand;
166 for (i = 0x80000002; i < 0x80000005; i++) {
167 do_cpuid(i, regs);
168 memcpy(brand, regs, sizeof(regs));
169 brand += sizeof(regs);
170 }
171 }
172 }
173 }
174
175 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
176 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
177 strcmp(cpu_vendor, "AuthenticAMD") == 0) {
178 if (cpu_exthigh >= 0x80000001) {
179 do_cpuid(0x80000001, regs);
180 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
181 amd_feature2 = regs[2];
182 }
183 if (cpu_exthigh >= 0x80000008) {
184 do_cpuid(0x80000008, regs);
185 cpu_procinfo2 = regs[2];
186 }
187 }
188
189 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
190 if ((cpu_id & 0xf00) > 0x300) {
191 u_int brand_index;
192
193 cpu_model[0] = '\0';
194
195 switch (cpu_id & 0x3000) {
196 case 0x1000:
197 strcpy(cpu_model, "Overdrive ");
198 break;
199 case 0x2000:
200 strcpy(cpu_model, "Dual ");
201 break;
202 }
203
204 switch (cpu_id & 0xf00) {
205 case 0x400:
206 strcat(cpu_model, "i486 ");
207 /* Check the particular flavor of 486 */
208 switch (cpu_id & 0xf0) {
209 case 0x00:
210 case 0x10:
211 strcat(cpu_model, "DX");
212 break;
213 case 0x20:
214 strcat(cpu_model, "SX");
215 break;
216 case 0x30:
217 strcat(cpu_model, "DX2");
218 break;
219 case 0x40:
220 strcat(cpu_model, "SL");
221 break;
222 case 0x50:
223 strcat(cpu_model, "SX2");
224 break;
225 case 0x70:
226 strcat(cpu_model,
227 "DX2 Write-Back Enhanced");
228 break;
229 case 0x80:
230 strcat(cpu_model, "DX4");
231 break;
232 }
233 break;
234 case 0x500:
235 /* Check the particular flavor of 586 */
236 strcat(cpu_model, "Pentium");
237 switch (cpu_id & 0xf0) {
238 case 0x00:
239 strcat(cpu_model, " A-step");
240 break;
241 case 0x10:
242 strcat(cpu_model, "/P5");
243 break;
244 case 0x20:
245 strcat(cpu_model, "/P54C");
246 break;
247 case 0x30:
248 strcat(cpu_model, "/P54T Overdrive");
249 break;
250 case 0x40:
251 strcat(cpu_model, "/P55C");
252 break;
253 case 0x70:
254 strcat(cpu_model, "/P54C");
255 break;
256 case 0x80:
257 strcat(cpu_model, "/P55C (quarter-micron)");
258 break;
259 default:
260 /* nothing */
261 break;
262 }
263 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
264 /*
265 * XXX - If/when Intel fixes the bug, this
266 * should also check the version of the
267 * CPU, not just that it's a Pentium.
268 */
269 has_f00f_bug = 1;
270 #endif
271 break;
272 case 0x600:
273 /* Check the particular flavor of 686 */
274 switch (cpu_id & 0xf0) {
275 case 0x00:
276 strcat(cpu_model, "Pentium Pro A-step");
277 break;
278 case 0x10:
279 strcat(cpu_model, "Pentium Pro");
280 break;
281 case 0x30:
282 case 0x50:
283 case 0x60:
284 strcat(cpu_model,
285 "Pentium II/Pentium II Xeon/Celeron");
286 cpu = CPU_PII;
287 break;
288 case 0x70:
289 case 0x80:
290 case 0xa0:
291 case 0xb0:
292 strcat(cpu_model,
293 "Pentium III/Pentium III Xeon/Celeron");
294 cpu = CPU_PIII;
295 break;
296 default:
297 strcat(cpu_model, "Unknown 80686");
298 break;
299 }
300 break;
301 case 0xf00:
302 strcat(cpu_model, "Pentium 4");
303 cpu = CPU_P4;
304 break;
305 default:
306 strcat(cpu_model, "unknown");
307 break;
308 }
309
310 /*
311 * If we didn't get a brand name from the extended
312 * CPUID, try to look it up in the brand table.
313 */
314 if (cpu_high > 0 && *cpu_brand == '\0') {
315 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
316 if (brand_index <= MAX_BRAND_INDEX &&
317 cpu_brandtable[brand_index] != NULL)
318 strcpy(cpu_brand,
319 cpu_brandtable[brand_index]);
320 }
321 }
322 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
323 /*
324 * Values taken from AMD Processor Recognition
325 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
326 * (also describes ``Features'' encodings.
327 */
328 strcpy(cpu_model, "AMD ");
329 switch (cpu_id & 0xFF0) {
330 case 0x410:
331 strcat(cpu_model, "Standard Am486DX");
332 break;
333 case 0x430:
334 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
335 break;
336 case 0x470:
337 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
338 break;
339 case 0x480:
340 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
341 break;
342 case 0x490:
343 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
344 break;
345 case 0x4E0:
346 strcat(cpu_model, "Am5x86 Write-Through");
347 break;
348 case 0x4F0:
349 strcat(cpu_model, "Am5x86 Write-Back");
350 break;
351 case 0x500:
352 strcat(cpu_model, "K5 model 0");
353 tsc_is_broken = 1;
354 break;
355 case 0x510:
356 strcat(cpu_model, "K5 model 1");
357 break;
358 case 0x520:
359 strcat(cpu_model, "K5 PR166 (model 2)");
360 break;
361 case 0x530:
362 strcat(cpu_model, "K5 PR200 (model 3)");
363 break;
364 case 0x560:
365 strcat(cpu_model, "K6");
366 break;
367 case 0x570:
368 strcat(cpu_model, "K6 266 (model 1)");
369 break;
370 case 0x580:
371 strcat(cpu_model, "K6-2");
372 break;
373 case 0x590:
374 strcat(cpu_model, "K6-III");
375 break;
376 default:
377 strcat(cpu_model, "Unknown");
378 break;
379 }
380 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
381 if ((cpu_id & 0xf00) == 0x500) {
382 if (((cpu_id & 0x0f0) > 0)
383 && ((cpu_id & 0x0f0) < 0x60)
384 && ((cpu_id & 0x00f) > 3))
385 enable_K5_wt_alloc();
386 else if (((cpu_id & 0x0f0) > 0x80)
387 || (((cpu_id & 0x0f0) == 0x80)
388 && (cpu_id & 0x00f) > 0x07))
389 enable_K6_2_wt_alloc();
390 else if ((cpu_id & 0x0f0) > 0x50)
391 enable_K6_wt_alloc();
392 }
393 #endif
394 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
395 strcpy(cpu_model, "Cyrix ");
396 switch (cpu_id & 0xff0) {
397 case 0x440:
398 strcat(cpu_model, "MediaGX");
399 break;
400 case 0x520:
401 strcat(cpu_model, "6x86");
402 break;
403 case 0x540:
404 cpu_class = CPUCLASS_586;
405 strcat(cpu_model, "GXm");
406 break;
407 case 0x600:
408 strcat(cpu_model, "6x86MX");
409 break;
410 default:
411 /*
412 * Even though CPU supports the cpuid
413 * instruction, it can be disabled.
414 * Therefore, this routine supports all Cyrix
415 * CPUs.
416 */
417 switch (cyrix_did & 0xf0) {
418 case 0x00:
419 switch (cyrix_did & 0x0f) {
420 case 0x00:
421 strcat(cpu_model, "486SLC");
422 break;
423 case 0x01:
424 strcat(cpu_model, "486DLC");
425 break;
426 case 0x02:
427 strcat(cpu_model, "486SLC2");
428 break;
429 case 0x03:
430 strcat(cpu_model, "486DLC2");
431 break;
432 case 0x04:
433 strcat(cpu_model, "486SRx");
434 break;
435 case 0x05:
436 strcat(cpu_model, "486DRx");
437 break;
438 case 0x06:
439 strcat(cpu_model, "486SRx2");
440 break;
441 case 0x07:
442 strcat(cpu_model, "486DRx2");
443 break;
444 case 0x08:
445 strcat(cpu_model, "486SRu");
446 break;
447 case 0x09:
448 strcat(cpu_model, "486DRu");
449 break;
450 case 0x0a:
451 strcat(cpu_model, "486SRu2");
452 break;
453 case 0x0b:
454 strcat(cpu_model, "486DRu2");
455 break;
456 default:
457 strcat(cpu_model, "Unknown");
458 break;
459 }
460 break;
461 case 0x10:
462 switch (cyrix_did & 0x0f) {
463 case 0x00:
464 strcat(cpu_model, "486S");
465 break;
466 case 0x01:
467 strcat(cpu_model, "486S2");
468 break;
469 case 0x02:
470 strcat(cpu_model, "486Se");
471 break;
472 case 0x03:
473 strcat(cpu_model, "486S2e");
474 break;
475 case 0x0a:
476 strcat(cpu_model, "486DX");
477 break;
478 case 0x0b:
479 strcat(cpu_model, "486DX2");
480 break;
481 case 0x0f:
482 strcat(cpu_model, "486DX4");
483 break;
484 default:
485 strcat(cpu_model, "Unknown");
486 break;
487 }
488 break;
489 case 0x20:
490 if ((cyrix_did & 0x0f) < 8)
491 strcat(cpu_model, "6x86"); /* Where did you get it? */
492 else
493 strcat(cpu_model, "5x86");
494 break;
495 case 0x30:
496 strcat(cpu_model, "6x86");
497 break;
498 case 0x40:
499 if ((cyrix_did & 0xf000) == 0x3000) {
500 cpu_class = CPUCLASS_586;
501 strcat(cpu_model, "GXm");
502 } else
503 strcat(cpu_model, "MediaGX");
504 break;
505 case 0x50:
506 strcat(cpu_model, "6x86MX");
507 break;
508 case 0xf0:
509 switch (cyrix_did & 0x0f) {
510 case 0x0d:
511 strcat(cpu_model, "Overdrive CPU");
512 break;
513 case 0x0e:
514 strcpy(cpu_model, "Texas Instruments 486SXL");
515 break;
516 case 0x0f:
517 strcat(cpu_model, "486SLC/DLC");
518 break;
519 default:
520 strcat(cpu_model, "Unknown");
521 break;
522 }
523 break;
524 default:
525 strcat(cpu_model, "Unknown");
526 break;
527 }
528 break;
529 }
530 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
531 strcpy(cpu_model, "Rise ");
532 switch (cpu_id & 0xff0) {
533 case 0x500:
534 strcat(cpu_model, "mP6");
535 break;
536 default:
537 strcat(cpu_model, "Unknown");
538 }
539 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
540 switch (cpu_id & 0xff0) {
541 case 0x540:
542 strcpy(cpu_model, "IDT WinChip C6");
543 tsc_is_broken = 1;
544 break;
545 case 0x580:
546 strcpy(cpu_model, "IDT WinChip 2");
547 break;
548 case 0x660:
549 strcpy(cpu_model, "VIA C3 Samuel");
550 break;
551 case 0x670:
552 if (cpu_id & 0x8)
553 strcpy(cpu_model, "VIA C3 Ezra");
554 else
555 strcpy(cpu_model, "VIA C3 Samuel 2");
556 break;
557 case 0x680:
558 strcpy(cpu_model, "VIA C3 Ezra-T");
559 break;
560 case 0x690:
561 strcpy(cpu_model, "VIA C3 Nehemiah");
562 do_cpuid(0xc0000000, regs);
563 if (regs[0] == 0xc0000001) {
564 do_cpuid(0xc0000001, regs);
565 if ((cpu_id & 0xf) >= 3)
566 if ((regs[3] & 0x0c) == 0x0c)
567 strcat(cpu_model, "+RNG");
568 if ((cpu_id & 0xf) >= 8)
569 if ((regs[3] & 0xc0) == 0xc0)
570 strcat(cpu_model, "+ACE");
571 }
572 break;
573 default:
574 strcpy(cpu_model, "VIA/IDT Unknown");
575 }
576 } else if (strcmp(cpu_vendor, "IBM") == 0) {
577 strcpy(cpu_model, "Blue Lightning CPU");
578 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
579 switch (cpu_id & 0xfff) {
580 case 0x540:
581 strcpy(cpu_model, "Geode SC1100");
582 cpu = CPU_GEODE1100;
583 tsc_is_broken = 1;
584 break;
585 default:
586 strcpy(cpu_model, "Geode/NSC unknown");
587 break;
588 }
589 }
590
591 /*
592 * Replace cpu_model with cpu_brand minus leading spaces if
593 * we have one.
594 */
595 brand = cpu_brand;
596 while (*brand == ' ')
597 ++brand;
598 if (*brand != '\0')
599 strcpy(cpu_model, brand);
600
601 #endif
602
603 printf("%s (", cpu_model);
604 switch(cpu_class) {
605 case CPUCLASS_286:
606 printf("286");
607 break;
608 case CPUCLASS_386:
609 printf("386");
610 break;
611 #if defined(I486_CPU)
612 case CPUCLASS_486:
613 printf("486");
614 bzero_vector = i486_bzero;
615 break;
616 #endif
617 #if defined(I586_CPU)
618 case CPUCLASS_586:
619 hw_clockrate = (tsc_freq + 5000) / 1000000;
620 printf("%jd.%02d-MHz ",
621 (intmax_t)(tsc_freq + 4999) / 1000000,
622 (u_int)((tsc_freq + 4999) / 10000) % 100);
623 printf("586");
624 break;
625 #endif
626 #if defined(I686_CPU)
627 case CPUCLASS_686:
628 hw_clockrate = (tsc_freq + 5000) / 1000000;
629 printf("%jd.%02d-MHz ",
630 (intmax_t)(tsc_freq + 4999) / 1000000,
631 (u_int)((tsc_freq + 4999) / 10000) % 100);
632 printf("686");
633 break;
634 #endif
635 default:
636 printf("Unknown"); /* will panic below... */
637 }
638 printf("-class CPU)\n");
639 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
640 if(*cpu_vendor)
641 printf(" Origin = \"%s\"",cpu_vendor);
642 if(cpu_id)
643 printf(" Id = 0x%x", cpu_id);
644
645 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
646 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
647 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
648 strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
649 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
650 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
651 strcmp(cpu_vendor, "Geode by NSC") == 0 ||
652 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
653 ((cpu_id & 0xf00) > 0x500))) {
654 printf(" Stepping = %u", cpu_id & 0xf);
655 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
656 printf(" DIR=0x%04x", cyrix_did);
657 if (cpu_high > 0) {
658 u_int cmp = 1, htt = 1;
659
660 /*
661 * Here we should probably set up flags indicating
662 * whether or not various features are available.
663 * The interesting ones are probably VME, PSE, PAE,
664 * and PGE. The code already assumes without bothering
665 * to check that all CPUs >= Pentium have a TSC and
666 * MSRs.
667 */
668 printf("\n Features=0x%b", cpu_feature,
669 "\020"
670 "\001FPU" /* Integral FPU */
671 "\002VME" /* Extended VM86 mode support */
672 "\003DE" /* Debugging Extensions (CR4.DE) */
673 "\004PSE" /* 4MByte page tables */
674 "\005TSC" /* Timestamp counter */
675 "\006MSR" /* Machine specific registers */
676 "\007PAE" /* Physical address extension */
677 "\010MCE" /* Machine Check support */
678 "\011CX8" /* CMPEXCH8 instruction */
679 "\012APIC" /* SMP local APIC */
680 "\013oldMTRR" /* Previous implementation of MTRR */
681 "\014SEP" /* Fast System Call */
682 "\015MTRR" /* Memory Type Range Registers */
683 "\016PGE" /* PG_G (global bit) support */
684 "\017MCA" /* Machine Check Architecture */
685 "\020CMOV" /* CMOV instruction */
686 "\021PAT" /* Page attributes table */
687 "\022PSE36" /* 36 bit address space support */
688 "\023PN" /* Processor Serial number */
689 "\024CLFLUSH" /* Has the CLFLUSH instruction */
690 "\025<b20>"
691 "\026DTS" /* Debug Trace Store */
692 "\027ACPI" /* ACPI support */
693 "\030MMX" /* MMX instructions */
694 "\031FXSR" /* FXSAVE/FXRSTOR */
695 "\032SSE" /* Streaming SIMD Extensions */
696 "\033SSE2" /* Streaming SIMD Extensions #2 */
697 "\034SS" /* Self snoop */
698 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
699 "\036TM" /* Thermal Monitor clock slowdown */
700 "\037IA64" /* CPU can execute IA64 instructions */
701 "\040PBE" /* Pending Break Enable */
702 );
703
704 if (cpu_feature2 != 0) {
705 printf("\n Features2=0x%b", cpu_feature2,
706 "\020"
707 "\001SSE3" /* SSE3 */
708 "\002<b1>"
709 "\003RSVD2" /* "Reserved" bit 2 */
710 "\004MON" /* MONITOR/MWAIT Instructions */
711 "\005DS_CPL" /* CPL Qualified Debug Store */
712 "\006VMX" /* Virtual Machine Extensions */
713 "\007<b6>"
714 "\010EST" /* Enhanced SpeedStep */
715 "\011TM2" /* Thermal Monitor 2 */
716 "\012<b9>"
717 "\013CNTX-ID" /* L1 context ID available */
718 "\014<b11>"
719 "\015<b12>"
720 "\016CX16" /* CMPXCHG16B Instruction */
721 "\017<b14>"
722 "\020<b15>"
723 "\021<b16>"
724 "\022<b17>"
725 "\023<b18>"
726 "\024<b19>"
727 "\025<b20>"
728 "\026<b21>"
729 "\027<b22>"
730 "\030<b23>"
731 "\031<b24>"
732 "\032<b25>"
733 "\033<b26>"
734 "\034<b27>"
735 "\035<b28>"
736 "\036<b29>"
737 "\037<b30>"
738 "\040<b31>"
739 );
740 }
741
742 /*
743 * AMD64 Architecture Programmer's Manual Volume 3:
744 * General-Purpose and System Instructions
745 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
746 *
747 * IA-32 Intel Architecture Software Developer's Manual,
748 * Volume 2A: Instruction Set Reference, A-M
749 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
750 */
751 if (amd_feature != 0) {
752 printf("\n AMD Features=0x%b", amd_feature,
753 "\020" /* in hex */
754 "\001<s0>" /* Same */
755 "\002<s1>" /* Same */
756 "\003<s2>" /* Same */
757 "\004<s3>" /* Same */
758 "\005<s4>" /* Same */
759 "\006<s5>" /* Same */
760 "\007<s6>" /* Same */
761 "\010<s7>" /* Same */
762 "\011<s8>" /* Same */
763 "\012<s9>" /* Same */
764 "\013<b10>" /* Undefined */
765 "\014SYSCALL" /* Have SYSCALL/SYSRET */
766 "\015<s12>" /* Same */
767 "\016<s13>" /* Same */
768 "\017<s14>" /* Same */
769 "\020<s15>" /* Same */
770 "\021<s16>" /* Same */
771 "\022<s17>" /* Same */
772 "\023<b18>" /* Reserved, unknown */
773 "\024MP" /* Multiprocessor Capable */
774 "\025NX" /* Has EFER.NXE, NX */
775 "\026<b21>" /* Undefined */
776 "\027MMX+" /* AMD MMX Extensions */
777 "\030<s23>" /* Same */
778 "\031<s24>" /* Same */
779 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
780 "\033<b26>" /* Undefined */
781 "\034RDTSCP" /* RDTSCP */
782 "\035<b28>" /* Undefined */
783 "\036LM" /* 64 bit long mode */
784 "\0373DNow+" /* AMD 3DNow! Extensions */
785 "\0403DNow" /* AMD 3DNow! */
786 );
787 }
788
789 if (amd_feature2 != 0) {
790 printf("\n AMD Features2=0x%b", amd_feature2,
791 "\020"
792 "\001LAHF" /* LAHF/SAHF in long mode */
793 "\002CMP" /* CMP legacy */
794 "\003<b2>"
795 "\004<b3>"
796 "\005CR8" /* CR8 in legacy mode */
797 "\006<b5>"
798 "\007<b6>"
799 "\010<b7>"
800 "\011<b8>"
801 "\012<b9>"
802 "\013<b10>"
803 "\014<b11>"
804 "\015<b12>"
805 "\016<b13>"
806 "\017<b14>"
807 "\020<b15>"
808 "\021<b16>"
809 "\022<b17>"
810 "\023<b18>"
811 "\024<b19>"
812 "\025<b20>"
813 "\026<b21>"
814 "\027<b22>"
815 "\030<b23>"
816 "\031<b24>"
817 "\032<b25>"
818 "\033<b26>"
819 "\034<b27>"
820 "\035<b28>"
821 "\036<b29>"
822 "\037<b30>"
823 "\040<b31>"
824 );
825 }
826
827 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
828 "AuthenticAMD") == 0) {
829 cpu_feature &= ~CPUID_HTT;
830 if (bootverbose)
831 printf("\n HTT bit cleared - FreeBSD"
832 " does not have licensing issues"
833 " requiring it.\n");
834 }
835
836 /*
837 * If this CPU supports HTT or CMP then mention the
838 * number of physical/logical cores it contains.
839 */
840 if (cpu_feature & CPUID_HTT)
841 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
842 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
843 (amd_feature2 & AMDID2_CMP))
844 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
845 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
846 (cpu_high >= 4)) {
847 cpuid_count(4, 0, regs);
848 cmp = ((regs[0] & 0xfc000000) >> 26) + 1;
849 }
850 if (cmp > 1)
851 printf("\n Cores per package: %d", cmp);
852 if ((htt / cmp) > 1)
853 printf("\n Logical CPUs per core: %d",
854 htt / cmp);
855 }
856 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
857 printf(" DIR=0x%04x", cyrix_did);
858 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
859 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
860 #ifndef CYRIX_CACHE_REALLY_WORKS
861 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
862 printf("\n CPU cache: write-through mode");
863 #endif
864 }
865 /* Avoid ugly blank lines: only print newline when we have to. */
866 if (*cpu_vendor || cpu_id)
867 printf("\n");
868
869 #endif
870
871 if (!bootverbose)
872 return;
873
874 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
875 print_AMD_info();
876 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
877 strcmp(cpu_vendor, "TransmetaCPU") == 0)
878 print_transmeta_info();
879
880 #ifdef I686_CPU
881 /*
882 * XXX - Do PPro CPUID level=2 stuff here?
883 *
884 * No, but maybe in a print_Intel_info() function called from here.
885 */
886 #endif
887 }
888
889 void
890 panicifcpuunsupported(void)
891 {
892
893 #if !defined(lint)
894 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
895 #error This kernel is not configured for one of the supported CPUs
896 #endif
897 #else /* lint */
898 #endif /* lint */
899 /*
900 * Now that we have told the user what they have,
901 * let them know if that machine type isn't configured.
902 */
903 switch (cpu_class) {
904 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
905 case CPUCLASS_386:
906 #if !defined(I486_CPU)
907 case CPUCLASS_486:
908 #endif
909 #if !defined(I586_CPU)
910 case CPUCLASS_586:
911 #endif
912 #if !defined(I686_CPU)
913 case CPUCLASS_686:
914 #endif
915 panic("CPU class not configured");
916 default:
917 break;
918 }
919 }
920
921
922 static volatile u_int trap_by_rdmsr;
923
924 /*
925 * Special exception 6 handler.
926 * The rdmsr instruction generates invalid opcodes fault on 486-class
927 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
928 * function identblue() when this handler is called. Stacked eip should
929 * be advanced.
930 */
931 inthand_t bluetrap6;
932 #ifdef __GNUCLIKE_ASM
933 __asm
934 (" \n\
935 .text \n\
936 .p2align 2,0x90 \n\
937 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
938 " __XSTRING(CNAME(bluetrap6)) ": \n\
939 ss \n\
940 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
941 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
942 iret \n\
943 ");
944 #endif
945
946 /*
947 * Special exception 13 handler.
948 * Accessing non-existent MSR generates general protection fault.
949 */
950 inthand_t bluetrap13;
951 #ifdef __GNUCLIKE_ASM
952 __asm
953 (" \n\
954 .text \n\
955 .p2align 2,0x90 \n\
956 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
957 " __XSTRING(CNAME(bluetrap13)) ": \n\
958 ss \n\
959 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
960 popl %eax /* discard error code */ \n\
961 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
962 iret \n\
963 ");
964 #endif
965
966 /*
967 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
968 * support cpuid instruction. This function should be called after
969 * loading interrupt descriptor table register.
970 *
971 * I don't like this method that handles fault, but I couldn't get
972 * information for any other methods. Does blue giant know?
973 */
974 static int
975 identblue(void)
976 {
977
978 trap_by_rdmsr = 0;
979
980 /*
981 * Cyrix 486-class CPU does not support rdmsr instruction.
982 * The rdmsr instruction generates invalid opcode fault, and exception
983 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
984 * bluetrap6() set the magic number to trap_by_rdmsr.
985 */
986 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
987 GSEL(GCODE_SEL, SEL_KPL));
988
989 /*
990 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
991 * In this case, rdmsr generates general protection fault, and
992 * exception will be trapped by bluetrap13().
993 */
994 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
995 GSEL(GCODE_SEL, SEL_KPL));
996
997 rdmsr(0x1002); /* Cyrix CPU generates fault. */
998
999 if (trap_by_rdmsr == 0xa8c1d)
1000 return IDENTBLUE_CYRIX486;
1001 else if (trap_by_rdmsr == 0xa89c4)
1002 return IDENTBLUE_CYRIXM2;
1003 return IDENTBLUE_IBMCPU;
1004 }
1005
1006
1007 /*
1008 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1009 *
1010 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1011 * +-------+-------+---------------+
1012 * | SID | RID | Device ID |
1013 * | (DIR 1) | (DIR 0) |
1014 * +-------+-------+---------------+
1015 */
1016 static void
1017 identifycyrix(void)
1018 {
1019 u_int eflags;
1020 int ccr2_test = 0, dir_test = 0;
1021 u_char ccr2, ccr3;
1022
1023 eflags = read_eflags();
1024 disable_intr();
1025
1026 ccr2 = read_cyrix_reg(CCR2);
1027 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1028 read_cyrix_reg(CCR2);
1029 if (read_cyrix_reg(CCR2) != ccr2)
1030 ccr2_test = 1;
1031 write_cyrix_reg(CCR2, ccr2);
1032
1033 ccr3 = read_cyrix_reg(CCR3);
1034 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1035 read_cyrix_reg(CCR3);
1036 if (read_cyrix_reg(CCR3) != ccr3)
1037 dir_test = 1; /* CPU supports DIRs. */
1038 write_cyrix_reg(CCR3, ccr3);
1039
1040 if (dir_test) {
1041 /* Device ID registers are available. */
1042 cyrix_did = read_cyrix_reg(DIR1) << 8;
1043 cyrix_did += read_cyrix_reg(DIR0);
1044 } else if (ccr2_test)
1045 cyrix_did = 0x0010; /* 486S A-step */
1046 else
1047 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1048
1049 write_eflags(eflags);
1050 }
1051
1052 /*
1053 * Final stage of CPU identification. -- Should I check TI?
1054 */
1055 void
1056 finishidentcpu(void)
1057 {
1058 int isblue = 0;
1059 u_char ccr3;
1060 u_int regs[4];
1061
1062 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
1063 if (cpu == CPU_486) {
1064 /*
1065 * These conditions are equivalent to:
1066 * - CPU does not support cpuid instruction.
1067 * - Cyrix/IBM CPU is detected.
1068 */
1069 isblue = identblue();
1070 if (isblue == IDENTBLUE_IBMCPU) {
1071 strcpy(cpu_vendor, "IBM");
1072 cpu = CPU_BLUE;
1073 return;
1074 }
1075 }
1076 switch (cpu_id & 0xf00) {
1077 case 0x600:
1078 /*
1079 * Cyrix's datasheet does not describe DIRs.
1080 * Therefor, I assume it does not have them
1081 * and use the result of the cpuid instruction.
1082 * XXX they seem to have it for now at least. -Peter
1083 */
1084 identifycyrix();
1085 cpu = CPU_M2;
1086 break;
1087 default:
1088 identifycyrix();
1089 /*
1090 * This routine contains a trick.
1091 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1092 */
1093 switch (cyrix_did & 0x00f0) {
1094 case 0x00:
1095 case 0xf0:
1096 cpu = CPU_486DLC;
1097 break;
1098 case 0x10:
1099 cpu = CPU_CY486DX;
1100 break;
1101 case 0x20:
1102 if ((cyrix_did & 0x000f) < 8)
1103 cpu = CPU_M1;
1104 else
1105 cpu = CPU_M1SC;
1106 break;
1107 case 0x30:
1108 cpu = CPU_M1;
1109 break;
1110 case 0x40:
1111 /* MediaGX CPU */
1112 cpu = CPU_M1SC;
1113 break;
1114 default:
1115 /* M2 and later CPUs are treated as M2. */
1116 cpu = CPU_M2;
1117
1118 /*
1119 * enable cpuid instruction.
1120 */
1121 ccr3 = read_cyrix_reg(CCR3);
1122 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1123 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1124 write_cyrix_reg(CCR3, ccr3);
1125
1126 do_cpuid(0, regs);
1127 cpu_high = regs[0]; /* eax */
1128 do_cpuid(1, regs);
1129 cpu_id = regs[0]; /* eax */
1130 cpu_feature = regs[3]; /* edx */
1131 break;
1132 }
1133 }
1134 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1135 /*
1136 * There are BlueLightning CPUs that do not change
1137 * undefined flags by dividing 5 by 2. In this case,
1138 * the CPU identification routine in locore.s leaves
1139 * cpu_vendor null string and puts CPU_486 into the
1140 * cpu.
1141 */
1142 isblue = identblue();
1143 if (isblue == IDENTBLUE_IBMCPU) {
1144 strcpy(cpu_vendor, "IBM");
1145 cpu = CPU_BLUE;
1146 return;
1147 }
1148 }
1149 }
1150
1151 static void
1152 print_AMD_assoc(int i)
1153 {
1154 if (i == 255)
1155 printf(", fully associative\n");
1156 else
1157 printf(", %d-way associative\n", i);
1158 }
1159
1160 static void
1161 print_AMD_info(void)
1162 {
1163 quad_t amd_whcr;
1164
1165 if (cpu_exthigh >= 0x80000005) {
1166 u_int regs[4];
1167
1168 do_cpuid(0x80000005, regs);
1169 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1170 print_AMD_assoc(regs[1] >> 24);
1171 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1172 print_AMD_assoc((regs[1] >> 8) & 0xff);
1173 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1174 printf(", %d bytes/line", regs[2] & 0xff);
1175 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1176 print_AMD_assoc((regs[2] >> 16) & 0xff);
1177 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1178 printf(", %d bytes/line", regs[3] & 0xff);
1179 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1180 print_AMD_assoc((regs[3] >> 16) & 0xff);
1181 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1182 do_cpuid(0x80000006, regs);
1183 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1184 printf(", %d bytes/line", regs[2] & 0xff);
1185 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1186 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1187 }
1188 }
1189 if (((cpu_id & 0xf00) == 0x500)
1190 && (((cpu_id & 0x0f0) > 0x80)
1191 || (((cpu_id & 0x0f0) == 0x80)
1192 && (cpu_id & 0x00f) > 0x07))) {
1193 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1194 amd_whcr = rdmsr(0xc0000082);
1195 if (!(amd_whcr & (0x3ff << 22))) {
1196 printf("Write Allocate Disable\n");
1197 } else {
1198 printf("Write Allocate Enable Limit: %dM bytes\n",
1199 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1200 printf("Write Allocate 15-16M bytes: %s\n",
1201 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1202 }
1203 } else if (((cpu_id & 0xf00) == 0x500)
1204 && ((cpu_id & 0x0f0) > 0x50)) {
1205 /* K6, K6-2(old core) */
1206 amd_whcr = rdmsr(0xc0000082);
1207 if (!(amd_whcr & (0x7f << 1))) {
1208 printf("Write Allocate Disable\n");
1209 } else {
1210 printf("Write Allocate Enable Limit: %dM bytes\n",
1211 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1212 printf("Write Allocate 15-16M bytes: %s\n",
1213 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1214 printf("Hardware Write Allocate Control: %s\n",
1215 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1216 }
1217 }
1218 }
1219
1220 static void
1221 print_transmeta_info()
1222 {
1223 u_int regs[4], nreg = 0;
1224
1225 do_cpuid(0x80860000, regs);
1226 nreg = regs[0];
1227 if (nreg >= 0x80860001) {
1228 do_cpuid(0x80860001, regs);
1229 printf(" Processor revision %u.%u.%u.%u\n",
1230 (regs[1] >> 24) & 0xff,
1231 (regs[1] >> 16) & 0xff,
1232 (regs[1] >> 8) & 0xff,
1233 regs[1] & 0xff);
1234 }
1235 if (nreg >= 0x80860002) {
1236 do_cpuid(0x80860002, regs);
1237 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1238 (regs[1] >> 24) & 0xff,
1239 (regs[1] >> 16) & 0xff,
1240 (regs[1] >> 8) & 0xff,
1241 regs[1] & 0xff,
1242 regs[2]);
1243 }
1244 if (nreg >= 0x80860006) {
1245 char info[65];
1246 do_cpuid(0x80860003, (u_int*) &info[0]);
1247 do_cpuid(0x80860004, (u_int*) &info[16]);
1248 do_cpuid(0x80860005, (u_int*) &info[32]);
1249 do_cpuid(0x80860006, (u_int*) &info[48]);
1250 info[64] = 0;
1251 printf(" %s\n", info);
1252 }
1253 }
Cache object: 648648a2971ebeee56a0a63a46e11adf
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