The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/identcpu.c

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    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/6.2/sys/i386/i386/identcpu.c 161076 2006-08-08 08:41:34Z mr $");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/systm.h>
   49 #include <sys/kernel.h>
   50 #include <sys/sysctl.h>
   51 #include <sys/power.h>
   52 
   53 #include <machine/asmacros.h>
   54 #include <machine/clock.h>
   55 #include <machine/cputypes.h>
   56 #include <machine/intr_machdep.h>
   57 #include <machine/md_var.h>
   58 #include <machine/segments.h>
   59 #include <machine/specialreg.h>
   60 
   61 #define IDENTBLUE_CYRIX486      0
   62 #define IDENTBLUE_IBMCPU        1
   63 #define IDENTBLUE_CYRIXM2       2
   64 
   65 /* XXX - should be in header file: */
   66 void printcpuinfo(void);
   67 void finishidentcpu(void);
   68 void earlysetcpuclass(void);
   69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   70 void    enable_K5_wt_alloc(void);
   71 void    enable_K6_wt_alloc(void);
   72 void    enable_K6_2_wt_alloc(void);
   73 #endif
   74 void panicifcpuunsupported(void);
   75 
   76 static void identifycyrix(void);
   77 static void print_AMD_info(void);
   78 static void print_AMD_assoc(int i);
   79 static void print_transmeta_info(void);
   80 
   81 int     cpu_class;
   82 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   83 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
   84 char machine[] = "i386";
   85 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   86     machine, 0, "Machine class");
   87 
   88 static char cpu_model[128];
   89 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   90     cpu_model, 0, "Machine model");
   91 
   92 static int hw_clockrate;
   93 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
   94     &hw_clockrate, 0, "CPU instruction clock rate");
   95 
   96 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
   97 static char cpu_brand[48];
   98 
   99 #define MAX_BRAND_INDEX 8
  100 
  101 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
  102         NULL,                   /* No brand */
  103         "Intel Celeron",
  104         "Intel Pentium III",
  105         "Intel Pentium III Xeon",
  106         NULL,
  107         NULL,
  108         NULL,
  109         NULL,
  110         "Intel Pentium 4"
  111 };
  112 #endif
  113 
  114 static struct {
  115         char    *cpu_name;
  116         int     cpu_class;
  117 } i386_cpus[] = {
  118         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
  119         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
  120         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
  121         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
  122         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
  123         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
  124         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
  125         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
  126         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
  127         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
  128         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
  129         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
  130         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
  131         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
  132         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
  133         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
  134         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
  135 };
  136 
  137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  138 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
  139 #endif
  140 
  141 void
  142 printcpuinfo(void)
  143 {
  144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  145         u_int regs[4], i;
  146         char *brand;
  147 #endif
  148 
  149         cpu_class = i386_cpus[cpu].cpu_class;
  150         printf("CPU: ");
  151         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
  152 
  153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  154         /* Check for extended CPUID information and a processor name. */
  155         if (cpu_high > 0 &&
  156             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  157             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  158             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  159             strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  160             strcmp(cpu_vendor, "Geode by NSC") == 0)) {
  161                 do_cpuid(0x80000000, regs);
  162                 if (regs[0] >= 0x80000000) {
  163                         cpu_exthigh = regs[0];
  164                         if (cpu_exthigh >= 0x80000004) {
  165                                 brand = cpu_brand;
  166                                 for (i = 0x80000002; i < 0x80000005; i++) {
  167                                         do_cpuid(i, regs);
  168                                         memcpy(brand, regs, sizeof(regs));
  169                                         brand += sizeof(regs);
  170                                 }
  171                         }
  172                 }
  173         }
  174 
  175         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
  176         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  177             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  178                 if (cpu_exthigh >= 0x80000001) {
  179                         do_cpuid(0x80000001, regs);
  180                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
  181                         amd_feature2 = regs[2];
  182                 }
  183                 if (cpu_exthigh >= 0x80000008) {
  184                         do_cpuid(0x80000008, regs);
  185                         cpu_procinfo2 = regs[2];
  186                 }
  187         }
  188 
  189         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  190                 if ((cpu_id & 0xf00) > 0x300) {
  191                         u_int brand_index;
  192 
  193                         cpu_model[0] = '\0';
  194 
  195                         switch (cpu_id & 0x3000) {
  196                         case 0x1000:
  197                                 strcpy(cpu_model, "Overdrive ");
  198                                 break;
  199                         case 0x2000:
  200                                 strcpy(cpu_model, "Dual ");
  201                                 break;
  202                         }
  203 
  204                         switch (cpu_id & 0xf00) {
  205                         case 0x400:
  206                                 strcat(cpu_model, "i486 ");
  207                                 /* Check the particular flavor of 486 */
  208                                 switch (cpu_id & 0xf0) {
  209                                 case 0x00:
  210                                 case 0x10:
  211                                         strcat(cpu_model, "DX");
  212                                         break;
  213                                 case 0x20:
  214                                         strcat(cpu_model, "SX");
  215                                         break;
  216                                 case 0x30:
  217                                         strcat(cpu_model, "DX2");
  218                                         break;
  219                                 case 0x40:
  220                                         strcat(cpu_model, "SL");
  221                                         break;
  222                                 case 0x50:
  223                                         strcat(cpu_model, "SX2");
  224                                         break;
  225                                 case 0x70:
  226                                         strcat(cpu_model,
  227                                             "DX2 Write-Back Enhanced");
  228                                         break;
  229                                 case 0x80:
  230                                         strcat(cpu_model, "DX4");
  231                                         break;
  232                                 }
  233                                 break;
  234                         case 0x500:
  235                                 /* Check the particular flavor of 586 */
  236                                 strcat(cpu_model, "Pentium");
  237                                 switch (cpu_id & 0xf0) {
  238                                 case 0x00:
  239                                         strcat(cpu_model, " A-step");
  240                                         break;
  241                                 case 0x10:
  242                                         strcat(cpu_model, "/P5");
  243                                         break;
  244                                 case 0x20:
  245                                         strcat(cpu_model, "/P54C");
  246                                         break;
  247                                 case 0x30:
  248                                         strcat(cpu_model, "/P54T Overdrive");
  249                                         break;
  250                                 case 0x40:
  251                                         strcat(cpu_model, "/P55C");
  252                                         break;
  253                                 case 0x70:
  254                                         strcat(cpu_model, "/P54C");
  255                                         break;
  256                                 case 0x80:
  257                                         strcat(cpu_model, "/P55C (quarter-micron)");
  258                                         break;
  259                                 default:
  260                                         /* nothing */
  261                                         break;
  262                                 }
  263 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  264                                 /*
  265                                  * XXX - If/when Intel fixes the bug, this
  266                                  * should also check the version of the
  267                                  * CPU, not just that it's a Pentium.
  268                                  */
  269                                 has_f00f_bug = 1;
  270 #endif
  271                                 break;
  272                         case 0x600:
  273                                 /* Check the particular flavor of 686 */
  274                                 switch (cpu_id & 0xf0) {
  275                                 case 0x00:
  276                                         strcat(cpu_model, "Pentium Pro A-step");
  277                                         break;
  278                                 case 0x10:
  279                                         strcat(cpu_model, "Pentium Pro");
  280                                         break;
  281                                 case 0x30:
  282                                 case 0x50:
  283                                 case 0x60:
  284                                         strcat(cpu_model,
  285                                 "Pentium II/Pentium II Xeon/Celeron");
  286                                         cpu = CPU_PII;
  287                                         break;
  288                                 case 0x70:
  289                                 case 0x80:
  290                                 case 0xa0:
  291                                 case 0xb0:
  292                                         strcat(cpu_model,
  293                                         "Pentium III/Pentium III Xeon/Celeron");
  294                                         cpu = CPU_PIII;
  295                                         break;
  296                                 default:
  297                                         strcat(cpu_model, "Unknown 80686");
  298                                         break;
  299                                 }
  300                                 break;
  301                         case 0xf00:
  302                                 strcat(cpu_model, "Pentium 4");
  303                                 cpu = CPU_P4;
  304                                 break;
  305                         default:
  306                                 strcat(cpu_model, "unknown");
  307                                 break;
  308                         }
  309 
  310                         /*
  311                          * If we didn't get a brand name from the extended
  312                          * CPUID, try to look it up in the brand table.
  313                          */
  314                         if (cpu_high > 0 && *cpu_brand == '\0') {
  315                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
  316                                 if (brand_index <= MAX_BRAND_INDEX &&
  317                                     cpu_brandtable[brand_index] != NULL)
  318                                         strcpy(cpu_brand,
  319                                             cpu_brandtable[brand_index]);
  320                         }
  321                 }
  322         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  323                 /*
  324                  * Values taken from AMD Processor Recognition
  325                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  326                  * (also describes ``Features'' encodings.
  327                  */
  328                 strcpy(cpu_model, "AMD ");
  329                 switch (cpu_id & 0xFF0) {
  330                 case 0x410:
  331                         strcat(cpu_model, "Standard Am486DX");
  332                         break;
  333                 case 0x430:
  334                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
  335                         break;
  336                 case 0x470:
  337                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
  338                         break;
  339                 case 0x480:
  340                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
  341                         break;
  342                 case 0x490:
  343                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
  344                         break;
  345                 case 0x4E0:
  346                         strcat(cpu_model, "Am5x86 Write-Through");
  347                         break;
  348                 case 0x4F0:
  349                         strcat(cpu_model, "Am5x86 Write-Back");
  350                         break;
  351                 case 0x500:
  352                         strcat(cpu_model, "K5 model 0");
  353                         tsc_is_broken = 1;
  354                         break;
  355                 case 0x510:
  356                         strcat(cpu_model, "K5 model 1");
  357                         break;
  358                 case 0x520:
  359                         strcat(cpu_model, "K5 PR166 (model 2)");
  360                         break;
  361                 case 0x530:
  362                         strcat(cpu_model, "K5 PR200 (model 3)");
  363                         break;
  364                 case 0x560:
  365                         strcat(cpu_model, "K6");
  366                         break;
  367                 case 0x570:
  368                         strcat(cpu_model, "K6 266 (model 1)");
  369                         break;
  370                 case 0x580:
  371                         strcat(cpu_model, "K6-2");
  372                         break;
  373                 case 0x590:
  374                         strcat(cpu_model, "K6-III");
  375                         break;
  376                 default:
  377                         strcat(cpu_model, "Unknown");
  378                         break;
  379                 }
  380 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  381                 if ((cpu_id & 0xf00) == 0x500) {
  382                         if (((cpu_id & 0x0f0) > 0)
  383                             && ((cpu_id & 0x0f0) < 0x60)
  384                             && ((cpu_id & 0x00f) > 3))
  385                                 enable_K5_wt_alloc();
  386                         else if (((cpu_id & 0x0f0) > 0x80)
  387                                  || (((cpu_id & 0x0f0) == 0x80)
  388                                      && (cpu_id & 0x00f) > 0x07))
  389                                 enable_K6_2_wt_alloc();
  390                         else if ((cpu_id & 0x0f0) > 0x50)
  391                                 enable_K6_wt_alloc();
  392                 }
  393 #endif
  394         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  395                 strcpy(cpu_model, "Cyrix ");
  396                 switch (cpu_id & 0xff0) {
  397                 case 0x440:
  398                         strcat(cpu_model, "MediaGX");
  399                         break;
  400                 case 0x520:
  401                         strcat(cpu_model, "6x86");
  402                         break;
  403                 case 0x540:
  404                         cpu_class = CPUCLASS_586;
  405                         strcat(cpu_model, "GXm");
  406                         break;
  407                 case 0x600:
  408                         strcat(cpu_model, "6x86MX");
  409                         break;
  410                 default:
  411                         /*
  412                          * Even though CPU supports the cpuid
  413                          * instruction, it can be disabled.
  414                          * Therefore, this routine supports all Cyrix
  415                          * CPUs.
  416                          */
  417                         switch (cyrix_did & 0xf0) {
  418                         case 0x00:
  419                                 switch (cyrix_did & 0x0f) {
  420                                 case 0x00:
  421                                         strcat(cpu_model, "486SLC");
  422                                         break;
  423                                 case 0x01:
  424                                         strcat(cpu_model, "486DLC");
  425                                         break;
  426                                 case 0x02:
  427                                         strcat(cpu_model, "486SLC2");
  428                                         break;
  429                                 case 0x03:
  430                                         strcat(cpu_model, "486DLC2");
  431                                         break;
  432                                 case 0x04:
  433                                         strcat(cpu_model, "486SRx");
  434                                         break;
  435                                 case 0x05:
  436                                         strcat(cpu_model, "486DRx");
  437                                         break;
  438                                 case 0x06:
  439                                         strcat(cpu_model, "486SRx2");
  440                                         break;
  441                                 case 0x07:
  442                                         strcat(cpu_model, "486DRx2");
  443                                         break;
  444                                 case 0x08:
  445                                         strcat(cpu_model, "486SRu");
  446                                         break;
  447                                 case 0x09:
  448                                         strcat(cpu_model, "486DRu");
  449                                         break;
  450                                 case 0x0a:
  451                                         strcat(cpu_model, "486SRu2");
  452                                         break;
  453                                 case 0x0b:
  454                                         strcat(cpu_model, "486DRu2");
  455                                         break;
  456                                 default:
  457                                         strcat(cpu_model, "Unknown");
  458                                         break;
  459                                 }
  460                                 break;
  461                         case 0x10:
  462                                 switch (cyrix_did & 0x0f) {
  463                                 case 0x00:
  464                                         strcat(cpu_model, "486S");
  465                                         break;
  466                                 case 0x01:
  467                                         strcat(cpu_model, "486S2");
  468                                         break;
  469                                 case 0x02:
  470                                         strcat(cpu_model, "486Se");
  471                                         break;
  472                                 case 0x03:
  473                                         strcat(cpu_model, "486S2e");
  474                                         break;
  475                                 case 0x0a:
  476                                         strcat(cpu_model, "486DX");
  477                                         break;
  478                                 case 0x0b:
  479                                         strcat(cpu_model, "486DX2");
  480                                         break;
  481                                 case 0x0f:
  482                                         strcat(cpu_model, "486DX4");
  483                                         break;
  484                                 default:
  485                                         strcat(cpu_model, "Unknown");
  486                                         break;
  487                                 }
  488                                 break;
  489                         case 0x20:
  490                                 if ((cyrix_did & 0x0f) < 8)
  491                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
  492                                 else
  493                                         strcat(cpu_model, "5x86");
  494                                 break;
  495                         case 0x30:
  496                                 strcat(cpu_model, "6x86");
  497                                 break;
  498                         case 0x40:
  499                                 if ((cyrix_did & 0xf000) == 0x3000) {
  500                                         cpu_class = CPUCLASS_586;
  501                                         strcat(cpu_model, "GXm");
  502                                 } else
  503                                         strcat(cpu_model, "MediaGX");
  504                                 break;
  505                         case 0x50:
  506                                 strcat(cpu_model, "6x86MX");
  507                                 break;
  508                         case 0xf0:
  509                                 switch (cyrix_did & 0x0f) {
  510                                 case 0x0d:
  511                                         strcat(cpu_model, "Overdrive CPU");
  512                                         break;
  513                                 case 0x0e:
  514                                         strcpy(cpu_model, "Texas Instruments 486SXL");
  515                                         break;
  516                                 case 0x0f:
  517                                         strcat(cpu_model, "486SLC/DLC");
  518                                         break;
  519                                 default:
  520                                         strcat(cpu_model, "Unknown");
  521                                         break;
  522                                 }
  523                                 break;
  524                         default:
  525                                 strcat(cpu_model, "Unknown");
  526                                 break;
  527                         }
  528                         break;
  529                 }
  530         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
  531                 strcpy(cpu_model, "Rise ");
  532                 switch (cpu_id & 0xff0) {
  533                 case 0x500:
  534                         strcat(cpu_model, "mP6");
  535                         break;
  536                 default:
  537                         strcat(cpu_model, "Unknown");
  538                 }
  539         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
  540                 switch (cpu_id & 0xff0) {
  541                 case 0x540:
  542                         strcpy(cpu_model, "IDT WinChip C6");
  543                         tsc_is_broken = 1;
  544                         break;
  545                 case 0x580:
  546                         strcpy(cpu_model, "IDT WinChip 2");
  547                         break;
  548                 case 0x660:
  549                         strcpy(cpu_model, "VIA C3 Samuel");
  550                         break;
  551                 case 0x670:
  552                         if (cpu_id & 0x8)
  553                                 strcpy(cpu_model, "VIA C3 Ezra");
  554                         else
  555                                 strcpy(cpu_model, "VIA C3 Samuel 2");
  556                         break;
  557                 case 0x680:
  558                         strcpy(cpu_model, "VIA C3 Ezra-T");
  559                         break;
  560                 case 0x690:
  561                         strcpy(cpu_model, "VIA C3 Nehemiah");
  562                         if ((cpu_id & 0xf) < 3)
  563                                 break;
  564                         goto via_common;
  565                 case 0x6a0:
  566                         strcpy(cpu_model, "VIA C7 Esther");
  567 via_common:
  568                         do_cpuid(0xc0000000, regs);
  569                         i = regs[0];
  570                         if (i >= 0xC0000001) {
  571                                 do_cpuid(0xc0000001, regs);
  572                                 i = regs[3];
  573                         } else
  574                                 i = 0;
  575                         if (i & VIA_CPUID_HAS_RNG)
  576                                 strcat(cpu_model, "+RNG");
  577 
  578                         if (i & VIA_CPUID_HAS_ACE)
  579                                 strcat(cpu_model, "+AES");
  580 
  581                         if (i & VIA_CPUID_HAS_ACE2)
  582                                 strcat(cpu_model, "+AES-CTR");
  583 
  584                         if (i & VIA_CPUID_HAS_PHE)
  585                                 strcat(cpu_model, "+SHA1+SHA256");
  586 
  587                         if (i & VIA_CPUID_HAS_PMM)
  588                                 strcat(cpu_model, "+RSA");
  589                         break;
  590                 default:
  591                         strcpy(cpu_model, "VIA/IDT Unknown");
  592                 }
  593         } else if (strcmp(cpu_vendor, "IBM") == 0) {
  594                 strcpy(cpu_model, "Blue Lightning CPU");
  595         } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
  596                 switch (cpu_id & 0xfff) {
  597                 case 0x540:
  598                         strcpy(cpu_model, "Geode SC1100");
  599                         cpu = CPU_GEODE1100;
  600                         tsc_is_broken = 1;
  601                         break;
  602                 default:
  603                         strcpy(cpu_model, "Geode/NSC unknown");
  604                         break;
  605                 }
  606         }
  607 
  608         /*
  609          * Replace cpu_model with cpu_brand minus leading spaces if
  610          * we have one.
  611          */
  612         brand = cpu_brand;
  613         while (*brand == ' ')
  614                 ++brand;
  615         if (*brand != '\0')
  616                 strcpy(cpu_model, brand);
  617 
  618 #endif
  619 
  620         printf("%s (", cpu_model);
  621         switch(cpu_class) {
  622         case CPUCLASS_286:
  623                 printf("286");
  624                 break;
  625         case CPUCLASS_386:
  626                 printf("386");
  627                 break;
  628 #if defined(I486_CPU)
  629         case CPUCLASS_486:
  630                 printf("486");
  631                 bzero_vector = i486_bzero;
  632                 break;
  633 #endif
  634 #if defined(I586_CPU)
  635         case CPUCLASS_586:
  636                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  637                 printf("%jd.%02d-MHz ",
  638                        (intmax_t)(tsc_freq + 4999) / 1000000,
  639                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  640                 printf("586");
  641                 break;
  642 #endif
  643 #if defined(I686_CPU)
  644         case CPUCLASS_686:
  645                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  646                 printf("%jd.%02d-MHz ",
  647                        (intmax_t)(tsc_freq + 4999) / 1000000,
  648                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  649                 printf("686");
  650                 break;
  651 #endif
  652         default:
  653                 printf("Unknown");      /* will panic below... */
  654         }
  655         printf("-class CPU)\n");
  656 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  657         if(*cpu_vendor)
  658                 printf("  Origin = \"%s\"",cpu_vendor);
  659         if(cpu_id)
  660                 printf("  Id = 0x%x", cpu_id);
  661 
  662         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  663             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  664             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  665             strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  666             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
  667             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
  668             strcmp(cpu_vendor, "Geode by NSC") == 0 ||
  669                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
  670                  ((cpu_id & 0xf00) > 0x500))) {
  671                 printf("  Stepping = %u", cpu_id & 0xf);
  672                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
  673                         printf("  DIR=0x%04x", cyrix_did);
  674                 if (cpu_high > 0) {
  675                         u_int cmp = 1, htt = 1;
  676 
  677                         /*
  678                          * Here we should probably set up flags indicating
  679                          * whether or not various features are available.
  680                          * The interesting ones are probably VME, PSE, PAE,
  681                          * and PGE.  The code already assumes without bothering
  682                          * to check that all CPUs >= Pentium have a TSC and
  683                          * MSRs.
  684                          */
  685                         printf("\n  Features=0x%b", cpu_feature,
  686                         "\020"
  687                         "\001FPU"       /* Integral FPU */
  688                         "\002VME"       /* Extended VM86 mode support */
  689                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  690                         "\004PSE"       /* 4MByte page tables */
  691                         "\005TSC"       /* Timestamp counter */
  692                         "\006MSR"       /* Machine specific registers */
  693                         "\007PAE"       /* Physical address extension */
  694                         "\010MCE"       /* Machine Check support */
  695                         "\011CX8"       /* CMPEXCH8 instruction */
  696                         "\012APIC"      /* SMP local APIC */
  697                         "\013oldMTRR"   /* Previous implementation of MTRR */
  698                         "\014SEP"       /* Fast System Call */
  699                         "\015MTRR"      /* Memory Type Range Registers */
  700                         "\016PGE"       /* PG_G (global bit) support */
  701                         "\017MCA"       /* Machine Check Architecture */
  702                         "\020CMOV"      /* CMOV instruction */
  703                         "\021PAT"       /* Page attributes table */
  704                         "\022PSE36"     /* 36 bit address space support */
  705                         "\023PN"        /* Processor Serial number */
  706                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  707                         "\025<b20>"
  708                         "\026DTS"       /* Debug Trace Store */
  709                         "\027ACPI"      /* ACPI support */
  710                         "\030MMX"       /* MMX instructions */
  711                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  712                         "\032SSE"       /* Streaming SIMD Extensions */
  713                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  714                         "\034SS"        /* Self snoop */
  715                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  716                         "\036TM"        /* Thermal Monitor clock slowdown */
  717                         "\037IA64"      /* CPU can execute IA64 instructions */
  718                         "\040PBE"       /* Pending Break Enable */
  719                         );
  720 
  721                         if (cpu_feature2 != 0) {
  722                                 printf("\n  Features2=0x%b", cpu_feature2,
  723                                 "\020"
  724                                 "\001SSE3"      /* SSE3 */
  725                                 "\002<b1>"
  726                                 "\003RSVD2"     /* "Reserved" bit 2 */
  727                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  728                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  729                                 "\006VMX"       /* Virtual Machine Extensions */
  730                                 "\007<b6>"
  731                                 "\010EST"       /* Enhanced SpeedStep */
  732                                 "\011TM2"       /* Thermal Monitor 2 */
  733                                 "\012<b9>"
  734                                 "\013CNTX-ID"   /* L1 context ID available */
  735                                 "\014<b11>"
  736                                 "\015<b12>"
  737                                 "\016CX16"      /* CMPXCHG16B Instruction */
  738                                 "\017<b14>"
  739                                 "\020<b15>"
  740                                 "\021<b16>"
  741                                 "\022<b17>"
  742                                 "\023<b18>"
  743                                 "\024<b19>"
  744                                 "\025<b20>"
  745                                 "\026<b21>"
  746                                 "\027<b22>"
  747                                 "\030<b23>"
  748                                 "\031<b24>"
  749                                 "\032<b25>"
  750                                 "\033<b26>"
  751                                 "\034<b27>"
  752                                 "\035<b28>"
  753                                 "\036<b29>"
  754                                 "\037<b30>"
  755                                 "\040<b31>"
  756                                 );
  757                         }
  758 
  759                         /*
  760                          * AMD64 Architecture Programmer's Manual Volume 3:
  761                          * General-Purpose and System Instructions
  762                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
  763                          *
  764                          * IA-32 Intel Architecture Software Developer's Manual,
  765                          * Volume 2A: Instruction Set Reference, A-M
  766                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
  767                          */
  768                         if (amd_feature != 0) {
  769                                 printf("\n  AMD Features=0x%b", amd_feature,
  770                                 "\020"          /* in hex */
  771                                 "\001<s0>"      /* Same */
  772                                 "\002<s1>"      /* Same */
  773                                 "\003<s2>"      /* Same */
  774                                 "\004<s3>"      /* Same */
  775                                 "\005<s4>"      /* Same */
  776                                 "\006<s5>"      /* Same */
  777                                 "\007<s6>"      /* Same */
  778                                 "\010<s7>"      /* Same */
  779                                 "\011<s8>"      /* Same */
  780                                 "\012<s9>"      /* Same */
  781                                 "\013<b10>"     /* Undefined */
  782                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  783                                 "\015<s12>"     /* Same */
  784                                 "\016<s13>"     /* Same */
  785                                 "\017<s14>"     /* Same */
  786                                 "\020<s15>"     /* Same */
  787                                 "\021<s16>"     /* Same */
  788                                 "\022<s17>"     /* Same */
  789                                 "\023<b18>"     /* Reserved, unknown */
  790                                 "\024MP"        /* Multiprocessor Capable */
  791                                 "\025NX"        /* Has EFER.NXE, NX */
  792                                 "\026<b21>"     /* Undefined */
  793                                 "\027MMX+"      /* AMD MMX Extensions */
  794                                 "\030<s23>"     /* Same */
  795                                 "\031<s24>"     /* Same */
  796                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
  797                                 "\033<b26>"     /* Undefined */
  798                                 "\034RDTSCP"    /* RDTSCP */
  799                                 "\035<b28>"     /* Undefined */
  800                                 "\036LM"        /* 64 bit long mode */
  801                                 "\0373DNow+"    /* AMD 3DNow! Extensions */
  802                                 "\0403DNow"     /* AMD 3DNow! */
  803                                 );
  804                         }
  805 
  806                         if (amd_feature2 != 0) {
  807                                 printf("\n  AMD Features2=0x%b", amd_feature2,
  808                                 "\020"
  809                                 "\001LAHF"      /* LAHF/SAHF in long mode */
  810                                 "\002CMP"       /* CMP legacy */
  811                                 "\003<b2>"
  812                                 "\004<b3>"
  813                                 "\005CR8"       /* CR8 in legacy mode */
  814                                 "\006<b5>"
  815                                 "\007<b6>"
  816                                 "\010<b7>"
  817                                 "\011<b8>"
  818                                 "\012<b9>"
  819                                 "\013<b10>"
  820                                 "\014<b11>"
  821                                 "\015<b12>"
  822                                 "\016<b13>"
  823                                 "\017<b14>"
  824                                 "\020<b15>"
  825                                 "\021<b16>"
  826                                 "\022<b17>"
  827                                 "\023<b18>"
  828                                 "\024<b19>"
  829                                 "\025<b20>"
  830                                 "\026<b21>"
  831                                 "\027<b22>"
  832                                 "\030<b23>"
  833                                 "\031<b24>"
  834                                 "\032<b25>"
  835                                 "\033<b26>"
  836                                 "\034<b27>"
  837                                 "\035<b28>"
  838                                 "\036<b29>"
  839                                 "\037<b30>"
  840                                 "\040<b31>"
  841                                 );
  842                         }
  843 
  844                         if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
  845                             "AuthenticAMD") == 0) {
  846                                 cpu_feature &= ~CPUID_HTT;
  847                                 if (bootverbose)
  848                                         printf("\n    HTT bit cleared - FreeBSD"
  849                                             " does not have licensing issues"
  850                                             " requiring it.\n");
  851                         }
  852 
  853                         /*
  854                          * If this CPU supports HTT or CMP then mention the
  855                          * number of physical/logical cores it contains.
  856                          */
  857                         if (cpu_feature & CPUID_HTT)
  858                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
  859                         if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
  860                             (amd_feature2 & AMDID2_CMP))
  861                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  862                         else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
  863                             (cpu_high >= 4)) {
  864                                 cpuid_count(4, 0, regs);
  865                                 cmp = ((regs[0] & 0xfc000000) >> 26) + 1;
  866                         }
  867                         if (cmp > 1)
  868                                 printf("\n  Cores per package: %d", cmp);
  869                         if ((htt / cmp) > 1)
  870                                 printf("\n  Logical CPUs per core: %d",
  871                                     htt / cmp);
  872                 }
  873         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  874                 printf("  DIR=0x%04x", cyrix_did);
  875                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
  876                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
  877 #ifndef CYRIX_CACHE_REALLY_WORKS
  878                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
  879                         printf("\n  CPU cache: write-through mode");
  880 #endif
  881         }
  882         /* Avoid ugly blank lines: only print newline when we have to. */
  883         if (*cpu_vendor || cpu_id)
  884                 printf("\n");
  885 
  886 #endif
  887 
  888         if (!bootverbose)
  889                 return;
  890 
  891         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  892                 print_AMD_info();
  893         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  894                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
  895                 print_transmeta_info();
  896 
  897 #ifdef I686_CPU
  898         /*
  899          * XXX - Do PPro CPUID level=2 stuff here?
  900          *
  901          * No, but maybe in a print_Intel_info() function called from here.
  902          */
  903 #endif
  904 }
  905 
  906 void
  907 panicifcpuunsupported(void)
  908 {
  909 
  910 #if !defined(lint)
  911 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
  912 #error This kernel is not configured for one of the supported CPUs
  913 #endif
  914 #else /* lint */
  915 #endif /* lint */
  916         /*
  917          * Now that we have told the user what they have,
  918          * let them know if that machine type isn't configured.
  919          */
  920         switch (cpu_class) {
  921         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
  922         case CPUCLASS_386:
  923 #if !defined(I486_CPU)
  924         case CPUCLASS_486:
  925 #endif
  926 #if !defined(I586_CPU)
  927         case CPUCLASS_586:
  928 #endif
  929 #if !defined(I686_CPU)
  930         case CPUCLASS_686:
  931 #endif
  932                 panic("CPU class not configured");
  933         default:
  934                 break;
  935         }
  936 }
  937 
  938 
  939 static  volatile u_int trap_by_rdmsr;
  940 
  941 /*
  942  * Special exception 6 handler.
  943  * The rdmsr instruction generates invalid opcodes fault on 486-class
  944  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
  945  * function identblue() when this handler is called.  Stacked eip should
  946  * be advanced.
  947  */
  948 inthand_t       bluetrap6;
  949 #ifdef __GNUCLIKE_ASM
  950 __asm
  951 ("                                                                      \n\
  952         .text                                                           \n\
  953         .p2align 2,0x90                                                 \n\
  954         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
  955 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
  956         ss                                                              \n\
  957         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  958         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  959         iret                                                            \n\
  960 ");
  961 #endif
  962 
  963 /*
  964  * Special exception 13 handler.
  965  * Accessing non-existent MSR generates general protection fault.
  966  */
  967 inthand_t       bluetrap13;
  968 #ifdef __GNUCLIKE_ASM
  969 __asm
  970 ("                                                                      \n\
  971         .text                                                           \n\
  972         .p2align 2,0x90                                                 \n\
  973         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
  974 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
  975         ss                                                              \n\
  976         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  977         popl    %eax            /* discard error code */                \n\
  978         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  979         iret                                                            \n\
  980 ");
  981 #endif
  982 
  983 /*
  984  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
  985  * support cpuid instruction.  This function should be called after
  986  * loading interrupt descriptor table register.
  987  *
  988  * I don't like this method that handles fault, but I couldn't get
  989  * information for any other methods.  Does blue giant know?
  990  */
  991 static int
  992 identblue(void)
  993 {
  994 
  995         trap_by_rdmsr = 0;
  996 
  997         /*
  998          * Cyrix 486-class CPU does not support rdmsr instruction.
  999          * The rdmsr instruction generates invalid opcode fault, and exception
 1000          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
 1001          * bluetrap6() set the magic number to trap_by_rdmsr.
 1002          */
 1003         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
 1004             GSEL(GCODE_SEL, SEL_KPL));
 1005 
 1006         /*
 1007          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
 1008          * In this case, rdmsr generates general protection fault, and
 1009          * exception will be trapped by bluetrap13().
 1010          */
 1011         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
 1012             GSEL(GCODE_SEL, SEL_KPL));
 1013 
 1014         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 1015 
 1016         if (trap_by_rdmsr == 0xa8c1d)
 1017                 return IDENTBLUE_CYRIX486;
 1018         else if (trap_by_rdmsr == 0xa89c4)
 1019                 return IDENTBLUE_CYRIXM2;
 1020         return IDENTBLUE_IBMCPU;
 1021 }
 1022 
 1023 
 1024 /*
 1025  * identifycyrix() set lower 16 bits of cyrix_did as follows:
 1026  *
 1027  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
 1028  * +-------+-------+---------------+
 1029  * |  SID  |  RID  |   Device ID   |
 1030  * |    (DIR 1)    |    (DIR 0)    |
 1031  * +-------+-------+---------------+
 1032  */
 1033 static void
 1034 identifycyrix(void)
 1035 {
 1036         u_int   eflags;
 1037         int     ccr2_test = 0, dir_test = 0;
 1038         u_char  ccr2, ccr3;
 1039 
 1040         eflags = read_eflags();
 1041         disable_intr();
 1042 
 1043         ccr2 = read_cyrix_reg(CCR2);
 1044         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
 1045         read_cyrix_reg(CCR2);
 1046         if (read_cyrix_reg(CCR2) != ccr2)
 1047                 ccr2_test = 1;
 1048         write_cyrix_reg(CCR2, ccr2);
 1049 
 1050         ccr3 = read_cyrix_reg(CCR3);
 1051         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
 1052         read_cyrix_reg(CCR3);
 1053         if (read_cyrix_reg(CCR3) != ccr3)
 1054                 dir_test = 1;                                   /* CPU supports DIRs. */
 1055         write_cyrix_reg(CCR3, ccr3);
 1056 
 1057         if (dir_test) {
 1058                 /* Device ID registers are available. */
 1059                 cyrix_did = read_cyrix_reg(DIR1) << 8;
 1060                 cyrix_did += read_cyrix_reg(DIR0);
 1061         } else if (ccr2_test)
 1062                 cyrix_did = 0x0010;             /* 486S A-step */
 1063         else
 1064                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
 1065 
 1066         write_eflags(eflags);
 1067 }
 1068 
 1069 /*
 1070  * Final stage of CPU identification. -- Should I check TI?
 1071  */
 1072 void
 1073 finishidentcpu(void)
 1074 {
 1075         int     isblue = 0;
 1076         u_char  ccr3;
 1077         u_int   regs[4];
 1078 
 1079         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 1080                 if (cpu == CPU_486) {
 1081                         /*
 1082                          * These conditions are equivalent to:
 1083                          *     - CPU does not support cpuid instruction.
 1084                          *     - Cyrix/IBM CPU is detected.
 1085                          */
 1086                         isblue = identblue();
 1087                         if (isblue == IDENTBLUE_IBMCPU) {
 1088                                 strcpy(cpu_vendor, "IBM");
 1089                                 cpu = CPU_BLUE;
 1090                                 return;
 1091                         }
 1092                 }
 1093                 switch (cpu_id & 0xf00) {
 1094                 case 0x600:
 1095                         /*
 1096                          * Cyrix's datasheet does not describe DIRs.
 1097                          * Therefor, I assume it does not have them
 1098                          * and use the result of the cpuid instruction.
 1099                          * XXX they seem to have it for now at least. -Peter
 1100                          */
 1101                         identifycyrix();
 1102                         cpu = CPU_M2;
 1103                         break;
 1104                 default:
 1105                         identifycyrix();
 1106                         /*
 1107                          * This routine contains a trick.
 1108                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 1109                          */
 1110                         switch (cyrix_did & 0x00f0) {
 1111                         case 0x00:
 1112                         case 0xf0:
 1113                                 cpu = CPU_486DLC;
 1114                                 break;
 1115                         case 0x10:
 1116                                 cpu = CPU_CY486DX;
 1117                                 break;
 1118                         case 0x20:
 1119                                 if ((cyrix_did & 0x000f) < 8)
 1120                                         cpu = CPU_M1;
 1121                                 else
 1122                                         cpu = CPU_M1SC;
 1123                                 break;
 1124                         case 0x30:
 1125                                 cpu = CPU_M1;
 1126                                 break;
 1127                         case 0x40:
 1128                                 /* MediaGX CPU */
 1129                                 cpu = CPU_M1SC;
 1130                                 break;
 1131                         default:
 1132                                 /* M2 and later CPUs are treated as M2. */
 1133                                 cpu = CPU_M2;
 1134 
 1135                                 /*
 1136                                  * enable cpuid instruction.
 1137                                  */
 1138                                 ccr3 = read_cyrix_reg(CCR3);
 1139                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 1140                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 1141                                 write_cyrix_reg(CCR3, ccr3);
 1142 
 1143                                 do_cpuid(0, regs);
 1144                                 cpu_high = regs[0];     /* eax */
 1145                                 do_cpuid(1, regs);
 1146                                 cpu_id = regs[0];       /* eax */
 1147                                 cpu_feature = regs[3];  /* edx */
 1148                                 break;
 1149                         }
 1150                 }
 1151         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 1152                 /*
 1153                  * There are BlueLightning CPUs that do not change
 1154                  * undefined flags by dividing 5 by 2.  In this case,
 1155                  * the CPU identification routine in locore.s leaves
 1156                  * cpu_vendor null string and puts CPU_486 into the
 1157                  * cpu.
 1158                  */
 1159                 isblue = identblue();
 1160                 if (isblue == IDENTBLUE_IBMCPU) {
 1161                         strcpy(cpu_vendor, "IBM");
 1162                         cpu = CPU_BLUE;
 1163                         return;
 1164                 }
 1165         }
 1166 }
 1167 
 1168 static void
 1169 print_AMD_assoc(int i)
 1170 {
 1171         if (i == 255)
 1172                 printf(", fully associative\n");
 1173         else
 1174                 printf(", %d-way associative\n", i);
 1175 }
 1176 
 1177 static void
 1178 print_AMD_info(void)
 1179 {
 1180         quad_t amd_whcr;
 1181 
 1182         if (cpu_exthigh >= 0x80000005) {
 1183                 u_int regs[4];
 1184 
 1185                 do_cpuid(0x80000005, regs);
 1186                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
 1187                 print_AMD_assoc(regs[1] >> 24);
 1188                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
 1189                 print_AMD_assoc((regs[1] >> 8) & 0xff);
 1190                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
 1191                 printf(", %d bytes/line", regs[2] & 0xff);
 1192                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 1193                 print_AMD_assoc((regs[2] >> 16) & 0xff);
 1194                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 1195                 printf(", %d bytes/line", regs[3] & 0xff);
 1196                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 1197                 print_AMD_assoc((regs[3] >> 16) & 0xff);
 1198                 if (cpu_exthigh >= 0x80000006) {        /* K6-III only */
 1199                         do_cpuid(0x80000006, regs);
 1200                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
 1201                         printf(", %d bytes/line", regs[2] & 0xff);
 1202                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 1203                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
 1204                 }
 1205         }
 1206         if (((cpu_id & 0xf00) == 0x500)
 1207             && (((cpu_id & 0x0f0) > 0x80)
 1208                 || (((cpu_id & 0x0f0) == 0x80)
 1209                     && (cpu_id & 0x00f) > 0x07))) {
 1210                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
 1211                 amd_whcr = rdmsr(0xc0000082);
 1212                 if (!(amd_whcr & (0x3ff << 22))) {
 1213                         printf("Write Allocate Disable\n");
 1214                 } else {
 1215                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1216                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
 1217                         printf("Write Allocate 15-16M bytes: %s\n",
 1218                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
 1219                 }
 1220         } else if (((cpu_id & 0xf00) == 0x500)
 1221                    && ((cpu_id & 0x0f0) > 0x50)) {
 1222                 /* K6, K6-2(old core) */
 1223                 amd_whcr = rdmsr(0xc0000082);
 1224                 if (!(amd_whcr & (0x7f << 1))) {
 1225                         printf("Write Allocate Disable\n");
 1226                 } else {
 1227                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1228                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
 1229                         printf("Write Allocate 15-16M bytes: %s\n",
 1230                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
 1231                         printf("Hardware Write Allocate Control: %s\n",
 1232                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
 1233                 }
 1234         }
 1235 }
 1236 
 1237 static void
 1238 print_transmeta_info()
 1239 {
 1240         u_int regs[4], nreg = 0;
 1241 
 1242         do_cpuid(0x80860000, regs);
 1243         nreg = regs[0];
 1244         if (nreg >= 0x80860001) {
 1245                 do_cpuid(0x80860001, regs);
 1246                 printf("  Processor revision %u.%u.%u.%u\n",
 1247                        (regs[1] >> 24) & 0xff,
 1248                        (regs[1] >> 16) & 0xff,
 1249                        (regs[1] >> 8) & 0xff,
 1250                        regs[1] & 0xff);
 1251         }
 1252         if (nreg >= 0x80860002) {
 1253                 do_cpuid(0x80860002, regs);
 1254                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
 1255                        (regs[1] >> 24) & 0xff,
 1256                        (regs[1] >> 16) & 0xff,
 1257                        (regs[1] >> 8) & 0xff,
 1258                        regs[1] & 0xff,
 1259                        regs[2]);
 1260         }
 1261         if (nreg >= 0x80860006) {
 1262                 char info[65];
 1263                 do_cpuid(0x80860003, (u_int*) &info[0]);
 1264                 do_cpuid(0x80860004, (u_int*) &info[16]);
 1265                 do_cpuid(0x80860005, (u_int*) &info[32]);
 1266                 do_cpuid(0x80860006, (u_int*) &info[48]);
 1267                 info[64] = 0;
 1268                 printf("  %s\n", info);
 1269         }
 1270 }

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