Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/i386/identcpu.c
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1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/md_var.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 63 #define IDENTBLUE_CYRIX486 0 64 #define IDENTBLUE_IBMCPU 1 65 #define IDENTBLUE_CYRIXM2 2 66 67 /* XXX - should be in header file: */ 68 void printcpuinfo(void); 69 void finishidentcpu(void); 70 void earlysetcpuclass(void); 71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 72 void enable_K5_wt_alloc(void); 73 void enable_K6_wt_alloc(void); 74 void enable_K6_2_wt_alloc(void); 75 #endif 76 void panicifcpuunsupported(void); 77 78 static void identifycyrix(void); 79 static void init_exthigh(void); 80 void setPQL2(int *const size, int *const ways); 81 static void setPQL2_AMD(int *const size, int *const ways); 82 static void setPQL2_INTEL(int *const size, int *const ways); 83 static void get_INTEL_TLB(u_int data, int *const size, int *const ways); 84 static void print_AMD_info(void); 85 static void print_INTEL_info(void); 86 static void print_INTEL_TLB(u_int data); 87 static void print_AMD_assoc(int i); 88 static void print_transmeta_info(void); 89 90 int cpu_class; 91 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 92 u_int cyrix_did; /* Device ID of Cyrix CPU */ 93 char machine[] = MACHINE; 94 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 95 machine, 0, "Machine class"); 96 97 static char cpu_model[128]; 98 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 99 cpu_model, 0, "Machine model"); 100 101 static int hw_clockrate; 102 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 103 &hw_clockrate, 0, "CPU instruction clock rate"); 104 105 static char cpu_brand[48]; 106 107 #define MAX_BRAND_INDEX 8 108 109 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 110 NULL, /* No brand */ 111 "Intel Celeron", 112 "Intel Pentium III", 113 "Intel Pentium III Xeon", 114 NULL, 115 NULL, 116 NULL, 117 NULL, 118 "Intel Pentium 4" 119 }; 120 121 static struct { 122 char *cpu_name; 123 int cpu_class; 124 } i386_cpus[] = { 125 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 126 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 127 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 128 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 129 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 130 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 131 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 132 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 133 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 134 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 135 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 136 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 137 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 138 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 139 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 140 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 141 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 142 }; 143 144 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 145 int has_f00f_bug = 0; /* Initialized so that it can be patched. */ 146 #endif 147 148 static void 149 init_exthigh(void) 150 { 151 static int done = 0; 152 u_int regs[4]; 153 154 if (done == 0) { 155 if (cpu_high > 0 && 156 (strcmp(cpu_vendor, "GenuineIntel") == 0 || 157 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 158 strcmp(cpu_vendor, "GenuineTMx86") == 0 || 159 strcmp(cpu_vendor, "TransmetaCPU") == 0 || 160 strcmp(cpu_vendor, "Geode by NSC") == 0)) { 161 do_cpuid(0x80000000, regs); 162 if (regs[0] >= 0x80000000) 163 cpu_exthigh = regs[0]; 164 } 165 166 done = 1; 167 } 168 } 169 170 void 171 printcpuinfo(void) 172 { 173 u_int regs[4], i; 174 char *brand; 175 176 cpu_class = i386_cpus[cpu].cpu_class; 177 printf("CPU: "); 178 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); 179 180 /* Check for extended CPUID information and a processor name. */ 181 init_exthigh(); 182 if (cpu_exthigh >= 0x80000004) { 183 brand = cpu_brand; 184 for (i = 0x80000002; i < 0x80000005; i++) { 185 do_cpuid(i, regs); 186 memcpy(brand, regs, sizeof(regs)); 187 brand += sizeof(regs); 188 } 189 } 190 191 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 192 if ((cpu_id & 0xf00) > 0x300) { 193 u_int brand_index; 194 u_int model; 195 196 cpu_model[0] = '\0'; 197 198 switch (cpu_id & 0x3000) { 199 case 0x1000: 200 strcpy(cpu_model, "Overdrive "); 201 break; 202 case 0x2000: 203 strcpy(cpu_model, "Dual "); 204 break; 205 } 206 207 switch (cpu_id & 0xf00) { 208 case 0x400: 209 strcat(cpu_model, "i486 "); 210 /* Check the particular flavor of 486 */ 211 switch (cpu_id & 0xf0) { 212 case 0x00: 213 case 0x10: 214 strcat(cpu_model, "DX"); 215 break; 216 case 0x20: 217 strcat(cpu_model, "SX"); 218 break; 219 case 0x30: 220 strcat(cpu_model, "DX2"); 221 break; 222 case 0x40: 223 strcat(cpu_model, "SL"); 224 break; 225 case 0x50: 226 strcat(cpu_model, "SX2"); 227 break; 228 case 0x70: 229 strcat(cpu_model, 230 "DX2 Write-Back Enhanced"); 231 break; 232 case 0x80: 233 strcat(cpu_model, "DX4"); 234 break; 235 } 236 break; 237 case 0x500: 238 /* Check the particular flavor of 586 */ 239 strcat(cpu_model, "Pentium"); 240 switch (cpu_id & 0xf0) { 241 case 0x00: 242 strcat(cpu_model, " A-step"); 243 break; 244 case 0x10: 245 strcat(cpu_model, "/P5"); 246 break; 247 case 0x20: 248 strcat(cpu_model, "/P54C"); 249 break; 250 case 0x30: 251 strcat(cpu_model, "/P54T Overdrive"); 252 break; 253 case 0x40: 254 strcat(cpu_model, "/P55C"); 255 break; 256 case 0x70: 257 strcat(cpu_model, "/P54C"); 258 break; 259 case 0x80: 260 strcat(cpu_model, "/P55C (quarter-micron)"); 261 break; 262 default: 263 /* nothing */ 264 break; 265 } 266 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 267 /* 268 * XXX - If/when Intel fixes the bug, this 269 * should also check the version of the 270 * CPU, not just that it's a Pentium. 271 */ 272 has_f00f_bug = 1; 273 #endif 274 break; 275 case 0x600: 276 /* Check the particular flavor of 686 */ 277 switch (cpu_id & 0xf0) { 278 case 0x00: 279 strcat(cpu_model, "Pentium Pro A-step"); 280 break; 281 case 0x10: 282 strcat(cpu_model, "Pentium Pro"); 283 break; 284 case 0x30: 285 case 0x50: 286 case 0x60: 287 strcat(cpu_model, 288 "Pentium II/Pentium II Xeon/Celeron"); 289 cpu = CPU_PII; 290 break; 291 case 0x70: 292 case 0x80: 293 case 0xa0: 294 case 0xb0: 295 strcat(cpu_model, 296 "Pentium III/Pentium III Xeon/Celeron"); 297 cpu = CPU_PIII; 298 break; 299 default: 300 strcat(cpu_model, "Unknown 80686"); 301 break; 302 } 303 break; 304 case 0xf00: 305 strcat(cpu_model, "Pentium 4"); 306 cpu = CPU_P4; 307 model = (cpu_id & 0x0f0) >> 4; 308 if (model == 3 || model == 4 || model == 6) { 309 uint64_t tmp; 310 311 tmp = rdmsr(MSR_IA32_MISC_ENABLE); 312 wrmsr(MSR_IA32_MISC_ENABLE, 313 tmp & ~(1LL << 22)); 314 do_cpuid(0, regs); 315 cpu_high = regs[0]; 316 } 317 break; 318 default: 319 strcat(cpu_model, "unknown"); 320 break; 321 } 322 323 /* 324 * If we didn't get a brand name from the extended 325 * CPUID, try to look it up in the brand table. 326 */ 327 if (cpu_high > 0 && *cpu_brand == '\0') { 328 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 329 if (brand_index <= MAX_BRAND_INDEX && 330 cpu_brandtable[brand_index] != NULL) 331 strcpy(cpu_brand, 332 cpu_brandtable[brand_index]); 333 } 334 } 335 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 336 /* 337 * Values taken from AMD Processor Recognition 338 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 339 * (also describes ``Features'' encodings. 340 */ 341 strcpy(cpu_model, "AMD "); 342 switch (cpu_id & 0xFF0) { 343 case 0x410: 344 strcat(cpu_model, "Standard Am486DX"); 345 break; 346 case 0x430: 347 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 348 break; 349 case 0x470: 350 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 351 break; 352 case 0x480: 353 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 354 break; 355 case 0x490: 356 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 357 break; 358 case 0x4E0: 359 strcat(cpu_model, "Am5x86 Write-Through"); 360 break; 361 case 0x4F0: 362 strcat(cpu_model, "Am5x86 Write-Back"); 363 break; 364 case 0x500: 365 strcat(cpu_model, "K5 model 0"); 366 tsc_is_broken = 1; 367 break; 368 case 0x510: 369 strcat(cpu_model, "K5 model 1"); 370 break; 371 case 0x520: 372 strcat(cpu_model, "K5 PR166 (model 2)"); 373 break; 374 case 0x530: 375 strcat(cpu_model, "K5 PR200 (model 3)"); 376 break; 377 case 0x560: 378 strcat(cpu_model, "K6"); 379 break; 380 case 0x570: 381 strcat(cpu_model, "K6 266 (model 1)"); 382 break; 383 case 0x580: 384 strcat(cpu_model, "K6-2"); 385 break; 386 case 0x590: 387 strcat(cpu_model, "K6-III"); 388 break; 389 case 0x5a0: 390 strcat(cpu_model, "Geode LX"); 391 /* 392 * Make sure the TSC runs through suspension, 393 * otherwise we can't use it as timecounter 394 */ 395 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 396 break; 397 default: 398 strcat(cpu_model, "Unknown"); 399 break; 400 } 401 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 402 if ((cpu_id & 0xf00) == 0x500) { 403 if (((cpu_id & 0x0f0) > 0) 404 && ((cpu_id & 0x0f0) < 0x60) 405 && ((cpu_id & 0x00f) > 3)) 406 enable_K5_wt_alloc(); 407 else if (((cpu_id & 0x0f0) > 0x80) 408 || (((cpu_id & 0x0f0) == 0x80) 409 && (cpu_id & 0x00f) > 0x07)) 410 enable_K6_2_wt_alloc(); 411 else if ((cpu_id & 0x0f0) > 0x50) 412 enable_K6_wt_alloc(); 413 } 414 #endif 415 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 416 strcpy(cpu_model, "Cyrix "); 417 switch (cpu_id & 0xff0) { 418 case 0x440: 419 strcat(cpu_model, "MediaGX"); 420 break; 421 case 0x520: 422 strcat(cpu_model, "6x86"); 423 break; 424 case 0x540: 425 cpu_class = CPUCLASS_586; 426 strcat(cpu_model, "GXm"); 427 break; 428 case 0x600: 429 strcat(cpu_model, "6x86MX"); 430 break; 431 default: 432 /* 433 * Even though CPU supports the cpuid 434 * instruction, it can be disabled. 435 * Therefore, this routine supports all Cyrix 436 * CPUs. 437 */ 438 switch (cyrix_did & 0xf0) { 439 case 0x00: 440 switch (cyrix_did & 0x0f) { 441 case 0x00: 442 strcat(cpu_model, "486SLC"); 443 break; 444 case 0x01: 445 strcat(cpu_model, "486DLC"); 446 break; 447 case 0x02: 448 strcat(cpu_model, "486SLC2"); 449 break; 450 case 0x03: 451 strcat(cpu_model, "486DLC2"); 452 break; 453 case 0x04: 454 strcat(cpu_model, "486SRx"); 455 break; 456 case 0x05: 457 strcat(cpu_model, "486DRx"); 458 break; 459 case 0x06: 460 strcat(cpu_model, "486SRx2"); 461 break; 462 case 0x07: 463 strcat(cpu_model, "486DRx2"); 464 break; 465 case 0x08: 466 strcat(cpu_model, "486SRu"); 467 break; 468 case 0x09: 469 strcat(cpu_model, "486DRu"); 470 break; 471 case 0x0a: 472 strcat(cpu_model, "486SRu2"); 473 break; 474 case 0x0b: 475 strcat(cpu_model, "486DRu2"); 476 break; 477 default: 478 strcat(cpu_model, "Unknown"); 479 break; 480 } 481 break; 482 case 0x10: 483 switch (cyrix_did & 0x0f) { 484 case 0x00: 485 strcat(cpu_model, "486S"); 486 break; 487 case 0x01: 488 strcat(cpu_model, "486S2"); 489 break; 490 case 0x02: 491 strcat(cpu_model, "486Se"); 492 break; 493 case 0x03: 494 strcat(cpu_model, "486S2e"); 495 break; 496 case 0x0a: 497 strcat(cpu_model, "486DX"); 498 break; 499 case 0x0b: 500 strcat(cpu_model, "486DX2"); 501 break; 502 case 0x0f: 503 strcat(cpu_model, "486DX4"); 504 break; 505 default: 506 strcat(cpu_model, "Unknown"); 507 break; 508 } 509 break; 510 case 0x20: 511 if ((cyrix_did & 0x0f) < 8) 512 strcat(cpu_model, "6x86"); /* Where did you get it? */ 513 else 514 strcat(cpu_model, "5x86"); 515 break; 516 case 0x30: 517 strcat(cpu_model, "6x86"); 518 break; 519 case 0x40: 520 if ((cyrix_did & 0xf000) == 0x3000) { 521 cpu_class = CPUCLASS_586; 522 strcat(cpu_model, "GXm"); 523 } else 524 strcat(cpu_model, "MediaGX"); 525 break; 526 case 0x50: 527 strcat(cpu_model, "6x86MX"); 528 break; 529 case 0xf0: 530 switch (cyrix_did & 0x0f) { 531 case 0x0d: 532 strcat(cpu_model, "Overdrive CPU"); 533 break; 534 case 0x0e: 535 strcpy(cpu_model, "Texas Instruments 486SXL"); 536 break; 537 case 0x0f: 538 strcat(cpu_model, "486SLC/DLC"); 539 break; 540 default: 541 strcat(cpu_model, "Unknown"); 542 break; 543 } 544 break; 545 default: 546 strcat(cpu_model, "Unknown"); 547 break; 548 } 549 break; 550 } 551 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) { 552 strcpy(cpu_model, "Rise "); 553 switch (cpu_id & 0xff0) { 554 case 0x500: 555 strcat(cpu_model, "mP6"); 556 break; 557 default: 558 strcat(cpu_model, "Unknown"); 559 } 560 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { 561 switch (cpu_id & 0xff0) { 562 case 0x540: 563 strcpy(cpu_model, "IDT WinChip C6"); 564 tsc_is_broken = 1; 565 break; 566 case 0x580: 567 strcpy(cpu_model, "IDT WinChip 2"); 568 break; 569 case 0x660: 570 strcpy(cpu_model, "VIA C3 Samuel"); 571 break; 572 case 0x670: 573 if (cpu_id & 0x8) 574 strcpy(cpu_model, "VIA C3 Ezra"); 575 else 576 strcpy(cpu_model, "VIA C3 Samuel 2"); 577 break; 578 case 0x680: 579 strcpy(cpu_model, "VIA C3 Ezra-T"); 580 break; 581 case 0x690: 582 strcpy(cpu_model, "VIA C3 Nehemiah"); 583 if ((cpu_id & 0xf) < 3) 584 break; 585 goto via_common; 586 case 0x6a0: 587 strcpy(cpu_model, "VIA C7 Esther"); 588 via_common: 589 do_cpuid(0xc0000000, regs); 590 i = regs[0]; 591 if (i >= 0xC0000001) { 592 do_cpuid(0xc0000001, regs); 593 i = regs[3]; 594 } else 595 i = 0; 596 if (i & VIA_CPUID_HAS_RNG) 597 strcat(cpu_model, "+RNG"); 598 if (i & VIA_CPUID_HAS_ACE) 599 strcat(cpu_model, "+AES"); 600 if (i & VIA_CPUID_HAS_ACE2) 601 strcat(cpu_model, "+AES-CTR"); 602 if (i & VIA_CPUID_HAS_PHE) 603 strcat(cpu_model, "+SHA1+SHA256"); 604 if (i & VIA_CPUID_HAS_PMM) 605 strcat(cpu_model, "+RSA"); 606 break; 607 default: 608 strcpy(cpu_model, "VIA/IDT Unknown"); 609 } 610 } else if (strcmp(cpu_vendor, "IBM") == 0) { 611 strcpy(cpu_model, "Blue Lightning CPU"); 612 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) { 613 switch (cpu_id & 0xfff) { 614 case 0x540: 615 strcpy(cpu_model, "Geode SC1100"); 616 cpu = CPU_GEODE1100; 617 tsc_is_broken = 1; 618 break; 619 default: 620 strcpy(cpu_model, "Geode/NSC unknown"); 621 break; 622 } 623 } 624 625 /* 626 * Replace cpu_model with cpu_brand minus leading spaces if 627 * we have one. 628 */ 629 brand = cpu_brand; 630 while (*brand == ' ') 631 ++brand; 632 if (*brand != '\0') 633 strcpy(cpu_model, brand); 634 635 printf("%s (", cpu_model); 636 switch(cpu_class) { 637 case CPUCLASS_286: 638 printf("286"); 639 break; 640 case CPUCLASS_386: 641 printf("386"); 642 break; 643 #if defined(I486_CPU) 644 case CPUCLASS_486: 645 printf("486"); 646 bzero_vector = i486_bzero; 647 break; 648 #endif 649 #if defined(I586_CPU) 650 case CPUCLASS_586: 651 hw_clockrate = (tsc_freq + 5000) / 1000000; 652 printf("%jd.%02d-MHz ", 653 (intmax_t)(tsc_freq + 4999) / 1000000, 654 (u_int)((tsc_freq + 4999) / 10000) % 100); 655 printf("586"); 656 break; 657 #endif 658 #if defined(I686_CPU) 659 case CPUCLASS_686: 660 hw_clockrate = (tsc_freq + 5000) / 1000000; 661 printf("%jd.%02d-MHz ", 662 (intmax_t)(tsc_freq + 4999) / 1000000, 663 (u_int)((tsc_freq + 4999) / 10000) % 100); 664 printf("686"); 665 break; 666 #endif 667 default: 668 printf("Unknown"); /* will panic below... */ 669 } 670 printf("-class CPU)\n"); 671 if(*cpu_vendor) 672 printf(" Origin = \"%s\"",cpu_vendor); 673 if(cpu_id) 674 printf(" Id = 0x%x", cpu_id); 675 676 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 677 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 678 strcmp(cpu_vendor, "GenuineTMx86") == 0 || 679 strcmp(cpu_vendor, "TransmetaCPU") == 0 || 680 strcmp(cpu_vendor, "RiseRiseRise") == 0 || 681 strcmp(cpu_vendor, "CentaurHauls") == 0 || 682 strcmp(cpu_vendor, "Geode by NSC") == 0 || 683 ((strcmp(cpu_vendor, "CyrixInstead") == 0) && 684 ((cpu_id & 0xf00) > 0x500))) { 685 printf(" Stepping = %u", cpu_id & 0xf); 686 if (strcmp(cpu_vendor, "CyrixInstead") == 0) 687 printf(" DIR=0x%04x", cyrix_did); 688 if (cpu_high > 0) { 689 u_int cmp = 1, htt = 1; 690 691 /* 692 * Here we should probably set up flags indicating 693 * whether or not various features are available. 694 * The interesting ones are probably VME, PSE, PAE, 695 * and PGE. The code already assumes without bothering 696 * to check that all CPUs >= Pentium have a TSC and 697 * MSRs. 698 */ 699 printf("\n Features=0x%b", cpu_feature, 700 "\020" 701 "\001FPU" /* Integral FPU */ 702 "\002VME" /* Extended VM86 mode support */ 703 "\003DE" /* Debugging Extensions (CR4.DE) */ 704 "\004PSE" /* 4MByte page tables */ 705 "\005TSC" /* Timestamp counter */ 706 "\006MSR" /* Machine specific registers */ 707 "\007PAE" /* Physical address extension */ 708 "\010MCE" /* Machine Check support */ 709 "\011CX8" /* CMPEXCH8 instruction */ 710 "\012APIC" /* SMP local APIC */ 711 "\013oldMTRR" /* Previous implementation of MTRR */ 712 "\014SEP" /* Fast System Call */ 713 "\015MTRR" /* Memory Type Range Registers */ 714 "\016PGE" /* PG_G (global bit) support */ 715 "\017MCA" /* Machine Check Architecture */ 716 "\020CMOV" /* CMOV instruction */ 717 "\021PAT" /* Page attributes table */ 718 "\022PSE36" /* 36 bit address space support */ 719 "\023PN" /* Processor Serial number */ 720 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 721 "\025<b20>" 722 "\026DTS" /* Debug Trace Store */ 723 "\027ACPI" /* ACPI support */ 724 "\030MMX" /* MMX instructions */ 725 "\031FXSR" /* FXSAVE/FXRSTOR */ 726 "\032SSE" /* Streaming SIMD Extensions */ 727 "\033SSE2" /* Streaming SIMD Extensions #2 */ 728 "\034SS" /* Self snoop */ 729 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 730 "\036TM" /* Thermal Monitor clock slowdown */ 731 "\037IA64" /* CPU can execute IA64 instructions */ 732 "\040PBE" /* Pending Break Enable */ 733 ); 734 735 if (cpu_feature2 != 0) { 736 printf("\n Features2=0x%b", cpu_feature2, 737 "\020" 738 "\001SSE3" /* SSE3 */ 739 "\002<b1>" 740 "\003RSVD2" /* "Reserved" bit 2 */ 741 "\004MON" /* MONITOR/MWAIT Instructions */ 742 "\005DS_CPL" /* CPL Qualified Debug Store */ 743 "\006VMX" /* Virtual Machine Extensions */ 744 "\007SMX" /* Safer Mode Extensions */ 745 "\010EST" /* Enhanced SpeedStep */ 746 "\011TM2" /* Thermal Monitor 2 */ 747 "\012SSSE3" /* SSSE3 */ 748 "\013CNXT-ID" /* L1 context ID available */ 749 "\014<b11>" 750 "\015<b12>" 751 "\016CX16" /* CMPXCHG16B Instruction */ 752 "\017xTPR" /* Send Task Priority Messages*/ 753 "\020PDCM" /* Perf/Debug Capability MSR */ 754 "\021<b16>" 755 "\022<b17>" 756 "\023DCA" /* Direct Cache Access */ 757 "\024<b19>" 758 "\025<b20>" 759 "\026<b21>" 760 "\027<b22>" 761 "\030<b23>" 762 "\031<b24>" 763 "\032<b25>" 764 "\033<b26>" 765 "\034<b27>" 766 "\035<b28>" 767 "\036<b29>" 768 "\037<b30>" 769 "\040<b31>" 770 ); 771 } 772 773 /* 774 * AMD64 Architecture Programmer's Manual Volume 3: 775 * General-Purpose and System Instructions 776 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 777 * 778 * IA-32 Intel Architecture Software Developer's Manual, 779 * Volume 2A: Instruction Set Reference, A-M 780 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 781 */ 782 if (amd_feature != 0) { 783 printf("\n AMD Features=0x%b", amd_feature, 784 "\020" /* in hex */ 785 "\001<s0>" /* Same */ 786 "\002<s1>" /* Same */ 787 "\003<s2>" /* Same */ 788 "\004<s3>" /* Same */ 789 "\005<s4>" /* Same */ 790 "\006<s5>" /* Same */ 791 "\007<s6>" /* Same */ 792 "\010<s7>" /* Same */ 793 "\011<s8>" /* Same */ 794 "\012<s9>" /* Same */ 795 "\013<b10>" /* Undefined */ 796 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 797 "\015<s12>" /* Same */ 798 "\016<s13>" /* Same */ 799 "\017<s14>" /* Same */ 800 "\020<s15>" /* Same */ 801 "\021<s16>" /* Same */ 802 "\022<s17>" /* Same */ 803 "\023<b18>" /* Reserved, unknown */ 804 "\024MP" /* Multiprocessor Capable */ 805 "\025NX" /* Has EFER.NXE, NX */ 806 "\026<b21>" /* Undefined */ 807 "\027MMX+" /* AMD MMX Extensions */ 808 "\030<s23>" /* Same */ 809 "\031<s24>" /* Same */ 810 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 811 "\033<b26>" /* Undefined */ 812 "\034RDTSCP" /* RDTSCP */ 813 "\035<b28>" /* Undefined */ 814 "\036LM" /* 64 bit long mode */ 815 "\0373DNow!+" /* AMD 3DNow! Extensions */ 816 "\0403DNow!" /* AMD 3DNow! */ 817 ); 818 } 819 820 if (amd_feature2 != 0) { 821 printf("\n AMD Features2=0x%b", amd_feature2, 822 "\020" 823 "\001LAHF" /* LAHF/SAHF in long mode */ 824 "\002CMP" /* CMP legacy */ 825 "\003SVM" /* Secure Virtual Mode */ 826 "\004ExtAPIC" /* Extended APIC register */ 827 "\005CR8" /* CR8 in legacy mode */ 828 "\006<b5>" 829 "\007<b6>" 830 "\010<b7>" 831 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 832 "\012<b9>" 833 "\013<b10>" 834 "\014<b11>" 835 "\015<b12>" 836 "\016<b13>" 837 "\017<b14>" 838 "\020<b15>" 839 "\021<b16>" 840 "\022<b17>" 841 "\023<b18>" 842 "\024<b19>" 843 "\025<b20>" 844 "\026<b21>" 845 "\027<b22>" 846 "\030<b23>" 847 "\031<b24>" 848 "\032<b25>" 849 "\033<b26>" 850 "\034<b27>" 851 "\035<b28>" 852 "\036<b29>" 853 "\037<b30>" 854 "\040<b31>" 855 ); 856 } 857 858 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, 859 "AuthenticAMD") == 0) 860 cpu_feature &= ~CPUID_HTT; 861 862 /* 863 * If this CPU supports HTT or CMP then mention the 864 * number of physical/logical cores it contains. 865 */ 866 if (cpu_feature & CPUID_HTT) 867 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 868 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 869 (amd_feature2 & AMDID2_CMP)) 870 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 871 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 872 (cpu_high >= 4)) { 873 cpuid_count(4, 0, regs); 874 if ((regs[0] & 0x1f) != 0) 875 cmp = ((regs[0] >> 26) & 0x3f) + 1; 876 } 877 if (cmp > 1) 878 printf("\n Cores per package: %d", cmp); 879 if ((htt / cmp) > 1) 880 printf("\n Logical CPUs per core: %d", 881 htt / cmp); 882 } 883 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 884 printf(" DIR=0x%04x", cyrix_did); 885 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 886 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 887 #ifndef CYRIX_CACHE_REALLY_WORKS 888 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 889 printf("\n CPU cache: write-through mode"); 890 #endif 891 } 892 /* Avoid ugly blank lines: only print newline when we have to. */ 893 if (*cpu_vendor || cpu_id) 894 printf("\n"); 895 896 if (!bootverbose) 897 return; 898 899 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 900 print_AMD_info(); 901 else if (strcmp(cpu_vendor, "GenuineIntel") == 0) 902 print_INTEL_info(); 903 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 || 904 strcmp(cpu_vendor, "TransmetaCPU") == 0) 905 print_transmeta_info(); 906 } 907 908 void 909 panicifcpuunsupported(void) 910 { 911 912 #if !defined(lint) 913 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 914 #error This kernel is not configured for one of the supported CPUs 915 #endif 916 #else /* lint */ 917 #endif /* lint */ 918 /* 919 * Now that we have told the user what they have, 920 * let them know if that machine type isn't configured. 921 */ 922 switch (cpu_class) { 923 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 924 case CPUCLASS_386: 925 #if !defined(I486_CPU) 926 case CPUCLASS_486: 927 #endif 928 #if !defined(I586_CPU) 929 case CPUCLASS_586: 930 #endif 931 #if !defined(I686_CPU) 932 case CPUCLASS_686: 933 #endif 934 panic("CPU class not configured"); 935 default: 936 break; 937 } 938 } 939 940 941 static volatile u_int trap_by_rdmsr; 942 943 /* 944 * Special exception 6 handler. 945 * The rdmsr instruction generates invalid opcodes fault on 486-class 946 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 947 * function identblue() when this handler is called. Stacked eip should 948 * be advanced. 949 */ 950 inthand_t bluetrap6; 951 #ifdef __GNUCLIKE_ASM 952 __asm 953 (" \n\ 954 .text \n\ 955 .p2align 2,0x90 \n\ 956 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 957 " __XSTRING(CNAME(bluetrap6)) ": \n\ 958 ss \n\ 959 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 960 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 961 iret \n\ 962 "); 963 #endif 964 965 /* 966 * Special exception 13 handler. 967 * Accessing non-existent MSR generates general protection fault. 968 */ 969 inthand_t bluetrap13; 970 #ifdef __GNUCLIKE_ASM 971 __asm 972 (" \n\ 973 .text \n\ 974 .p2align 2,0x90 \n\ 975 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 976 " __XSTRING(CNAME(bluetrap13)) ": \n\ 977 ss \n\ 978 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 979 popl %eax /* discard error code */ \n\ 980 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 981 iret \n\ 982 "); 983 #endif 984 985 /* 986 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 987 * support cpuid instruction. This function should be called after 988 * loading interrupt descriptor table register. 989 * 990 * I don't like this method that handles fault, but I couldn't get 991 * information for any other methods. Does blue giant know? 992 */ 993 static int 994 identblue(void) 995 { 996 997 trap_by_rdmsr = 0; 998 999 /* 1000 * Cyrix 486-class CPU does not support rdmsr instruction. 1001 * The rdmsr instruction generates invalid opcode fault, and exception 1002 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1003 * bluetrap6() set the magic number to trap_by_rdmsr. 1004 */ 1005 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1006 GSEL(GCODE_SEL, SEL_KPL)); 1007 1008 /* 1009 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1010 * In this case, rdmsr generates general protection fault, and 1011 * exception will be trapped by bluetrap13(). 1012 */ 1013 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1014 GSEL(GCODE_SEL, SEL_KPL)); 1015 1016 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1017 1018 if (trap_by_rdmsr == 0xa8c1d) 1019 return IDENTBLUE_CYRIX486; 1020 else if (trap_by_rdmsr == 0xa89c4) 1021 return IDENTBLUE_CYRIXM2; 1022 return IDENTBLUE_IBMCPU; 1023 } 1024 1025 1026 /* 1027 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1028 * 1029 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1030 * +-------+-------+---------------+ 1031 * | SID | RID | Device ID | 1032 * | (DIR 1) | (DIR 0) | 1033 * +-------+-------+---------------+ 1034 */ 1035 static void 1036 identifycyrix(void) 1037 { 1038 u_int eflags; 1039 int ccr2_test = 0, dir_test = 0; 1040 u_char ccr2, ccr3; 1041 1042 eflags = read_eflags(); 1043 disable_intr(); 1044 1045 ccr2 = read_cyrix_reg(CCR2); 1046 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1047 read_cyrix_reg(CCR2); 1048 if (read_cyrix_reg(CCR2) != ccr2) 1049 ccr2_test = 1; 1050 write_cyrix_reg(CCR2, ccr2); 1051 1052 ccr3 = read_cyrix_reg(CCR3); 1053 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1054 read_cyrix_reg(CCR3); 1055 if (read_cyrix_reg(CCR3) != ccr3) 1056 dir_test = 1; /* CPU supports DIRs. */ 1057 write_cyrix_reg(CCR3, ccr3); 1058 1059 if (dir_test) { 1060 /* Device ID registers are available. */ 1061 cyrix_did = read_cyrix_reg(DIR1) << 8; 1062 cyrix_did += read_cyrix_reg(DIR0); 1063 } else if (ccr2_test) 1064 cyrix_did = 0x0010; /* 486S A-step */ 1065 else 1066 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1067 1068 write_eflags(eflags); 1069 } 1070 1071 /* Update TSC freq with the value indicated by the caller. */ 1072 static void 1073 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 1074 { 1075 /* If there was an error during the transition, don't do anything. */ 1076 if (status != 0) 1077 return; 1078 1079 /* Total setting for this level gives the new frequency in MHz. */ 1080 hw_clockrate = level->total_set.freq; 1081 } 1082 1083 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 1084 EVENTHANDLER_PRI_ANY); 1085 1086 /* 1087 * Final stage of CPU identification. -- Should I check TI? 1088 */ 1089 void 1090 finishidentcpu(void) 1091 { 1092 int isblue = 0; 1093 u_char ccr3; 1094 u_int regs[4]; 1095 1096 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ 1097 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 1098 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 1099 init_exthigh(); 1100 if (cpu_exthigh >= 0x80000001) { 1101 do_cpuid(0x80000001, regs); 1102 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1103 amd_feature2 = regs[2]; 1104 } 1105 if (cpu_exthigh >= 0x80000008) { 1106 do_cpuid(0x80000008, regs); 1107 cpu_procinfo2 = regs[2]; 1108 } 1109 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 1110 if (cpu == CPU_486) { 1111 /* 1112 * These conditions are equivalent to: 1113 * - CPU does not support cpuid instruction. 1114 * - Cyrix/IBM CPU is detected. 1115 */ 1116 isblue = identblue(); 1117 if (isblue == IDENTBLUE_IBMCPU) { 1118 strcpy(cpu_vendor, "IBM"); 1119 cpu = CPU_BLUE; 1120 return; 1121 } 1122 } 1123 switch (cpu_id & 0xf00) { 1124 case 0x600: 1125 /* 1126 * Cyrix's datasheet does not describe DIRs. 1127 * Therefor, I assume it does not have them 1128 * and use the result of the cpuid instruction. 1129 * XXX they seem to have it for now at least. -Peter 1130 */ 1131 identifycyrix(); 1132 cpu = CPU_M2; 1133 break; 1134 default: 1135 identifycyrix(); 1136 /* 1137 * This routine contains a trick. 1138 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1139 */ 1140 switch (cyrix_did & 0x00f0) { 1141 case 0x00: 1142 case 0xf0: 1143 cpu = CPU_486DLC; 1144 break; 1145 case 0x10: 1146 cpu = CPU_CY486DX; 1147 break; 1148 case 0x20: 1149 if ((cyrix_did & 0x000f) < 8) 1150 cpu = CPU_M1; 1151 else 1152 cpu = CPU_M1SC; 1153 break; 1154 case 0x30: 1155 cpu = CPU_M1; 1156 break; 1157 case 0x40: 1158 /* MediaGX CPU */ 1159 cpu = CPU_M1SC; 1160 break; 1161 default: 1162 /* M2 and later CPUs are treated as M2. */ 1163 cpu = CPU_M2; 1164 1165 /* 1166 * enable cpuid instruction. 1167 */ 1168 ccr3 = read_cyrix_reg(CCR3); 1169 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1170 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1171 write_cyrix_reg(CCR3, ccr3); 1172 1173 do_cpuid(0, regs); 1174 cpu_high = regs[0]; /* eax */ 1175 do_cpuid(1, regs); 1176 cpu_id = regs[0]; /* eax */ 1177 cpu_feature = regs[3]; /* edx */ 1178 break; 1179 } 1180 } 1181 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1182 /* 1183 * There are BlueLightning CPUs that do not change 1184 * undefined flags by dividing 5 by 2. In this case, 1185 * the CPU identification routine in locore.s leaves 1186 * cpu_vendor null string and puts CPU_486 into the 1187 * cpu. 1188 */ 1189 isblue = identblue(); 1190 if (isblue == IDENTBLUE_IBMCPU) { 1191 strcpy(cpu_vendor, "IBM"); 1192 cpu = CPU_BLUE; 1193 return; 1194 } 1195 } 1196 } 1197 1198 static void 1199 print_AMD_assoc(int i) 1200 { 1201 if (i == 255) 1202 printf(", fully associative\n"); 1203 else 1204 printf(", %d-way associative\n", i); 1205 } 1206 1207 static void 1208 print_AMD_info(void) 1209 { 1210 quad_t amd_whcr; 1211 1212 if (cpu_exthigh >= 0x80000005) { 1213 u_int regs[4]; 1214 1215 do_cpuid(0x80000005, regs); 1216 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); 1217 print_AMD_assoc(regs[1] >> 24); 1218 printf("Instruction TLB: %d entries", regs[1] & 0xff); 1219 print_AMD_assoc((regs[1] >> 8) & 0xff); 1220 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1221 printf(", %d bytes/line", regs[2] & 0xff); 1222 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1223 print_AMD_assoc((regs[2] >> 16) & 0xff); 1224 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1225 printf(", %d bytes/line", regs[3] & 0xff); 1226 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1227 print_AMD_assoc((regs[3] >> 16) & 0xff); 1228 if (cpu_exthigh >= 0x80000006) { /* K6-III only */ 1229 do_cpuid(0x80000006, regs); 1230 printf("L2 internal cache: %d kbytes", regs[2] >> 16); 1231 printf(", %d bytes/line", regs[2] & 0xff); 1232 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1233 print_AMD_assoc((regs[2] >> 12) & 0x0f); 1234 } 1235 } 1236 if (((cpu_id & 0xf00) == 0x500) 1237 && (((cpu_id & 0x0f0) > 0x80) 1238 || (((cpu_id & 0x0f0) == 0x80) 1239 && (cpu_id & 0x00f) > 0x07))) { 1240 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1241 amd_whcr = rdmsr(0xc0000082); 1242 if (!(amd_whcr & (0x3ff << 22))) { 1243 printf("Write Allocate Disable\n"); 1244 } else { 1245 printf("Write Allocate Enable Limit: %dM bytes\n", 1246 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1247 printf("Write Allocate 15-16M bytes: %s\n", 1248 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1249 } 1250 } else if (((cpu_id & 0xf00) == 0x500) 1251 && ((cpu_id & 0x0f0) > 0x50)) { 1252 /* K6, K6-2(old core) */ 1253 amd_whcr = rdmsr(0xc0000082); 1254 if (!(amd_whcr & (0x7f << 1))) { 1255 printf("Write Allocate Disable\n"); 1256 } else { 1257 printf("Write Allocate Enable Limit: %dM bytes\n", 1258 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1259 printf("Write Allocate 15-16M bytes: %s\n", 1260 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1261 printf("Hardware Write Allocate Control: %s\n", 1262 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1263 } 1264 } 1265 } 1266 1267 static void 1268 print_INTEL_info(void) 1269 { 1270 u_int regs[4]; 1271 u_int rounds, regnum; 1272 u_int nwaycode, nway; 1273 1274 if (cpu_high >= 2) { 1275 rounds = 0; 1276 do { 1277 do_cpuid(0x2, regs); 1278 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1279 break; /* we have a buggy CPU */ 1280 1281 for (regnum = 0; regnum <= 3; ++regnum) { 1282 if (regs[regnum] & (1<<31)) 1283 continue; 1284 if (regnum != 0) 1285 print_INTEL_TLB(regs[regnum] & 0xff); 1286 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1287 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1288 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1289 } 1290 } while (--rounds > 0); 1291 } 1292 1293 if (cpu_exthigh >= 0x80000006) { 1294 do_cpuid(0x80000006, regs); 1295 nwaycode = (regs[2] >> 12) & 0x0f; 1296 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1297 nway = 1 << (nwaycode / 2); 1298 else 1299 nway = 0; 1300 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line", 1301 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1302 } 1303 1304 printf("\n"); 1305 } 1306 1307 static void 1308 print_INTEL_TLB(u_int data) 1309 { 1310 switch (data) { 1311 case 0x0: 1312 case 0x40: 1313 default: 1314 break; 1315 case 0x1: 1316 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries"); 1317 break; 1318 case 0x2: 1319 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries"); 1320 break; 1321 case 0x3: 1322 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries"); 1323 break; 1324 case 0x4: 1325 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries"); 1326 break; 1327 case 0x6: 1328 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size"); 1329 break; 1330 case 0x8: 1331 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size"); 1332 break; 1333 case 0xa: 1334 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size"); 1335 break; 1336 case 0xc: 1337 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size"); 1338 break; 1339 case 0x22: 1340 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size"); 1341 break; 1342 case 0x23: 1343 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1344 break; 1345 case 0x25: 1346 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size"); 1347 break; 1348 case 0x29: 1349 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size"); 1350 break; 1351 case 0x2c: 1352 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size"); 1353 break; 1354 case 0x30: 1355 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size"); 1356 break; 1357 case 0x39: 1358 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size"); 1359 break; 1360 case 0x3b: 1361 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size"); 1362 break; 1363 case 0x3c: 1364 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size"); 1365 break; 1366 case 0x41: 1367 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size"); 1368 break; 1369 case 0x42: 1370 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size"); 1371 break; 1372 case 0x43: 1373 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size"); 1374 break; 1375 case 0x44: 1376 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size"); 1377 break; 1378 case 0x45: 1379 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size"); 1380 break; 1381 case 0x46: 1382 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size"); 1383 break; 1384 case 0x47: 1385 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size"); 1386 break; 1387 case 0x50: 1388 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries"); 1389 break; 1390 case 0x51: 1391 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries"); 1392 break; 1393 case 0x52: 1394 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries"); 1395 break; 1396 case 0x5b: 1397 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries"); 1398 break; 1399 case 0x5c: 1400 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries"); 1401 break; 1402 case 0x5d: 1403 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries"); 1404 break; 1405 case 0x60: 1406 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size"); 1407 break; 1408 case 0x66: 1409 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size"); 1410 break; 1411 case 0x67: 1412 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size"); 1413 break; 1414 case 0x68: 1415 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size"); 1416 break; 1417 case 0x70: 1418 printf("\nTrace cache: 12K-uops, 8-way set associative"); 1419 break; 1420 case 0x71: 1421 printf("\nTrace cache: 16K-uops, 8-way set associative"); 1422 break; 1423 case 0x72: 1424 printf("\nTrace cache: 32K-uops, 8-way set associative"); 1425 break; 1426 case 0x78: 1427 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size"); 1428 break; 1429 case 0x79: 1430 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size"); 1431 break; 1432 case 0x7a: 1433 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size"); 1434 break; 1435 case 0x7b: 1436 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size"); 1437 break; 1438 case 0x7c: 1439 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1440 break; 1441 case 0x7d: 1442 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size"); 1443 break; 1444 case 0x7f: 1445 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size"); 1446 break; 1447 case 0x82: 1448 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size"); 1449 break; 1450 case 0x83: 1451 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size"); 1452 break; 1453 case 0x84: 1454 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size"); 1455 break; 1456 case 0x85: 1457 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size"); 1458 break; 1459 case 0x86: 1460 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size"); 1461 break; 1462 case 0x87: 1463 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size"); 1464 break; 1465 case 0xb0: 1466 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1467 break; 1468 case 0xb3: 1469 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1470 break; 1471 } 1472 } 1473 1474 1475 static void 1476 setPQL2_AMD(int *const size, int *const ways) { 1477 if (cpu_exthigh >= 0x80000006) { 1478 u_int regs[4]; 1479 1480 do_cpuid(0x80000006, regs); 1481 *size = regs[2] >> 16; 1482 *ways = (regs[2] >> 12) & 0x0f; 1483 } 1484 } 1485 1486 1487 static void 1488 setPQL2_INTEL(int *const size, int *const ways) 1489 { 1490 u_int rounds, regnum; 1491 u_int regs[4]; 1492 u_int nwaycode; 1493 1494 if (cpu_high >= 2) { 1495 rounds = 0; 1496 do { 1497 do_cpuid(0x2, regs); 1498 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1499 break; /* we have a buggy CPU */ 1500 1501 for (regnum = 0; regnum <= 3; ++regnum) { 1502 if (regs[regnum] & (1<<31)) 1503 continue; 1504 if (regnum != 0) 1505 get_INTEL_TLB(regs[regnum] & 0xff, 1506 size, ways); 1507 get_INTEL_TLB((regs[regnum] >> 8) & 0xff, 1508 size, ways); 1509 get_INTEL_TLB((regs[regnum] >> 16) & 0xff, 1510 size, ways); 1511 get_INTEL_TLB((regs[regnum] >> 24) & 0xff, 1512 size, ways); 1513 } 1514 } while (--rounds > 0); 1515 } 1516 1517 if (cpu_exthigh >= 0x80000006) { 1518 do_cpuid(0x80000006, regs); 1519 if (*size < ((regs[2] >> 16) & 0xffff)) { 1520 *size = (regs[2] >> 16) & 0xffff; 1521 nwaycode = (regs[2] >> 12) & 0x0f; 1522 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1523 *ways = 1 << (nwaycode / 2); 1524 else 1525 *ways = 0; 1526 } 1527 } 1528 } 1529 1530 static void 1531 get_INTEL_TLB(u_int data, int *const size, int *const ways) 1532 { 1533 switch (data) { 1534 default: 1535 break; 1536 case 0x22: 1537 /* 3rd-level cache: 512 KB, 4-way set associative, 1538 * sectored cache, 64 byte line size */ 1539 if (*size < 512) { 1540 *size = 512; 1541 *ways = 4; 1542 } 1543 break; 1544 case 0x23: 1545 /* 3rd-level cache: 1 MB, 8-way set associative, 1546 * sectored cache, 64 byte line size */ 1547 if (*size < 1024) { 1548 *size = 1024; 1549 *ways = 8; 1550 } 1551 break; 1552 case 0x25: 1553 /* 3rd-level cache: 2 MB, 8-way set associative, 1554 * sectored cache, 64 byte line size */ 1555 if (*size < 2048) { 1556 *size = 2048; 1557 *ways = 8; 1558 } 1559 break; 1560 case 0x29: 1561 /* 3rd-level cache: 4 MB, 8-way set associative, 1562 * sectored cache, 64 byte line size */ 1563 if (*size < 4096) { 1564 *size = 4096; 1565 *ways = 8; 1566 } 1567 break; 1568 case 0x39: 1569 /* 2nd-level cache: 128 KB, 4-way set associative, 1570 * sectored cache, 64 byte line size */ 1571 if (*size < 128) { 1572 *size = 128; 1573 *ways = 4; 1574 } 1575 break; 1576 case 0x3b: 1577 /* 2nd-level cache: 128 KB, 2-way set associative, 1578 * sectored cache, 64 byte line size */ 1579 if (*size < 128) { 1580 *size = 128; 1581 *ways = 2; 1582 } 1583 break; 1584 case 0x3c: 1585 /* 2nd-level cache: 256 KB, 4-way set associative, 1586 * sectored cache, 64 byte line size */ 1587 if (*size < 256) { 1588 *size = 256; 1589 *ways = 4; 1590 } 1591 break; 1592 case 0x41: 1593 /* 2nd-level cache: 128 KB, 4-way set associative, 1594 * 32 byte line size */ 1595 if (*size < 128) { 1596 *size = 128; 1597 *ways = 4; 1598 } 1599 break; 1600 case 0x42: 1601 /* 2nd-level cache: 256 KB, 4-way set associative, 1602 * 32 byte line size */ 1603 if (*size < 256) { 1604 *size = 256; 1605 *ways = 4; 1606 } 1607 break; 1608 case 0x43: 1609 /* 2nd-level cache: 512 KB, 4-way set associative, 1610 * 32 byte line size */ 1611 if (*size < 512) { 1612 *size = 512; 1613 *ways = 4; 1614 } 1615 break; 1616 case 0x44: 1617 /* 2nd-level cache: 1 MB, 4-way set associative, 1618 * 32 byte line size */ 1619 if (*size < 1024) { 1620 *size = 1024; 1621 *ways = 4; 1622 } 1623 break; 1624 case 0x45: 1625 /* 2nd-level cache: 2 MB, 4-way set associative, 1626 * 32 byte line size */ 1627 if (*size < 2048) { 1628 *size = 2048; 1629 *ways = 4; 1630 } 1631 break; 1632 case 0x46: 1633 /* 3rd-level cache: 4 MB, 4-way set associative, 1634 * 64 byte line size */ 1635 if (*size < 4096) { 1636 *size = 4096; 1637 *ways = 4; 1638 } 1639 break; 1640 case 0x47: 1641 /* 3rd-level cache: 8 MB, 8-way set associative, 1642 * 64 byte line size */ 1643 if (*size < 8192) { 1644 *size = 8192; 1645 *ways = 8; 1646 } 1647 break; 1648 case 0x78: 1649 /* 2nd-level cache: 1 MB, 4-way set associative, 1650 * 64-byte line size */ 1651 if (*size < 1024) { 1652 *size = 1024; 1653 *ways = 4; 1654 } 1655 break; 1656 case 0x79: 1657 /* 2nd-level cache: 128 KB, 8-way set associative, 1658 * sectored cache, 64 byte line size */ 1659 if (*size < 128) { 1660 *size = 128; 1661 *ways = 8; 1662 } 1663 break; 1664 case 0x7a: 1665 /* 2nd-level cache: 256 KB, 8-way set associative, 1666 * sectored cache, 64 byte line size */ 1667 if (*size < 256) { 1668 *size = 256; 1669 *ways = 8; 1670 } 1671 break; 1672 case 0x7b: 1673 /* 2nd-level cache: 512 KB, 8-way set associative, 1674 * sectored cache, 64 byte line size */ 1675 if (*size < 512) { 1676 *size = 512; 1677 *ways = 8; 1678 } 1679 break; 1680 case 0x7c: 1681 /* 2nd-level cache: 1 MB, 8-way set associative, 1682 * sectored cache, 64 byte line size */ 1683 if (*size < 1024) { 1684 *size = 1024; 1685 *ways = 8; 1686 } 1687 break; 1688 case 0x7d: 1689 /* 2nd-level cache: 2 MB, 8-way set associative, 1690 * 64-byte line size */ 1691 if (*size < 2048) { 1692 *size = 2048; 1693 *ways = 8; 1694 } 1695 break; 1696 case 0x7f: 1697 /* 2nd-level cache: 512 KB, 2-way set associative, 1698 * 64-byte line size */ 1699 if (*size < 512) { 1700 *size = 512; 1701 *ways = 2; 1702 } 1703 break; 1704 case 0x82: 1705 /* 2nd-level cache: 256 KB, 8-way set associative, 1706 * 32 byte line size */ 1707 if (*size < 256) { 1708 *size = 256; 1709 *ways = 8; 1710 } 1711 break; 1712 case 0x83: 1713 /* 2nd-level cache: 512 KB, 8-way set associative, 1714 * 32 byte line size */ 1715 if (*size < 512) { 1716 *size = 512; 1717 *ways = 8; 1718 } 1719 break; 1720 case 0x84: 1721 /* 2nd-level cache: 1 MB, 8-way set associative, 1722 * 32 byte line size */ 1723 if (*size < 1024) { 1724 *size = 1024; 1725 *ways = 8; 1726 } 1727 break; 1728 case 0x85: 1729 /* 2nd-level cache: 2 MB, 8-way set associative, 1730 * 32 byte line size */ 1731 if (*size < 2048) { 1732 *size = 2048; 1733 *ways = 8; 1734 } 1735 break; 1736 case 0x86: 1737 /* 2nd-level cache: 512 KB, 4-way set associative, 1738 * 64 byte line size */ 1739 if (*size < 512) { 1740 *size = 512; 1741 *ways = 4; 1742 } 1743 break; 1744 case 0x87: 1745 /* 2nd-level cache: 1 MB, 8-way set associative, 1746 * 64 byte line size */ 1747 if (*size < 1024) { 1748 *size = 512; 1749 *ways = 8; 1750 } 1751 break; 1752 } 1753 } 1754 1755 void 1756 setPQL2(int *const size, int *const ways) 1757 { 1758 /* make sure the cpu_exthigh variable is initialized */ 1759 init_exthigh(); 1760 1761 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 1762 setPQL2_AMD(size, ways); 1763 else if (strcmp(cpu_vendor, "GenuineIntel") == 0) 1764 setPQL2_INTEL(size, ways); 1765 } 1766 1767 static void 1768 print_transmeta_info() 1769 { 1770 u_int regs[4], nreg = 0; 1771 1772 do_cpuid(0x80860000, regs); 1773 nreg = regs[0]; 1774 if (nreg >= 0x80860001) { 1775 do_cpuid(0x80860001, regs); 1776 printf(" Processor revision %u.%u.%u.%u\n", 1777 (regs[1] >> 24) & 0xff, 1778 (regs[1] >> 16) & 0xff, 1779 (regs[1] >> 8) & 0xff, 1780 regs[1] & 0xff); 1781 } 1782 if (nreg >= 0x80860002) { 1783 do_cpuid(0x80860002, regs); 1784 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 1785 (regs[1] >> 24) & 0xff, 1786 (regs[1] >> 16) & 0xff, 1787 (regs[1] >> 8) & 0xff, 1788 regs[1] & 0xff, 1789 regs[2]); 1790 } 1791 if (nreg >= 0x80860006) { 1792 char info[65]; 1793 do_cpuid(0x80860003, (u_int*) &info[0]); 1794 do_cpuid(0x80860004, (u_int*) &info[16]); 1795 do_cpuid(0x80860005, (u_int*) &info[32]); 1796 do_cpuid(0x80860006, (u_int*) &info[48]); 1797 info[64] = 0; 1798 printf(" %s\n", info); 1799 } 1800 }
Cache object: 860664e94c13f650e9fe0aac8a64967a
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