The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/identcpu.c

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    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD$");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/cpu.h>
   49 #include <sys/eventhandler.h>
   50 #include <sys/systm.h>
   51 #include <sys/kernel.h>
   52 #include <sys/sysctl.h>
   53 #include <sys/power.h>
   54 
   55 #include <machine/asmacros.h>
   56 #include <machine/clock.h>
   57 #include <machine/cputypes.h>
   58 #include <machine/intr_machdep.h>
   59 #include <machine/md_var.h>
   60 #include <machine/segments.h>
   61 #include <machine/specialreg.h>
   62 
   63 #define IDENTBLUE_CYRIX486      0
   64 #define IDENTBLUE_IBMCPU        1
   65 #define IDENTBLUE_CYRIXM2       2
   66 
   67 /* XXX - should be in header file: */
   68 void printcpuinfo(void);
   69 void finishidentcpu(void);
   70 void earlysetcpuclass(void);
   71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   72 void    enable_K5_wt_alloc(void);
   73 void    enable_K6_wt_alloc(void);
   74 void    enable_K6_2_wt_alloc(void);
   75 #endif
   76 void panicifcpuunsupported(void);
   77 
   78 static void identifycyrix(void);
   79 static void init_exthigh(void);
   80 void setPQL2(int *const size, int *const ways);
   81 static void setPQL2_AMD(int *const size, int *const ways);
   82 static void setPQL2_INTEL(int *const size, int *const ways);
   83 static void get_INTEL_TLB(u_int data, int *const size, int *const ways);
   84 static void print_AMD_info(void);
   85 static void print_INTEL_info(void);
   86 static void print_INTEL_TLB(u_int data);
   87 static void print_AMD_assoc(int i);
   88 static void print_transmeta_info(void);
   89 static void print_via_padlock_info(void);
   90 
   91 int     cpu_class;
   92 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   93 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
   94 char machine[] = MACHINE;
   95 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   96     machine, 0, "Machine class");
   97 
   98 static char cpu_model[128];
   99 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
  100     cpu_model, 0, "Machine model");
  101 
  102 static int hw_clockrate;
  103 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
  104     &hw_clockrate, 0, "CPU instruction clock rate");
  105 
  106 static char cpu_brand[48];
  107 
  108 #define MAX_BRAND_INDEX 8
  109 
  110 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
  111         NULL,                   /* No brand */
  112         "Intel Celeron",
  113         "Intel Pentium III",
  114         "Intel Pentium III Xeon",
  115         NULL,
  116         NULL,
  117         NULL,
  118         NULL,
  119         "Intel Pentium 4"
  120 };
  121 
  122 static struct {
  123         char    *cpu_name;
  124         int     cpu_class;
  125 } i386_cpus[] = {
  126         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
  127         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
  128         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
  129         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
  130         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
  131         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
  132         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
  133         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
  134         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
  135         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
  136         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
  137         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
  138         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
  139         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
  140         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
  141         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
  142         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
  143 };
  144 
  145 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  146 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
  147 #endif
  148 
  149 static void
  150 init_exthigh(void)
  151 {
  152         static int done = 0;
  153         u_int regs[4];
  154 
  155         if (done == 0) {
  156                 if (cpu_high > 0 &&
  157                     (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  158                     strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  159                     strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  160                     strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  161                     strcmp(cpu_vendor, "CentaurHauls") == 0 ||
  162                     strcmp(cpu_vendor, "Geode by NSC") == 0)) {
  163                         do_cpuid(0x80000000, regs);
  164                         if (regs[0] >= 0x80000000)
  165                                 cpu_exthigh = regs[0];
  166                 }
  167 
  168                 done = 1;
  169         }
  170 }
  171 
  172 void
  173 printcpuinfo(void)
  174 {
  175         u_int regs[4], i;
  176         char *brand;
  177 
  178         cpu_class = i386_cpus[cpu].cpu_class;
  179         printf("CPU: ");
  180         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
  181 
  182         /* Check for extended CPUID information and a processor name. */
  183         init_exthigh();
  184         if (cpu_exthigh >= 0x80000004) {
  185                 brand = cpu_brand;
  186                 for (i = 0x80000002; i < 0x80000005; i++) {
  187                         do_cpuid(i, regs);
  188                         memcpy(brand, regs, sizeof(regs));
  189                         brand += sizeof(regs);
  190                 }
  191         }
  192 
  193         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  194                 if ((cpu_id & 0xf00) > 0x300) {
  195                         u_int brand_index;
  196                         u_int model;
  197 
  198                         cpu_model[0] = '\0';
  199 
  200                         switch (cpu_id & 0x3000) {
  201                         case 0x1000:
  202                                 strcpy(cpu_model, "Overdrive ");
  203                                 break;
  204                         case 0x2000:
  205                                 strcpy(cpu_model, "Dual ");
  206                                 break;
  207                         }
  208 
  209                         switch (cpu_id & 0xf00) {
  210                         case 0x400:
  211                                 strcat(cpu_model, "i486 ");
  212                                 /* Check the particular flavor of 486 */
  213                                 switch (cpu_id & 0xf0) {
  214                                 case 0x00:
  215                                 case 0x10:
  216                                         strcat(cpu_model, "DX");
  217                                         break;
  218                                 case 0x20:
  219                                         strcat(cpu_model, "SX");
  220                                         break;
  221                                 case 0x30:
  222                                         strcat(cpu_model, "DX2");
  223                                         break;
  224                                 case 0x40:
  225                                         strcat(cpu_model, "SL");
  226                                         break;
  227                                 case 0x50:
  228                                         strcat(cpu_model, "SX2");
  229                                         break;
  230                                 case 0x70:
  231                                         strcat(cpu_model,
  232                                             "DX2 Write-Back Enhanced");
  233                                         break;
  234                                 case 0x80:
  235                                         strcat(cpu_model, "DX4");
  236                                         break;
  237                                 }
  238                                 break;
  239                         case 0x500:
  240                                 /* Check the particular flavor of 586 */
  241                                 strcat(cpu_model, "Pentium");
  242                                 switch (cpu_id & 0xf0) {
  243                                 case 0x00:
  244                                         strcat(cpu_model, " A-step");
  245                                         break;
  246                                 case 0x10:
  247                                         strcat(cpu_model, "/P5");
  248                                         break;
  249                                 case 0x20:
  250                                         strcat(cpu_model, "/P54C");
  251                                         break;
  252                                 case 0x30:
  253                                         strcat(cpu_model, "/P54T Overdrive");
  254                                         break;
  255                                 case 0x40:
  256                                         strcat(cpu_model, "/P55C");
  257                                         break;
  258                                 case 0x70:
  259                                         strcat(cpu_model, "/P54C");
  260                                         break;
  261                                 case 0x80:
  262                                         strcat(cpu_model, "/P55C (quarter-micron)");
  263                                         break;
  264                                 default:
  265                                         /* nothing */
  266                                         break;
  267                                 }
  268 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  269                                 /*
  270                                  * XXX - If/when Intel fixes the bug, this
  271                                  * should also check the version of the
  272                                  * CPU, not just that it's a Pentium.
  273                                  */
  274                                 has_f00f_bug = 1;
  275 #endif
  276                                 break;
  277                         case 0x600:
  278                                 /* Check the particular flavor of 686 */
  279                                 switch (cpu_id & 0xf0) {
  280                                 case 0x00:
  281                                         strcat(cpu_model, "Pentium Pro A-step");
  282                                         break;
  283                                 case 0x10:
  284                                         strcat(cpu_model, "Pentium Pro");
  285                                         break;
  286                                 case 0x30:
  287                                 case 0x50:
  288                                 case 0x60:
  289                                         strcat(cpu_model,
  290                                 "Pentium II/Pentium II Xeon/Celeron");
  291                                         cpu = CPU_PII;
  292                                         break;
  293                                 case 0x70:
  294                                 case 0x80:
  295                                 case 0xa0:
  296                                 case 0xb0:
  297                                         strcat(cpu_model,
  298                                         "Pentium III/Pentium III Xeon/Celeron");
  299                                         cpu = CPU_PIII;
  300                                         break;
  301                                 default:
  302                                         strcat(cpu_model, "Unknown 80686");
  303                                         break;
  304                                 }
  305                                 break;
  306                         case 0xf00:
  307                                 strcat(cpu_model, "Pentium 4");
  308                                 cpu = CPU_P4;
  309                                 model = (cpu_id & 0x0f0) >> 4;
  310                                 if (model == 3 || model == 4 || model == 6) {
  311                                         uint64_t tmp;
  312 
  313                                         tmp = rdmsr(MSR_IA32_MISC_ENABLE);
  314                                         wrmsr(MSR_IA32_MISC_ENABLE,
  315                                               tmp & ~(1LL << 22));
  316                                         do_cpuid(0, regs);
  317                                         cpu_high = regs[0];
  318                                 }
  319                                 break;
  320                         default:
  321                                 strcat(cpu_model, "unknown");
  322                                 break;
  323                         }
  324 
  325                         /*
  326                          * If we didn't get a brand name from the extended
  327                          * CPUID, try to look it up in the brand table.
  328                          */
  329                         if (cpu_high > 0 && *cpu_brand == '\0') {
  330                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
  331                                 if (brand_index <= MAX_BRAND_INDEX &&
  332                                     cpu_brandtable[brand_index] != NULL)
  333                                         strcpy(cpu_brand,
  334                                             cpu_brandtable[brand_index]);
  335                         }
  336                 }
  337         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  338                 /*
  339                  * Values taken from AMD Processor Recognition
  340                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  341                  * (also describes ``Features'' encodings.
  342                  */
  343                 strcpy(cpu_model, "AMD ");
  344                 switch (cpu_id & 0xFF0) {
  345                 case 0x410:
  346                         strcat(cpu_model, "Standard Am486DX");
  347                         break;
  348                 case 0x430:
  349                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
  350                         break;
  351                 case 0x470:
  352                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
  353                         break;
  354                 case 0x480:
  355                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
  356                         break;
  357                 case 0x490:
  358                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
  359                         break;
  360                 case 0x4E0:
  361                         strcat(cpu_model, "Am5x86 Write-Through");
  362                         break;
  363                 case 0x4F0:
  364                         strcat(cpu_model, "Am5x86 Write-Back");
  365                         break;
  366                 case 0x500:
  367                         strcat(cpu_model, "K5 model 0");
  368                         tsc_is_broken = 1;
  369                         break;
  370                 case 0x510:
  371                         strcat(cpu_model, "K5 model 1");
  372                         break;
  373                 case 0x520:
  374                         strcat(cpu_model, "K5 PR166 (model 2)");
  375                         break;
  376                 case 0x530:
  377                         strcat(cpu_model, "K5 PR200 (model 3)");
  378                         break;
  379                 case 0x560:
  380                         strcat(cpu_model, "K6");
  381                         break;
  382                 case 0x570:
  383                         strcat(cpu_model, "K6 266 (model 1)");
  384                         break;
  385                 case 0x580:
  386                         strcat(cpu_model, "K6-2");
  387                         break;
  388                 case 0x590:
  389                         strcat(cpu_model, "K6-III");
  390                         break;
  391                 case 0x5a0:
  392                         strcat(cpu_model, "Geode LX");
  393                         /*
  394                          * Make sure the TSC runs through suspension,
  395                          * otherwise we can't use it as timecounter
  396                          */
  397                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
  398                         break;
  399                 default:
  400                         strcat(cpu_model, "Unknown");
  401                         break;
  402                 }
  403 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  404                 if ((cpu_id & 0xf00) == 0x500) {
  405                         if (((cpu_id & 0x0f0) > 0)
  406                             && ((cpu_id & 0x0f0) < 0x60)
  407                             && ((cpu_id & 0x00f) > 3))
  408                                 enable_K5_wt_alloc();
  409                         else if (((cpu_id & 0x0f0) > 0x80)
  410                                  || (((cpu_id & 0x0f0) == 0x80)
  411                                      && (cpu_id & 0x00f) > 0x07))
  412                                 enable_K6_2_wt_alloc();
  413                         else if ((cpu_id & 0x0f0) > 0x50)
  414                                 enable_K6_wt_alloc();
  415                 }
  416 #endif
  417         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  418                 strcpy(cpu_model, "Cyrix ");
  419                 switch (cpu_id & 0xff0) {
  420                 case 0x440:
  421                         strcat(cpu_model, "MediaGX");
  422                         break;
  423                 case 0x520:
  424                         strcat(cpu_model, "6x86");
  425                         break;
  426                 case 0x540:
  427                         cpu_class = CPUCLASS_586;
  428                         strcat(cpu_model, "GXm");
  429                         break;
  430                 case 0x600:
  431                         strcat(cpu_model, "6x86MX");
  432                         break;
  433                 default:
  434                         /*
  435                          * Even though CPU supports the cpuid
  436                          * instruction, it can be disabled.
  437                          * Therefore, this routine supports all Cyrix
  438                          * CPUs.
  439                          */
  440                         switch (cyrix_did & 0xf0) {
  441                         case 0x00:
  442                                 switch (cyrix_did & 0x0f) {
  443                                 case 0x00:
  444                                         strcat(cpu_model, "486SLC");
  445                                         break;
  446                                 case 0x01:
  447                                         strcat(cpu_model, "486DLC");
  448                                         break;
  449                                 case 0x02:
  450                                         strcat(cpu_model, "486SLC2");
  451                                         break;
  452                                 case 0x03:
  453                                         strcat(cpu_model, "486DLC2");
  454                                         break;
  455                                 case 0x04:
  456                                         strcat(cpu_model, "486SRx");
  457                                         break;
  458                                 case 0x05:
  459                                         strcat(cpu_model, "486DRx");
  460                                         break;
  461                                 case 0x06:
  462                                         strcat(cpu_model, "486SRx2");
  463                                         break;
  464                                 case 0x07:
  465                                         strcat(cpu_model, "486DRx2");
  466                                         break;
  467                                 case 0x08:
  468                                         strcat(cpu_model, "486SRu");
  469                                         break;
  470                                 case 0x09:
  471                                         strcat(cpu_model, "486DRu");
  472                                         break;
  473                                 case 0x0a:
  474                                         strcat(cpu_model, "486SRu2");
  475                                         break;
  476                                 case 0x0b:
  477                                         strcat(cpu_model, "486DRu2");
  478                                         break;
  479                                 default:
  480                                         strcat(cpu_model, "Unknown");
  481                                         break;
  482                                 }
  483                                 break;
  484                         case 0x10:
  485                                 switch (cyrix_did & 0x0f) {
  486                                 case 0x00:
  487                                         strcat(cpu_model, "486S");
  488                                         break;
  489                                 case 0x01:
  490                                         strcat(cpu_model, "486S2");
  491                                         break;
  492                                 case 0x02:
  493                                         strcat(cpu_model, "486Se");
  494                                         break;
  495                                 case 0x03:
  496                                         strcat(cpu_model, "486S2e");
  497                                         break;
  498                                 case 0x0a:
  499                                         strcat(cpu_model, "486DX");
  500                                         break;
  501                                 case 0x0b:
  502                                         strcat(cpu_model, "486DX2");
  503                                         break;
  504                                 case 0x0f:
  505                                         strcat(cpu_model, "486DX4");
  506                                         break;
  507                                 default:
  508                                         strcat(cpu_model, "Unknown");
  509                                         break;
  510                                 }
  511                                 break;
  512                         case 0x20:
  513                                 if ((cyrix_did & 0x0f) < 8)
  514                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
  515                                 else
  516                                         strcat(cpu_model, "5x86");
  517                                 break;
  518                         case 0x30:
  519                                 strcat(cpu_model, "6x86");
  520                                 break;
  521                         case 0x40:
  522                                 if ((cyrix_did & 0xf000) == 0x3000) {
  523                                         cpu_class = CPUCLASS_586;
  524                                         strcat(cpu_model, "GXm");
  525                                 } else
  526                                         strcat(cpu_model, "MediaGX");
  527                                 break;
  528                         case 0x50:
  529                                 strcat(cpu_model, "6x86MX");
  530                                 break;
  531                         case 0xf0:
  532                                 switch (cyrix_did & 0x0f) {
  533                                 case 0x0d:
  534                                         strcat(cpu_model, "Overdrive CPU");
  535                                         break;
  536                                 case 0x0e:
  537                                         strcpy(cpu_model, "Texas Instruments 486SXL");
  538                                         break;
  539                                 case 0x0f:
  540                                         strcat(cpu_model, "486SLC/DLC");
  541                                         break;
  542                                 default:
  543                                         strcat(cpu_model, "Unknown");
  544                                         break;
  545                                 }
  546                                 break;
  547                         default:
  548                                 strcat(cpu_model, "Unknown");
  549                                 break;
  550                         }
  551                         break;
  552                 }
  553         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
  554                 strcpy(cpu_model, "Rise ");
  555                 switch (cpu_id & 0xff0) {
  556                 case 0x500:
  557                         strcat(cpu_model, "mP6");
  558                         break;
  559                 default:
  560                         strcat(cpu_model, "Unknown");
  561                 }
  562         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
  563                 switch (cpu_id & 0xff0) {
  564                 case 0x540:
  565                         strcpy(cpu_model, "IDT WinChip C6");
  566                         tsc_is_broken = 1;
  567                         break;
  568                 case 0x580:
  569                         strcpy(cpu_model, "IDT WinChip 2");
  570                         break;
  571                 case 0x660:
  572                         strcpy(cpu_model, "VIA C3 Samuel");
  573                         break;
  574                 case 0x670:
  575                         if (cpu_id & 0x8)
  576                                 strcpy(cpu_model, "VIA C3 Ezra");
  577                         else
  578                                 strcpy(cpu_model, "VIA C3 Samuel 2");
  579                         break;
  580                 case 0x680:
  581                         strcpy(cpu_model, "VIA C3 Ezra-T");
  582                         break;
  583                 case 0x690:
  584                         strcpy(cpu_model, "VIA C3 Nehemiah");
  585                         break;
  586                 case 0x6a0:
  587                 case 0x6d0:
  588                         strcpy(cpu_model, "VIA C7 Esther");
  589                         break;
  590                 default:
  591                         strcpy(cpu_model, "VIA/IDT Unknown");
  592                 }
  593         } else if (strcmp(cpu_vendor, "IBM") == 0) {
  594                 strcpy(cpu_model, "Blue Lightning CPU");
  595         } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
  596                 switch (cpu_id & 0xfff) {
  597                 case 0x540:
  598                         strcpy(cpu_model, "Geode SC1100");
  599                         cpu = CPU_GEODE1100;
  600                         tsc_is_broken = 1;
  601                         break;
  602                 default:
  603                         strcpy(cpu_model, "Geode/NSC unknown");
  604                         break;
  605                 }
  606         }
  607 
  608         /*
  609          * Replace cpu_model with cpu_brand minus leading spaces if
  610          * we have one.
  611          */
  612         brand = cpu_brand;
  613         while (*brand == ' ')
  614                 ++brand;
  615         if (*brand != '\0')
  616                 strcpy(cpu_model, brand);
  617 
  618         printf("%s (", cpu_model);
  619         switch(cpu_class) {
  620         case CPUCLASS_286:
  621                 printf("286");
  622                 break;
  623         case CPUCLASS_386:
  624                 printf("386");
  625                 break;
  626 #if defined(I486_CPU)
  627         case CPUCLASS_486:
  628                 printf("486");
  629                 bzero_vector = i486_bzero;
  630                 break;
  631 #endif
  632 #if defined(I586_CPU)
  633         case CPUCLASS_586:
  634                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  635                 printf("%jd.%02d-MHz ",
  636                        (intmax_t)(tsc_freq + 4999) / 1000000,
  637                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  638                 printf("586");
  639                 break;
  640 #endif
  641 #if defined(I686_CPU)
  642         case CPUCLASS_686:
  643                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  644                 printf("%jd.%02d-MHz ",
  645                        (intmax_t)(tsc_freq + 4999) / 1000000,
  646                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  647                 printf("686");
  648                 break;
  649 #endif
  650         default:
  651                 printf("Unknown");      /* will panic below... */
  652         }
  653         printf("-class CPU)\n");
  654         if(*cpu_vendor)
  655                 printf("  Origin = \"%s\"",cpu_vendor);
  656         if(cpu_id)
  657                 printf("  Id = 0x%x", cpu_id);
  658 
  659         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  660             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
  661             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  662             strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
  663             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
  664             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
  665             strcmp(cpu_vendor, "Geode by NSC") == 0 ||
  666                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
  667                  ((cpu_id & 0xf00) > 0x500))) {
  668                 printf("  Stepping = %u", cpu_id & 0xf);
  669                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
  670                         printf("  DIR=0x%04x", cyrix_did);
  671                 if (cpu_high > 0) {
  672                         u_int cmp = 1, htt = 1;
  673 
  674                         /*
  675                          * Here we should probably set up flags indicating
  676                          * whether or not various features are available.
  677                          * The interesting ones are probably VME, PSE, PAE,
  678                          * and PGE.  The code already assumes without bothering
  679                          * to check that all CPUs >= Pentium have a TSC and
  680                          * MSRs.
  681                          */
  682                         printf("\n  Features=0x%b", cpu_feature,
  683                         "\020"
  684                         "\001FPU"       /* Integral FPU */
  685                         "\002VME"       /* Extended VM86 mode support */
  686                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  687                         "\004PSE"       /* 4MByte page tables */
  688                         "\005TSC"       /* Timestamp counter */
  689                         "\006MSR"       /* Machine specific registers */
  690                         "\007PAE"       /* Physical address extension */
  691                         "\010MCE"       /* Machine Check support */
  692                         "\011CX8"       /* CMPEXCH8 instruction */
  693                         "\012APIC"      /* SMP local APIC */
  694                         "\013oldMTRR"   /* Previous implementation of MTRR */
  695                         "\014SEP"       /* Fast System Call */
  696                         "\015MTRR"      /* Memory Type Range Registers */
  697                         "\016PGE"       /* PG_G (global bit) support */
  698                         "\017MCA"       /* Machine Check Architecture */
  699                         "\020CMOV"      /* CMOV instruction */
  700                         "\021PAT"       /* Page attributes table */
  701                         "\022PSE36"     /* 36 bit address space support */
  702                         "\023PN"        /* Processor Serial number */
  703                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  704                         "\025<b20>"
  705                         "\026DTS"       /* Debug Trace Store */
  706                         "\027ACPI"      /* ACPI support */
  707                         "\030MMX"       /* MMX instructions */
  708                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  709                         "\032SSE"       /* Streaming SIMD Extensions */
  710                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  711                         "\034SS"        /* Self snoop */
  712                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  713                         "\036TM"        /* Thermal Monitor clock slowdown */
  714                         "\037IA64"      /* CPU can execute IA64 instructions */
  715                         "\040PBE"       /* Pending Break Enable */
  716                         );
  717 
  718                         if (cpu_feature2 != 0) {
  719                                 printf("\n  Features2=0x%b", cpu_feature2,
  720                                 "\020"
  721                                 "\001SSE3"      /* SSE3 */
  722                                 "\002<b1>"
  723                                 "\003DTES64"    /* 64-bit Debug Trace */
  724                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  725                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  726                                 "\006VMX"       /* Virtual Machine Extensions */
  727                                 "\007SMX"       /* Safer Mode Extensions */
  728                                 "\010EST"       /* Enhanced SpeedStep */
  729                                 "\011TM2"       /* Thermal Monitor 2 */
  730                                 "\012SSSE3"     /* SSSE3 */
  731                                 "\013CNXT-ID"   /* L1 context ID available */
  732                                 "\014<b11>"
  733                                 "\015<b12>"
  734                                 "\016CX16"      /* CMPXCHG16B Instruction */
  735                                 "\017xTPR"      /* Send Task Priority Messages*/
  736                                 "\020PDCM"      /* Perf/Debug Capability MSR */
  737                                 "\021<b16>"
  738                                 "\022<b17>"
  739                                 "\023DCA"       /* Direct Cache Access */
  740                                 "\024SSE4.1"
  741                                 "\025SSE4.2"
  742                                 "\026x2APIC"    /* xAPIC Extensions */
  743                                 "\027<b22>"
  744                                 "\030POPCNT"
  745                                 "\031<b24>"
  746                                 "\032<b25>"
  747                                 "\033<b26>"
  748                                 "\034<b27>"
  749                                 "\035<b28>"
  750                                 "\036<b29>"
  751                                 "\037<b30>"
  752                                 "\040<b31>"
  753                                 );
  754                         }
  755 
  756                         /*
  757                          * AMD64 Architecture Programmer's Manual Volume 3:
  758                          * General-Purpose and System Instructions
  759                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
  760                          *
  761                          * IA-32 Intel Architecture Software Developer's Manual,
  762                          * Volume 2A: Instruction Set Reference, A-M
  763                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
  764                          */
  765                         if (amd_feature != 0) {
  766                                 printf("\n  AMD Features=0x%b", amd_feature,
  767                                 "\020"          /* in hex */
  768                                 "\001<s0>"      /* Same */
  769                                 "\002<s1>"      /* Same */
  770                                 "\003<s2>"      /* Same */
  771                                 "\004<s3>"      /* Same */
  772                                 "\005<s4>"      /* Same */
  773                                 "\006<s5>"      /* Same */
  774                                 "\007<s6>"      /* Same */
  775                                 "\010<s7>"      /* Same */
  776                                 "\011<s8>"      /* Same */
  777                                 "\012<s9>"      /* Same */
  778                                 "\013<b10>"     /* Undefined */
  779                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  780                                 "\015<s12>"     /* Same */
  781                                 "\016<s13>"     /* Same */
  782                                 "\017<s14>"     /* Same */
  783                                 "\020<s15>"     /* Same */
  784                                 "\021<s16>"     /* Same */
  785                                 "\022<s17>"     /* Same */
  786                                 "\023<b18>"     /* Reserved, unknown */
  787                                 "\024MP"        /* Multiprocessor Capable */
  788                                 "\025NX"        /* Has EFER.NXE, NX */
  789                                 "\026<b21>"     /* Undefined */
  790                                 "\027MMX+"      /* AMD MMX Extensions */
  791                                 "\030<s23>"     /* Same */
  792                                 "\031<s24>"     /* Same */
  793                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
  794                                 "\033Page1GB"   /* 1-GB large page support */
  795                                 "\034RDTSCP"    /* RDTSCP */
  796                                 "\035<b28>"     /* Undefined */
  797                                 "\036LM"        /* 64 bit long mode */
  798                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
  799                                 "\0403DNow!"    /* AMD 3DNow! */
  800                                 );
  801                         }
  802 
  803                         if (amd_feature2 != 0) {
  804                                 printf("\n  AMD Features2=0x%b", amd_feature2,
  805                                 "\020"
  806                                 "\001LAHF"      /* LAHF/SAHF in long mode */
  807                                 "\002CMP"       /* CMP legacy */
  808                                 "\003SVM"       /* Secure Virtual Mode */
  809                                 "\004ExtAPIC"   /* Extended APIC register */
  810                                 "\005CR8"       /* CR8 in legacy mode */
  811                                 "\006<b5>"
  812                                 "\007<b6>"
  813                                 "\010<b7>"
  814                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
  815                                 "\012<b9>"
  816                                 "\013<b10>"
  817                                 "\014<b11>"
  818                                 "\015<b12>"
  819                                 "\016<b13>"
  820                                 "\017<b14>"
  821                                 "\020<b15>"
  822                                 "\021<b16>"
  823                                 "\022<b17>"
  824                                 "\023<b18>"
  825                                 "\024<b19>"
  826                                 "\025<b20>"
  827                                 "\026<b21>"
  828                                 "\027<b22>"
  829                                 "\030<b23>"
  830                                 "\031<b24>"
  831                                 "\032<b25>"
  832                                 "\033<b26>"
  833                                 "\034<b27>"
  834                                 "\035<b28>"
  835                                 "\036<b29>"
  836                                 "\037<b30>"
  837                                 "\040<b31>"
  838                                 );
  839                         }
  840 
  841                         if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
  842                             "AuthenticAMD") == 0)
  843                                 cpu_feature &= ~CPUID_HTT;
  844 
  845                         /*
  846                          * If this CPU supports HTT or CMP then mention the
  847                          * number of physical/logical cores it contains.
  848                          */
  849                         if (cpu_feature & CPUID_HTT)
  850                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
  851                         if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
  852                             (amd_feature2 & AMDID2_CMP))
  853                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  854                         else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
  855                             (cpu_high >= 4)) {
  856                                 cpuid_count(4, 0, regs);
  857                                 if ((regs[0] & 0x1f) != 0)
  858                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
  859                         }
  860                         if (cmp > 1)
  861                                 printf("\n  Cores per package: %d", cmp);
  862                         if ((htt / cmp) > 1)
  863                                 printf("\n  Logical CPUs per core: %d",
  864                                     htt / cmp);
  865                 }
  866         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  867                 printf("  DIR=0x%04x", cyrix_did);
  868                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
  869                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
  870 #ifndef CYRIX_CACHE_REALLY_WORKS
  871                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
  872                         printf("\n  CPU cache: write-through mode");
  873 #endif
  874         }
  875         if (strcmp(cpu_vendor, "CentaurHauls") == 0)
  876                 print_via_padlock_info();
  877 
  878         /* Avoid ugly blank lines: only print newline when we have to. */
  879         if (*cpu_vendor || cpu_id)
  880                 printf("\n");
  881 
  882         if (!bootverbose)
  883                 return;
  884 
  885         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  886                 print_AMD_info();
  887         else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
  888                 print_INTEL_info();
  889         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
  890                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
  891                 print_transmeta_info();
  892 }
  893 
  894 void
  895 panicifcpuunsupported(void)
  896 {
  897 
  898 #if !defined(lint)
  899 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
  900 #error This kernel is not configured for one of the supported CPUs
  901 #endif
  902 #else /* lint */
  903 #endif /* lint */
  904         /*
  905          * Now that we have told the user what they have,
  906          * let them know if that machine type isn't configured.
  907          */
  908         switch (cpu_class) {
  909         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
  910         case CPUCLASS_386:
  911 #if !defined(I486_CPU)
  912         case CPUCLASS_486:
  913 #endif
  914 #if !defined(I586_CPU)
  915         case CPUCLASS_586:
  916 #endif
  917 #if !defined(I686_CPU)
  918         case CPUCLASS_686:
  919 #endif
  920                 panic("CPU class not configured");
  921         default:
  922                 break;
  923         }
  924 }
  925 
  926 
  927 static  volatile u_int trap_by_rdmsr;
  928 
  929 /*
  930  * Special exception 6 handler.
  931  * The rdmsr instruction generates invalid opcodes fault on 486-class
  932  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
  933  * function identblue() when this handler is called.  Stacked eip should
  934  * be advanced.
  935  */
  936 inthand_t       bluetrap6;
  937 #ifdef __GNUCLIKE_ASM
  938 __asm
  939 ("                                                                      \n\
  940         .text                                                           \n\
  941         .p2align 2,0x90                                                 \n\
  942         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
  943 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
  944         ss                                                              \n\
  945         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  946         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  947         iret                                                            \n\
  948 ");
  949 #endif
  950 
  951 /*
  952  * Special exception 13 handler.
  953  * Accessing non-existent MSR generates general protection fault.
  954  */
  955 inthand_t       bluetrap13;
  956 #ifdef __GNUCLIKE_ASM
  957 __asm
  958 ("                                                                      \n\
  959         .text                                                           \n\
  960         .p2align 2,0x90                                                 \n\
  961         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
  962 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
  963         ss                                                              \n\
  964         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  965         popl    %eax            /* discard error code */                \n\
  966         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  967         iret                                                            \n\
  968 ");
  969 #endif
  970 
  971 /*
  972  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
  973  * support cpuid instruction.  This function should be called after
  974  * loading interrupt descriptor table register.
  975  *
  976  * I don't like this method that handles fault, but I couldn't get
  977  * information for any other methods.  Does blue giant know?
  978  */
  979 static int
  980 identblue(void)
  981 {
  982 
  983         trap_by_rdmsr = 0;
  984 
  985         /*
  986          * Cyrix 486-class CPU does not support rdmsr instruction.
  987          * The rdmsr instruction generates invalid opcode fault, and exception
  988          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
  989          * bluetrap6() set the magic number to trap_by_rdmsr.
  990          */
  991         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
  992             GSEL(GCODE_SEL, SEL_KPL));
  993 
  994         /*
  995          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
  996          * In this case, rdmsr generates general protection fault, and
  997          * exception will be trapped by bluetrap13().
  998          */
  999         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
 1000             GSEL(GCODE_SEL, SEL_KPL));
 1001 
 1002         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 1003 
 1004         if (trap_by_rdmsr == 0xa8c1d)
 1005                 return IDENTBLUE_CYRIX486;
 1006         else if (trap_by_rdmsr == 0xa89c4)
 1007                 return IDENTBLUE_CYRIXM2;
 1008         return IDENTBLUE_IBMCPU;
 1009 }
 1010 
 1011 
 1012 /*
 1013  * identifycyrix() set lower 16 bits of cyrix_did as follows:
 1014  *
 1015  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
 1016  * +-------+-------+---------------+
 1017  * |  SID  |  RID  |   Device ID   |
 1018  * |    (DIR 1)    |    (DIR 0)    |
 1019  * +-------+-------+---------------+
 1020  */
 1021 static void
 1022 identifycyrix(void)
 1023 {
 1024         u_int   eflags;
 1025         int     ccr2_test = 0, dir_test = 0;
 1026         u_char  ccr2, ccr3;
 1027 
 1028         eflags = read_eflags();
 1029         disable_intr();
 1030 
 1031         ccr2 = read_cyrix_reg(CCR2);
 1032         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
 1033         read_cyrix_reg(CCR2);
 1034         if (read_cyrix_reg(CCR2) != ccr2)
 1035                 ccr2_test = 1;
 1036         write_cyrix_reg(CCR2, ccr2);
 1037 
 1038         ccr3 = read_cyrix_reg(CCR3);
 1039         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
 1040         read_cyrix_reg(CCR3);
 1041         if (read_cyrix_reg(CCR3) != ccr3)
 1042                 dir_test = 1;                                   /* CPU supports DIRs. */
 1043         write_cyrix_reg(CCR3, ccr3);
 1044 
 1045         if (dir_test) {
 1046                 /* Device ID registers are available. */
 1047                 cyrix_did = read_cyrix_reg(DIR1) << 8;
 1048                 cyrix_did += read_cyrix_reg(DIR0);
 1049         } else if (ccr2_test)
 1050                 cyrix_did = 0x0010;             /* 486S A-step */
 1051         else
 1052                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
 1053 
 1054         write_eflags(eflags);
 1055 }
 1056 
 1057 /* Update TSC freq with the value indicated by the caller. */
 1058 static void
 1059 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
 1060 {
 1061         /* If there was an error during the transition, don't do anything. */
 1062         if (status != 0)
 1063                 return;
 1064 
 1065         /* Total setting for this level gives the new frequency in MHz. */
 1066         hw_clockrate = level->total_set.freq;
 1067 }
 1068 
 1069 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
 1070     EVENTHANDLER_PRI_ANY);
 1071 
 1072 /*
 1073  * Final stage of CPU identification. -- Should I check TI?
 1074  */
 1075 void
 1076 finishidentcpu(void)
 1077 {
 1078         int     isblue = 0;
 1079         u_char  ccr3;
 1080         u_int   regs[4];
 1081 
 1082         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
 1083         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 1084             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 1085                 init_exthigh();
 1086                 if (cpu_exthigh >= 0x80000001) {
 1087                         do_cpuid(0x80000001, regs);
 1088                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 1089                         amd_feature2 = regs[2];
 1090                 }
 1091                 if (cpu_exthigh >= 0x80000008) {
 1092                         do_cpuid(0x80000008, regs);
 1093                         cpu_procinfo2 = regs[2];
 1094                 }
 1095         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 1096                 if (cpu == CPU_486) {
 1097                         /*
 1098                          * These conditions are equivalent to:
 1099                          *     - CPU does not support cpuid instruction.
 1100                          *     - Cyrix/IBM CPU is detected.
 1101                          */
 1102                         isblue = identblue();
 1103                         if (isblue == IDENTBLUE_IBMCPU) {
 1104                                 strcpy(cpu_vendor, "IBM");
 1105                                 cpu = CPU_BLUE;
 1106                                 return;
 1107                         }
 1108                 }
 1109                 switch (cpu_id & 0xf00) {
 1110                 case 0x600:
 1111                         /*
 1112                          * Cyrix's datasheet does not describe DIRs.
 1113                          * Therefor, I assume it does not have them
 1114                          * and use the result of the cpuid instruction.
 1115                          * XXX they seem to have it for now at least. -Peter
 1116                          */
 1117                         identifycyrix();
 1118                         cpu = CPU_M2;
 1119                         break;
 1120                 default:
 1121                         identifycyrix();
 1122                         /*
 1123                          * This routine contains a trick.
 1124                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 1125                          */
 1126                         switch (cyrix_did & 0x00f0) {
 1127                         case 0x00:
 1128                         case 0xf0:
 1129                                 cpu = CPU_486DLC;
 1130                                 break;
 1131                         case 0x10:
 1132                                 cpu = CPU_CY486DX;
 1133                                 break;
 1134                         case 0x20:
 1135                                 if ((cyrix_did & 0x000f) < 8)
 1136                                         cpu = CPU_M1;
 1137                                 else
 1138                                         cpu = CPU_M1SC;
 1139                                 break;
 1140                         case 0x30:
 1141                                 cpu = CPU_M1;
 1142                                 break;
 1143                         case 0x40:
 1144                                 /* MediaGX CPU */
 1145                                 cpu = CPU_M1SC;
 1146                                 break;
 1147                         default:
 1148                                 /* M2 and later CPUs are treated as M2. */
 1149                                 cpu = CPU_M2;
 1150 
 1151                                 /*
 1152                                  * enable cpuid instruction.
 1153                                  */
 1154                                 ccr3 = read_cyrix_reg(CCR3);
 1155                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 1156                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 1157                                 write_cyrix_reg(CCR3, ccr3);
 1158 
 1159                                 do_cpuid(0, regs);
 1160                                 cpu_high = regs[0];     /* eax */
 1161                                 do_cpuid(1, regs);
 1162                                 cpu_id = regs[0];       /* eax */
 1163                                 cpu_feature = regs[3];  /* edx */
 1164                                 break;
 1165                         }
 1166                 }
 1167         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 1168                 /*
 1169                  * There are BlueLightning CPUs that do not change
 1170                  * undefined flags by dividing 5 by 2.  In this case,
 1171                  * the CPU identification routine in locore.s leaves
 1172                  * cpu_vendor null string and puts CPU_486 into the
 1173                  * cpu.
 1174                  */
 1175                 isblue = identblue();
 1176                 if (isblue == IDENTBLUE_IBMCPU) {
 1177                         strcpy(cpu_vendor, "IBM");
 1178                         cpu = CPU_BLUE;
 1179                         return;
 1180                 }
 1181         }
 1182 }
 1183 
 1184 static void
 1185 print_AMD_assoc(int i)
 1186 {
 1187         if (i == 255)
 1188                 printf(", fully associative\n");
 1189         else
 1190                 printf(", %d-way associative\n", i);
 1191 }
 1192 
 1193 static void
 1194 print_AMD_info(void)
 1195 {
 1196         quad_t amd_whcr;
 1197 
 1198         if (cpu_exthigh >= 0x80000005) {
 1199                 u_int regs[4];
 1200 
 1201                 do_cpuid(0x80000005, regs);
 1202                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
 1203                 print_AMD_assoc(regs[1] >> 24);
 1204                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
 1205                 print_AMD_assoc((regs[1] >> 8) & 0xff);
 1206                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
 1207                 printf(", %d bytes/line", regs[2] & 0xff);
 1208                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 1209                 print_AMD_assoc((regs[2] >> 16) & 0xff);
 1210                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 1211                 printf(", %d bytes/line", regs[3] & 0xff);
 1212                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 1213                 print_AMD_assoc((regs[3] >> 16) & 0xff);
 1214                 if (cpu_exthigh >= 0x80000006) {        /* K6-III only */
 1215                         do_cpuid(0x80000006, regs);
 1216                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
 1217                         printf(", %d bytes/line", regs[2] & 0xff);
 1218                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 1219                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
 1220                 }
 1221         }
 1222         if (((cpu_id & 0xf00) == 0x500)
 1223             && (((cpu_id & 0x0f0) > 0x80)
 1224                 || (((cpu_id & 0x0f0) == 0x80)
 1225                     && (cpu_id & 0x00f) > 0x07))) {
 1226                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
 1227                 amd_whcr = rdmsr(0xc0000082);
 1228                 if (!(amd_whcr & (0x3ff << 22))) {
 1229                         printf("Write Allocate Disable\n");
 1230                 } else {
 1231                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1232                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
 1233                         printf("Write Allocate 15-16M bytes: %s\n",
 1234                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
 1235                 }
 1236         } else if (((cpu_id & 0xf00) == 0x500)
 1237                    && ((cpu_id & 0x0f0) > 0x50)) {
 1238                 /* K6, K6-2(old core) */
 1239                 amd_whcr = rdmsr(0xc0000082);
 1240                 if (!(amd_whcr & (0x7f << 1))) {
 1241                         printf("Write Allocate Disable\n");
 1242                 } else {
 1243                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1244                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
 1245                         printf("Write Allocate 15-16M bytes: %s\n",
 1246                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
 1247                         printf("Hardware Write Allocate Control: %s\n",
 1248                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
 1249                 }
 1250         }
 1251 }
 1252 
 1253 static void
 1254 print_INTEL_info(void)
 1255 {
 1256         u_int regs[4];
 1257         u_int rounds, regnum;
 1258         u_int nwaycode, nway;
 1259 
 1260         if (cpu_high >= 2) {
 1261                 rounds = 0;
 1262                 do {
 1263                         do_cpuid(0x2, regs);
 1264                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
 1265                                 break;  /* we have a buggy CPU */
 1266 
 1267                         for (regnum = 0; regnum <= 3; ++regnum) {
 1268                                 if (regs[regnum] & (1<<31))
 1269                                         continue;
 1270                                 if (regnum != 0)
 1271                                         print_INTEL_TLB(regs[regnum] & 0xff);
 1272                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
 1273                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
 1274                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
 1275                         }
 1276                 } while (--rounds > 0);
 1277         }
 1278 
 1279         if (cpu_exthigh >= 0x80000006) {
 1280                 do_cpuid(0x80000006, regs);
 1281                 nwaycode = (regs[2] >> 12) & 0x0f;
 1282                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
 1283                         nway = 1 << (nwaycode / 2);
 1284                 else
 1285                         nway = 0;
 1286                 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
 1287                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
 1288         }
 1289 
 1290         printf("\n");
 1291 }
 1292 
 1293 static void
 1294 print_INTEL_TLB(u_int data)
 1295 {
 1296         switch (data) {
 1297         case 0x0:
 1298         case 0x40:
 1299         default:
 1300                 break;
 1301         case 0x1:
 1302                 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
 1303                 break;
 1304         case 0x2:
 1305                 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
 1306                 break;
 1307         case 0x3:
 1308                 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
 1309                 break;
 1310         case 0x4:
 1311                 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
 1312                 break;
 1313         case 0x6:
 1314                 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
 1315                 break;
 1316         case 0x8:
 1317                 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
 1318                 break;
 1319         case 0xa:
 1320                 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
 1321                 break;
 1322         case 0xc:
 1323                 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
 1324                 break;
 1325         case 0x22:
 1326                 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
 1327                 break;
 1328         case 0x23:
 1329                 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
 1330                 break;
 1331         case 0x25:
 1332                 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
 1333                 break;
 1334         case 0x29:
 1335                 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
 1336                 break;
 1337         case 0x2c:
 1338                 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
 1339                 break;
 1340         case 0x30:
 1341                 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
 1342                 break;
 1343         case 0x39:
 1344                 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
 1345                 break;
 1346         case 0x3b:
 1347                 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
 1348                 break;
 1349         case 0x3c:
 1350                 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
 1351                 break;
 1352         case 0x41:
 1353                 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
 1354                 break;
 1355         case 0x42:
 1356                 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
 1357                 break;
 1358         case 0x43:
 1359                 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
 1360                 break;
 1361         case 0x44:
 1362                 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
 1363                 break;
 1364         case 0x45:
 1365                 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
 1366                 break;
 1367         case 0x46:
 1368                 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
 1369                 break;
 1370         case 0x47:
 1371                 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
 1372                 break;
 1373         case 0x50:
 1374                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
 1375                 break;
 1376         case 0x51:
 1377                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
 1378                 break;
 1379         case 0x52:
 1380                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
 1381                 break;
 1382         case 0x5b:
 1383                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
 1384                 break;
 1385         case 0x5c:
 1386                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
 1387                 break;
 1388         case 0x5d:
 1389                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
 1390                 break;
 1391         case 0x60:
 1392                 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
 1393                 break;
 1394         case 0x66:
 1395                 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
 1396                 break;
 1397         case 0x67:
 1398                 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
 1399                 break;
 1400         case 0x68:
 1401                 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
 1402                 break;
 1403         case 0x70:
 1404                 printf("\nTrace cache: 12K-uops, 8-way set associative");
 1405                 break;
 1406         case 0x71:
 1407                 printf("\nTrace cache: 16K-uops, 8-way set associative");
 1408                 break;
 1409         case 0x72:
 1410                 printf("\nTrace cache: 32K-uops, 8-way set associative");
 1411                 break;
 1412         case 0x78:
 1413                 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
 1414                 break;
 1415         case 0x79:
 1416                 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
 1417                 break;
 1418         case 0x7a:
 1419                 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
 1420                 break;
 1421         case 0x7b:
 1422                 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
 1423                 break;
 1424         case 0x7c:
 1425                 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
 1426                 break;
 1427         case 0x7d:
 1428                 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
 1429                 break;
 1430         case 0x7f:
 1431                 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
 1432                 break;
 1433         case 0x82:
 1434                 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
 1435                 break;
 1436         case 0x83:
 1437                 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
 1438                 break;
 1439         case 0x84:
 1440                 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
 1441                 break;
 1442         case 0x85:
 1443                 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
 1444                 break;
 1445         case 0x86:
 1446                 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
 1447                 break;
 1448         case 0x87:
 1449                 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
 1450                 break;
 1451         case 0xb0:
 1452                 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
 1453                 break;
 1454         case 0xb3:
 1455                 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
 1456                 break;
 1457         }
 1458 }
 1459 
 1460 
 1461 static void
 1462 setPQL2_AMD(int *const size, int *const ways)
 1463 {
 1464         if (cpu_exthigh >= 0x80000006) {
 1465                 u_int regs[4];
 1466 
 1467                 do_cpuid(0x80000006, regs);
 1468                 *size = regs[2] >> 16;
 1469                 *ways = (regs[2] >> 12) & 0x0f;
 1470         }
 1471 }
 1472 
 1473 
 1474 static void
 1475 setPQL2_INTEL(int *const size, int *const ways)
 1476 {
 1477         u_int rounds, regnum;
 1478         u_int regs[4];
 1479         u_int nwaycode;
 1480 
 1481         if (cpu_high >= 2) {
 1482                 rounds = 0;
 1483                 do {
 1484                         do_cpuid(0x2, regs);
 1485                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
 1486                                 break;  /* we have a buggy CPU */
 1487 
 1488                         for (regnum = 0; regnum <= 3; ++regnum) {
 1489                                 if (regs[regnum] & (1<<31))
 1490                                         continue;
 1491                                 if (regnum != 0)
 1492                                         get_INTEL_TLB(regs[regnum] & 0xff,
 1493                                             size, ways);
 1494                                 get_INTEL_TLB((regs[regnum] >> 8) & 0xff,
 1495                                     size, ways);
 1496                                 get_INTEL_TLB((regs[regnum] >> 16) & 0xff,
 1497                                     size, ways);
 1498                                 get_INTEL_TLB((regs[regnum] >> 24) & 0xff,
 1499                                     size, ways);
 1500                         }
 1501                 } while (--rounds > 0);
 1502         }
 1503 
 1504         if (cpu_exthigh >= 0x80000006) {
 1505                 do_cpuid(0x80000006, regs);
 1506                 if (*size < ((regs[2] >> 16) & 0xffff)) {
 1507                         *size = (regs[2] >> 16) & 0xffff;
 1508                         nwaycode = (regs[2] >> 12) & 0x0f;
 1509                         if (nwaycode >= 0x02 && nwaycode <= 0x08)
 1510                                 *ways = 1 << (nwaycode / 2);
 1511                         else
 1512                                 *ways = 0;
 1513                 }
 1514         }
 1515 }
 1516 
 1517 static void
 1518 get_INTEL_TLB(u_int data, int *const size, int *const ways)
 1519 {
 1520         switch (data) {
 1521         default:
 1522                 break;
 1523         case 0x22:
 1524                 /* 3rd-level cache: 512 KB, 4-way set associative,
 1525                  * sectored cache, 64 byte line size */
 1526                 if (*size < 512) {
 1527                         *size = 512;
 1528                         *ways = 4;
 1529                 }
 1530                 break;
 1531         case 0x23:
 1532                 /* 3rd-level cache: 1 MB, 8-way set associative,
 1533                  * sectored cache, 64 byte line size */
 1534                 if (*size < 1024) {
 1535                         *size = 1024;
 1536                         *ways = 8;
 1537                 }
 1538                 break;
 1539         case 0x25:
 1540                 /* 3rd-level cache: 2 MB, 8-way set associative,
 1541                  * sectored cache, 64 byte line size */
 1542                 if (*size < 2048) {
 1543                         *size = 2048;
 1544                         *ways = 8;
 1545                 }
 1546                 break;
 1547         case 0x29:
 1548                 /* 3rd-level cache: 4 MB, 8-way set associative,
 1549                  * sectored cache, 64 byte line size */
 1550                 if (*size < 4096) {
 1551                         *size = 4096;
 1552                         *ways = 8;
 1553                 }
 1554                 break;
 1555         case 0x39:
 1556                 /* 2nd-level cache: 128 KB, 4-way set associative,
 1557                  * sectored cache, 64 byte line size */
 1558                 if (*size < 128) {
 1559                         *size = 128;
 1560                         *ways = 4;
 1561                 }
 1562                 break;
 1563         case 0x3b:
 1564                 /* 2nd-level cache: 128 KB, 2-way set associative,
 1565                  * sectored cache, 64 byte line size */
 1566                 if (*size < 128) {
 1567                         *size = 128;
 1568                         *ways = 2;
 1569                 }
 1570                 break;
 1571         case 0x3c:
 1572                 /* 2nd-level cache: 256 KB, 4-way set associative,
 1573                  * sectored cache, 64 byte line size */
 1574                 if (*size < 256) {
 1575                         *size = 256;
 1576                         *ways = 4;
 1577                 }
 1578                 break;
 1579         case 0x41:
 1580                 /* 2nd-level cache: 128 KB, 4-way set associative,
 1581                  * 32 byte line size */
 1582                 if (*size < 128) {
 1583                         *size = 128;
 1584                         *ways = 4;
 1585                 }
 1586                 break;
 1587         case 0x42:
 1588                 /* 2nd-level cache: 256 KB, 4-way set associative,
 1589                  * 32 byte line size */
 1590                 if (*size < 256) {
 1591                         *size = 256;
 1592                         *ways = 4;
 1593                 }
 1594                 break;
 1595         case 0x43:
 1596                 /* 2nd-level cache: 512 KB, 4-way set associative,
 1597                  * 32 byte line size */
 1598                 if (*size < 512) {
 1599                         *size = 512;
 1600                         *ways = 4;
 1601                 }
 1602                 break;
 1603         case 0x44:
 1604                 /* 2nd-level cache: 1 MB, 4-way set associative,
 1605                  * 32 byte line size */
 1606                 if (*size < 1024) {
 1607                         *size = 1024;
 1608                         *ways = 4;
 1609                 }
 1610                 break;
 1611         case 0x45:
 1612                 /* 2nd-level cache: 2 MB, 4-way set associative,
 1613                  * 32 byte line size */
 1614                 if (*size < 2048) {
 1615                         *size = 2048;
 1616                         *ways = 4;
 1617                 }
 1618                 break;
 1619         case 0x46:
 1620                 /* 3rd-level cache: 4 MB, 4-way set associative,
 1621                  * 64 byte line size */
 1622                 if (*size < 4096) {
 1623                         *size = 4096;
 1624                         *ways = 4;
 1625                 }
 1626                 break;
 1627         case 0x47:
 1628                 /* 3rd-level cache: 8 MB, 8-way set associative,
 1629                  * 64 byte line size */
 1630                 if (*size < 8192) {
 1631                         *size = 8192;
 1632                         *ways = 8;
 1633                 }
 1634                 break;
 1635         case 0x78:
 1636                 /* 2nd-level cache: 1 MB, 4-way set associative,
 1637                  * 64-byte line size */
 1638                 if (*size < 1024) {
 1639                         *size = 1024;
 1640                         *ways = 4;
 1641                 }
 1642                 break;
 1643         case 0x79:
 1644                 /* 2nd-level cache: 128 KB, 8-way set associative,
 1645                  * sectored cache, 64 byte line size */
 1646                 if (*size < 128) {
 1647                         *size = 128;
 1648                         *ways = 8;
 1649                 }
 1650                 break;
 1651         case 0x7a:
 1652                 /* 2nd-level cache: 256 KB, 8-way set associative,
 1653                  * sectored cache, 64 byte line size */
 1654                 if (*size < 256) {
 1655                         *size = 256;
 1656                         *ways = 8;
 1657                 }
 1658                 break;
 1659         case 0x7b:
 1660                 /* 2nd-level cache: 512 KB, 8-way set associative,
 1661                  * sectored cache, 64 byte line size */
 1662                 if (*size < 512) {
 1663                         *size = 512;
 1664                         *ways = 8;
 1665                 }
 1666                 break;
 1667         case 0x7c:
 1668                 /* 2nd-level cache: 1 MB, 8-way set associative,
 1669                  * sectored cache, 64 byte line size */
 1670                 if (*size < 1024) {
 1671                         *size = 1024;
 1672                         *ways = 8;
 1673                 }
 1674                 break;
 1675         case 0x7d:
 1676                 /* 2nd-level cache: 2 MB, 8-way set associative,
 1677                  * 64-byte line size */
 1678                 if (*size < 2048) {
 1679                         *size = 2048;
 1680                         *ways = 8;
 1681                 }
 1682                 break;
 1683         case 0x7f:
 1684                 /* 2nd-level cache: 512 KB, 2-way set associative,
 1685                  * 64-byte line size */
 1686                 if (*size < 512) {
 1687                         *size = 512;
 1688                         *ways = 2;
 1689                 }
 1690                 break;
 1691         case 0x82:
 1692                 /* 2nd-level cache: 256 KB, 8-way set associative,
 1693                  * 32 byte line size */
 1694                 if (*size < 256) {
 1695                         *size = 256;
 1696                         *ways = 8;
 1697                 }
 1698                 break;
 1699         case 0x83:
 1700                 /* 2nd-level cache: 512 KB, 8-way set associative,
 1701                  * 32 byte line size */
 1702                 if (*size < 512) {
 1703                         *size = 512;
 1704                         *ways = 8;
 1705                 }
 1706                 break;
 1707         case 0x84:
 1708                 /* 2nd-level cache: 1 MB, 8-way set associative,
 1709                  * 32 byte line size */
 1710                 if (*size < 1024) {
 1711                         *size = 1024;
 1712                         *ways = 8;
 1713                 }
 1714                 break;
 1715         case 0x85:
 1716                 /* 2nd-level cache: 2 MB, 8-way set associative,
 1717                  * 32 byte line size */
 1718                 if (*size < 2048) {
 1719                         *size = 2048;
 1720                         *ways = 8;
 1721                 }
 1722                 break;
 1723         case 0x86:
 1724                 /* 2nd-level cache: 512 KB, 4-way set associative,
 1725                  * 64 byte line size */
 1726                 if (*size < 512) {
 1727                         *size = 512;
 1728                         *ways = 4;
 1729                 }
 1730                 break;
 1731         case 0x87:
 1732                 /* 2nd-level cache: 1 MB, 8-way set associative,
 1733                  * 64 byte line size */
 1734                 if (*size < 1024) {
 1735                         *size = 512;
 1736                         *ways = 8;
 1737                 }
 1738                 break;
 1739         }
 1740 }
 1741 
 1742 void
 1743 setPQL2(int *const size, int *const ways)
 1744 {
 1745         /* make sure the cpu_exthigh variable is initialized */
 1746         init_exthigh();
 1747 
 1748         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
 1749                 setPQL2_AMD(size, ways);
 1750         else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
 1751                 setPQL2_INTEL(size, ways);
 1752 }
 1753 
 1754 static void
 1755 print_transmeta_info(void)
 1756 {
 1757         u_int regs[4], nreg = 0;
 1758 
 1759         do_cpuid(0x80860000, regs);
 1760         nreg = regs[0];
 1761         if (nreg >= 0x80860001) {
 1762                 do_cpuid(0x80860001, regs);
 1763                 printf("  Processor revision %u.%u.%u.%u\n",
 1764                        (regs[1] >> 24) & 0xff,
 1765                        (regs[1] >> 16) & 0xff,
 1766                        (regs[1] >> 8) & 0xff,
 1767                        regs[1] & 0xff);
 1768         }
 1769         if (nreg >= 0x80860002) {
 1770                 do_cpuid(0x80860002, regs);
 1771                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
 1772                        (regs[1] >> 24) & 0xff,
 1773                        (regs[1] >> 16) & 0xff,
 1774                        (regs[1] >> 8) & 0xff,
 1775                        regs[1] & 0xff,
 1776                        regs[2]);
 1777         }
 1778         if (nreg >= 0x80860006) {
 1779                 char info[65];
 1780                 do_cpuid(0x80860003, (u_int*) &info[0]);
 1781                 do_cpuid(0x80860004, (u_int*) &info[16]);
 1782                 do_cpuid(0x80860005, (u_int*) &info[32]);
 1783                 do_cpuid(0x80860006, (u_int*) &info[48]);
 1784                 info[64] = 0;
 1785                 printf("  %s\n", info);
 1786         }
 1787 }
 1788 
 1789 static void
 1790 print_via_padlock_info(void)
 1791 {
 1792         u_int regs[4];
 1793 
 1794         /* Check for supported models. */
 1795         switch (cpu_id & 0xff0) {
 1796         case 0x690:
 1797                 if ((cpu_id & 0xf) < 3)
 1798                         return;
 1799         case 0x6a0:
 1800         case 0x6d0:
 1801                 break;
 1802         default:
 1803                 return;
 1804         }
 1805         
 1806         do_cpuid(0xc0000000, regs);
 1807         if (regs[0] >= 0xc0000001)
 1808                 do_cpuid(0xc0000001, regs);
 1809         else
 1810                 return;
 1811 
 1812         printf("\n  VIA Padlock Features=0x%b", regs[3],
 1813         "\020"
 1814         "\003RNG"               /* RNG */
 1815         "\007AES"               /* ACE */
 1816         "\011AES-CTR"           /* ACE2 */
 1817         "\013SHA1,SHA256"       /* PHE */
 1818         "\015RSA"               /* PMM */
 1819         );
 1820 }

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