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sys/i386/i386/identcpu.c
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1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/md_var.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 63 #define IDENTBLUE_CYRIX486 0 64 #define IDENTBLUE_IBMCPU 1 65 #define IDENTBLUE_CYRIXM2 2 66 67 /* XXX - should be in header file: */ 68 void printcpuinfo(void); 69 void finishidentcpu(void); 70 void earlysetcpuclass(void); 71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 72 void enable_K5_wt_alloc(void); 73 void enable_K6_wt_alloc(void); 74 void enable_K6_2_wt_alloc(void); 75 #endif 76 void panicifcpuunsupported(void); 77 78 static void identifycyrix(void); 79 static void init_exthigh(void); 80 void setPQL2(int *const size, int *const ways); 81 static void setPQL2_AMD(int *const size, int *const ways); 82 static void setPQL2_INTEL(int *const size, int *const ways); 83 static void get_INTEL_TLB(u_int data, int *const size, int *const ways); 84 static void print_AMD_info(void); 85 static void print_INTEL_info(void); 86 static void print_INTEL_TLB(u_int data); 87 static void print_AMD_assoc(int i); 88 static void print_transmeta_info(void); 89 static void print_via_padlock_info(void); 90 91 int cpu_class; 92 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 93 u_int cyrix_did; /* Device ID of Cyrix CPU */ 94 char machine[] = MACHINE; 95 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 96 machine, 0, "Machine class"); 97 98 static char cpu_model[128]; 99 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 100 cpu_model, 0, "Machine model"); 101 102 static int hw_clockrate; 103 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 104 &hw_clockrate, 0, "CPU instruction clock rate"); 105 106 static char cpu_brand[48]; 107 108 #define MAX_BRAND_INDEX 8 109 110 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 111 NULL, /* No brand */ 112 "Intel Celeron", 113 "Intel Pentium III", 114 "Intel Pentium III Xeon", 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 "Intel Pentium 4" 120 }; 121 122 static struct { 123 char *cpu_name; 124 int cpu_class; 125 } i386_cpus[] = { 126 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 127 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 128 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 129 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 130 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 131 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 132 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 133 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 134 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 135 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 136 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 137 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 138 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 139 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 140 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 141 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 142 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 143 }; 144 145 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 146 int has_f00f_bug = 0; /* Initialized so that it can be patched. */ 147 #endif 148 149 static void 150 init_exthigh(void) 151 { 152 static int done = 0; 153 u_int regs[4]; 154 155 if (done == 0) { 156 if (cpu_high > 0 && 157 (strcmp(cpu_vendor, "GenuineIntel") == 0 || 158 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 159 strcmp(cpu_vendor, "GenuineTMx86") == 0 || 160 strcmp(cpu_vendor, "TransmetaCPU") == 0 || 161 strcmp(cpu_vendor, "CentaurHauls") == 0 || 162 strcmp(cpu_vendor, "Geode by NSC") == 0)) { 163 do_cpuid(0x80000000, regs); 164 if (regs[0] >= 0x80000000) 165 cpu_exthigh = regs[0]; 166 } 167 168 done = 1; 169 } 170 } 171 172 void 173 printcpuinfo(void) 174 { 175 u_int regs[4], i; 176 char *brand; 177 178 cpu_class = i386_cpus[cpu].cpu_class; 179 printf("CPU: "); 180 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); 181 182 /* Check for extended CPUID information and a processor name. */ 183 init_exthigh(); 184 if (cpu_exthigh >= 0x80000004) { 185 brand = cpu_brand; 186 for (i = 0x80000002; i < 0x80000005; i++) { 187 do_cpuid(i, regs); 188 memcpy(brand, regs, sizeof(regs)); 189 brand += sizeof(regs); 190 } 191 } 192 193 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 194 if ((cpu_id & 0xf00) > 0x300) { 195 u_int brand_index; 196 u_int model; 197 198 cpu_model[0] = '\0'; 199 200 switch (cpu_id & 0x3000) { 201 case 0x1000: 202 strcpy(cpu_model, "Overdrive "); 203 break; 204 case 0x2000: 205 strcpy(cpu_model, "Dual "); 206 break; 207 } 208 209 switch (cpu_id & 0xf00) { 210 case 0x400: 211 strcat(cpu_model, "i486 "); 212 /* Check the particular flavor of 486 */ 213 switch (cpu_id & 0xf0) { 214 case 0x00: 215 case 0x10: 216 strcat(cpu_model, "DX"); 217 break; 218 case 0x20: 219 strcat(cpu_model, "SX"); 220 break; 221 case 0x30: 222 strcat(cpu_model, "DX2"); 223 break; 224 case 0x40: 225 strcat(cpu_model, "SL"); 226 break; 227 case 0x50: 228 strcat(cpu_model, "SX2"); 229 break; 230 case 0x70: 231 strcat(cpu_model, 232 "DX2 Write-Back Enhanced"); 233 break; 234 case 0x80: 235 strcat(cpu_model, "DX4"); 236 break; 237 } 238 break; 239 case 0x500: 240 /* Check the particular flavor of 586 */ 241 strcat(cpu_model, "Pentium"); 242 switch (cpu_id & 0xf0) { 243 case 0x00: 244 strcat(cpu_model, " A-step"); 245 break; 246 case 0x10: 247 strcat(cpu_model, "/P5"); 248 break; 249 case 0x20: 250 strcat(cpu_model, "/P54C"); 251 break; 252 case 0x30: 253 strcat(cpu_model, "/P54T Overdrive"); 254 break; 255 case 0x40: 256 strcat(cpu_model, "/P55C"); 257 break; 258 case 0x70: 259 strcat(cpu_model, "/P54C"); 260 break; 261 case 0x80: 262 strcat(cpu_model, "/P55C (quarter-micron)"); 263 break; 264 default: 265 /* nothing */ 266 break; 267 } 268 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 269 /* 270 * XXX - If/when Intel fixes the bug, this 271 * should also check the version of the 272 * CPU, not just that it's a Pentium. 273 */ 274 has_f00f_bug = 1; 275 #endif 276 break; 277 case 0x600: 278 /* Check the particular flavor of 686 */ 279 switch (cpu_id & 0xf0) { 280 case 0x00: 281 strcat(cpu_model, "Pentium Pro A-step"); 282 break; 283 case 0x10: 284 strcat(cpu_model, "Pentium Pro"); 285 break; 286 case 0x30: 287 case 0x50: 288 case 0x60: 289 strcat(cpu_model, 290 "Pentium II/Pentium II Xeon/Celeron"); 291 cpu = CPU_PII; 292 break; 293 case 0x70: 294 case 0x80: 295 case 0xa0: 296 case 0xb0: 297 strcat(cpu_model, 298 "Pentium III/Pentium III Xeon/Celeron"); 299 cpu = CPU_PIII; 300 break; 301 default: 302 strcat(cpu_model, "Unknown 80686"); 303 break; 304 } 305 break; 306 case 0xf00: 307 strcat(cpu_model, "Pentium 4"); 308 cpu = CPU_P4; 309 model = (cpu_id & 0x0f0) >> 4; 310 if (model == 3 || model == 4 || model == 6) { 311 uint64_t tmp; 312 313 tmp = rdmsr(MSR_IA32_MISC_ENABLE); 314 wrmsr(MSR_IA32_MISC_ENABLE, 315 tmp & ~(1LL << 22)); 316 do_cpuid(0, regs); 317 cpu_high = regs[0]; 318 } 319 break; 320 default: 321 strcat(cpu_model, "unknown"); 322 break; 323 } 324 325 /* 326 * If we didn't get a brand name from the extended 327 * CPUID, try to look it up in the brand table. 328 */ 329 if (cpu_high > 0 && *cpu_brand == '\0') { 330 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 331 if (brand_index <= MAX_BRAND_INDEX && 332 cpu_brandtable[brand_index] != NULL) 333 strcpy(cpu_brand, 334 cpu_brandtable[brand_index]); 335 } 336 } 337 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 338 /* 339 * Values taken from AMD Processor Recognition 340 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 341 * (also describes ``Features'' encodings. 342 */ 343 strcpy(cpu_model, "AMD "); 344 switch (cpu_id & 0xFF0) { 345 case 0x410: 346 strcat(cpu_model, "Standard Am486DX"); 347 break; 348 case 0x430: 349 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 350 break; 351 case 0x470: 352 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 353 break; 354 case 0x480: 355 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 356 break; 357 case 0x490: 358 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 359 break; 360 case 0x4E0: 361 strcat(cpu_model, "Am5x86 Write-Through"); 362 break; 363 case 0x4F0: 364 strcat(cpu_model, "Am5x86 Write-Back"); 365 break; 366 case 0x500: 367 strcat(cpu_model, "K5 model 0"); 368 tsc_is_broken = 1; 369 break; 370 case 0x510: 371 strcat(cpu_model, "K5 model 1"); 372 break; 373 case 0x520: 374 strcat(cpu_model, "K5 PR166 (model 2)"); 375 break; 376 case 0x530: 377 strcat(cpu_model, "K5 PR200 (model 3)"); 378 break; 379 case 0x560: 380 strcat(cpu_model, "K6"); 381 break; 382 case 0x570: 383 strcat(cpu_model, "K6 266 (model 1)"); 384 break; 385 case 0x580: 386 strcat(cpu_model, "K6-2"); 387 break; 388 case 0x590: 389 strcat(cpu_model, "K6-III"); 390 break; 391 case 0x5a0: 392 strcat(cpu_model, "Geode LX"); 393 /* 394 * Make sure the TSC runs through suspension, 395 * otherwise we can't use it as timecounter 396 */ 397 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 398 break; 399 default: 400 strcat(cpu_model, "Unknown"); 401 break; 402 } 403 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 404 if ((cpu_id & 0xf00) == 0x500) { 405 if (((cpu_id & 0x0f0) > 0) 406 && ((cpu_id & 0x0f0) < 0x60) 407 && ((cpu_id & 0x00f) > 3)) 408 enable_K5_wt_alloc(); 409 else if (((cpu_id & 0x0f0) > 0x80) 410 || (((cpu_id & 0x0f0) == 0x80) 411 && (cpu_id & 0x00f) > 0x07)) 412 enable_K6_2_wt_alloc(); 413 else if ((cpu_id & 0x0f0) > 0x50) 414 enable_K6_wt_alloc(); 415 } 416 #endif 417 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 418 strcpy(cpu_model, "Cyrix "); 419 switch (cpu_id & 0xff0) { 420 case 0x440: 421 strcat(cpu_model, "MediaGX"); 422 break; 423 case 0x520: 424 strcat(cpu_model, "6x86"); 425 break; 426 case 0x540: 427 cpu_class = CPUCLASS_586; 428 strcat(cpu_model, "GXm"); 429 break; 430 case 0x600: 431 strcat(cpu_model, "6x86MX"); 432 break; 433 default: 434 /* 435 * Even though CPU supports the cpuid 436 * instruction, it can be disabled. 437 * Therefore, this routine supports all Cyrix 438 * CPUs. 439 */ 440 switch (cyrix_did & 0xf0) { 441 case 0x00: 442 switch (cyrix_did & 0x0f) { 443 case 0x00: 444 strcat(cpu_model, "486SLC"); 445 break; 446 case 0x01: 447 strcat(cpu_model, "486DLC"); 448 break; 449 case 0x02: 450 strcat(cpu_model, "486SLC2"); 451 break; 452 case 0x03: 453 strcat(cpu_model, "486DLC2"); 454 break; 455 case 0x04: 456 strcat(cpu_model, "486SRx"); 457 break; 458 case 0x05: 459 strcat(cpu_model, "486DRx"); 460 break; 461 case 0x06: 462 strcat(cpu_model, "486SRx2"); 463 break; 464 case 0x07: 465 strcat(cpu_model, "486DRx2"); 466 break; 467 case 0x08: 468 strcat(cpu_model, "486SRu"); 469 break; 470 case 0x09: 471 strcat(cpu_model, "486DRu"); 472 break; 473 case 0x0a: 474 strcat(cpu_model, "486SRu2"); 475 break; 476 case 0x0b: 477 strcat(cpu_model, "486DRu2"); 478 break; 479 default: 480 strcat(cpu_model, "Unknown"); 481 break; 482 } 483 break; 484 case 0x10: 485 switch (cyrix_did & 0x0f) { 486 case 0x00: 487 strcat(cpu_model, "486S"); 488 break; 489 case 0x01: 490 strcat(cpu_model, "486S2"); 491 break; 492 case 0x02: 493 strcat(cpu_model, "486Se"); 494 break; 495 case 0x03: 496 strcat(cpu_model, "486S2e"); 497 break; 498 case 0x0a: 499 strcat(cpu_model, "486DX"); 500 break; 501 case 0x0b: 502 strcat(cpu_model, "486DX2"); 503 break; 504 case 0x0f: 505 strcat(cpu_model, "486DX4"); 506 break; 507 default: 508 strcat(cpu_model, "Unknown"); 509 break; 510 } 511 break; 512 case 0x20: 513 if ((cyrix_did & 0x0f) < 8) 514 strcat(cpu_model, "6x86"); /* Where did you get it? */ 515 else 516 strcat(cpu_model, "5x86"); 517 break; 518 case 0x30: 519 strcat(cpu_model, "6x86"); 520 break; 521 case 0x40: 522 if ((cyrix_did & 0xf000) == 0x3000) { 523 cpu_class = CPUCLASS_586; 524 strcat(cpu_model, "GXm"); 525 } else 526 strcat(cpu_model, "MediaGX"); 527 break; 528 case 0x50: 529 strcat(cpu_model, "6x86MX"); 530 break; 531 case 0xf0: 532 switch (cyrix_did & 0x0f) { 533 case 0x0d: 534 strcat(cpu_model, "Overdrive CPU"); 535 break; 536 case 0x0e: 537 strcpy(cpu_model, "Texas Instruments 486SXL"); 538 break; 539 case 0x0f: 540 strcat(cpu_model, "486SLC/DLC"); 541 break; 542 default: 543 strcat(cpu_model, "Unknown"); 544 break; 545 } 546 break; 547 default: 548 strcat(cpu_model, "Unknown"); 549 break; 550 } 551 break; 552 } 553 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) { 554 strcpy(cpu_model, "Rise "); 555 switch (cpu_id & 0xff0) { 556 case 0x500: 557 strcat(cpu_model, "mP6"); 558 break; 559 default: 560 strcat(cpu_model, "Unknown"); 561 } 562 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { 563 switch (cpu_id & 0xff0) { 564 case 0x540: 565 strcpy(cpu_model, "IDT WinChip C6"); 566 tsc_is_broken = 1; 567 break; 568 case 0x580: 569 strcpy(cpu_model, "IDT WinChip 2"); 570 break; 571 case 0x660: 572 strcpy(cpu_model, "VIA C3 Samuel"); 573 break; 574 case 0x670: 575 if (cpu_id & 0x8) 576 strcpy(cpu_model, "VIA C3 Ezra"); 577 else 578 strcpy(cpu_model, "VIA C3 Samuel 2"); 579 break; 580 case 0x680: 581 strcpy(cpu_model, "VIA C3 Ezra-T"); 582 break; 583 case 0x690: 584 strcpy(cpu_model, "VIA C3 Nehemiah"); 585 break; 586 case 0x6a0: 587 case 0x6d0: 588 strcpy(cpu_model, "VIA C7 Esther"); 589 break; 590 default: 591 strcpy(cpu_model, "VIA/IDT Unknown"); 592 } 593 } else if (strcmp(cpu_vendor, "IBM") == 0) { 594 strcpy(cpu_model, "Blue Lightning CPU"); 595 } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) { 596 switch (cpu_id & 0xfff) { 597 case 0x540: 598 strcpy(cpu_model, "Geode SC1100"); 599 cpu = CPU_GEODE1100; 600 tsc_is_broken = 1; 601 break; 602 default: 603 strcpy(cpu_model, "Geode/NSC unknown"); 604 break; 605 } 606 } 607 608 /* 609 * Replace cpu_model with cpu_brand minus leading spaces if 610 * we have one. 611 */ 612 brand = cpu_brand; 613 while (*brand == ' ') 614 ++brand; 615 if (*brand != '\0') 616 strcpy(cpu_model, brand); 617 618 printf("%s (", cpu_model); 619 switch(cpu_class) { 620 case CPUCLASS_286: 621 printf("286"); 622 break; 623 case CPUCLASS_386: 624 printf("386"); 625 break; 626 #if defined(I486_CPU) 627 case CPUCLASS_486: 628 printf("486"); 629 bzero_vector = i486_bzero; 630 break; 631 #endif 632 #if defined(I586_CPU) 633 case CPUCLASS_586: 634 hw_clockrate = (tsc_freq + 5000) / 1000000; 635 printf("%jd.%02d-MHz ", 636 (intmax_t)(tsc_freq + 4999) / 1000000, 637 (u_int)((tsc_freq + 4999) / 10000) % 100); 638 printf("586"); 639 break; 640 #endif 641 #if defined(I686_CPU) 642 case CPUCLASS_686: 643 hw_clockrate = (tsc_freq + 5000) / 1000000; 644 printf("%jd.%02d-MHz ", 645 (intmax_t)(tsc_freq + 4999) / 1000000, 646 (u_int)((tsc_freq + 4999) / 10000) % 100); 647 printf("686"); 648 break; 649 #endif 650 default: 651 printf("Unknown"); /* will panic below... */ 652 } 653 printf("-class CPU)\n"); 654 if(*cpu_vendor) 655 printf(" Origin = \"%s\"",cpu_vendor); 656 if(cpu_id) 657 printf(" Id = 0x%x", cpu_id); 658 659 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 660 strcmp(cpu_vendor, "AuthenticAMD") == 0 || 661 strcmp(cpu_vendor, "GenuineTMx86") == 0 || 662 strcmp(cpu_vendor, "TransmetaCPU") == 0 || 663 strcmp(cpu_vendor, "RiseRiseRise") == 0 || 664 strcmp(cpu_vendor, "CentaurHauls") == 0 || 665 strcmp(cpu_vendor, "Geode by NSC") == 0 || 666 ((strcmp(cpu_vendor, "CyrixInstead") == 0) && 667 ((cpu_id & 0xf00) > 0x500))) { 668 printf(" Stepping = %u", cpu_id & 0xf); 669 if (strcmp(cpu_vendor, "CyrixInstead") == 0) 670 printf(" DIR=0x%04x", cyrix_did); 671 if (cpu_high > 0) { 672 u_int cmp = 1, htt = 1; 673 674 /* 675 * Here we should probably set up flags indicating 676 * whether or not various features are available. 677 * The interesting ones are probably VME, PSE, PAE, 678 * and PGE. The code already assumes without bothering 679 * to check that all CPUs >= Pentium have a TSC and 680 * MSRs. 681 */ 682 printf("\n Features=0x%b", cpu_feature, 683 "\020" 684 "\001FPU" /* Integral FPU */ 685 "\002VME" /* Extended VM86 mode support */ 686 "\003DE" /* Debugging Extensions (CR4.DE) */ 687 "\004PSE" /* 4MByte page tables */ 688 "\005TSC" /* Timestamp counter */ 689 "\006MSR" /* Machine specific registers */ 690 "\007PAE" /* Physical address extension */ 691 "\010MCE" /* Machine Check support */ 692 "\011CX8" /* CMPEXCH8 instruction */ 693 "\012APIC" /* SMP local APIC */ 694 "\013oldMTRR" /* Previous implementation of MTRR */ 695 "\014SEP" /* Fast System Call */ 696 "\015MTRR" /* Memory Type Range Registers */ 697 "\016PGE" /* PG_G (global bit) support */ 698 "\017MCA" /* Machine Check Architecture */ 699 "\020CMOV" /* CMOV instruction */ 700 "\021PAT" /* Page attributes table */ 701 "\022PSE36" /* 36 bit address space support */ 702 "\023PN" /* Processor Serial number */ 703 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 704 "\025<b20>" 705 "\026DTS" /* Debug Trace Store */ 706 "\027ACPI" /* ACPI support */ 707 "\030MMX" /* MMX instructions */ 708 "\031FXSR" /* FXSAVE/FXRSTOR */ 709 "\032SSE" /* Streaming SIMD Extensions */ 710 "\033SSE2" /* Streaming SIMD Extensions #2 */ 711 "\034SS" /* Self snoop */ 712 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 713 "\036TM" /* Thermal Monitor clock slowdown */ 714 "\037IA64" /* CPU can execute IA64 instructions */ 715 "\040PBE" /* Pending Break Enable */ 716 ); 717 718 if (cpu_feature2 != 0) { 719 printf("\n Features2=0x%b", cpu_feature2, 720 "\020" 721 "\001SSE3" /* SSE3 */ 722 "\002<b1>" 723 "\003DTES64" /* 64-bit Debug Trace */ 724 "\004MON" /* MONITOR/MWAIT Instructions */ 725 "\005DS_CPL" /* CPL Qualified Debug Store */ 726 "\006VMX" /* Virtual Machine Extensions */ 727 "\007SMX" /* Safer Mode Extensions */ 728 "\010EST" /* Enhanced SpeedStep */ 729 "\011TM2" /* Thermal Monitor 2 */ 730 "\012SSSE3" /* SSSE3 */ 731 "\013CNXT-ID" /* L1 context ID available */ 732 "\014<b11>" 733 "\015<b12>" 734 "\016CX16" /* CMPXCHG16B Instruction */ 735 "\017xTPR" /* Send Task Priority Messages*/ 736 "\020PDCM" /* Perf/Debug Capability MSR */ 737 "\021<b16>" 738 "\022<b17>" 739 "\023DCA" /* Direct Cache Access */ 740 "\024SSE4.1" 741 "\025SSE4.2" 742 "\026x2APIC" /* xAPIC Extensions */ 743 "\027<b22>" 744 "\030POPCNT" 745 "\031<b24>" 746 "\032<b25>" 747 "\033XSAVE" 748 "\034OSXSAVE" 749 "\035<b28>" 750 "\036<b29>" 751 "\037<b30>" 752 "\040<b31>" 753 ); 754 } 755 756 /* 757 * AMD64 Architecture Programmer's Manual Volume 3: 758 * General-Purpose and System Instructions 759 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 760 * 761 * IA-32 Intel Architecture Software Developer's Manual, 762 * Volume 2A: Instruction Set Reference, A-M 763 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 764 */ 765 if (amd_feature != 0) { 766 printf("\n AMD Features=0x%b", amd_feature, 767 "\020" /* in hex */ 768 "\001<s0>" /* Same */ 769 "\002<s1>" /* Same */ 770 "\003<s2>" /* Same */ 771 "\004<s3>" /* Same */ 772 "\005<s4>" /* Same */ 773 "\006<s5>" /* Same */ 774 "\007<s6>" /* Same */ 775 "\010<s7>" /* Same */ 776 "\011<s8>" /* Same */ 777 "\012<s9>" /* Same */ 778 "\013<b10>" /* Undefined */ 779 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 780 "\015<s12>" /* Same */ 781 "\016<s13>" /* Same */ 782 "\017<s14>" /* Same */ 783 "\020<s15>" /* Same */ 784 "\021<s16>" /* Same */ 785 "\022<s17>" /* Same */ 786 "\023<b18>" /* Reserved, unknown */ 787 "\024MP" /* Multiprocessor Capable */ 788 "\025NX" /* Has EFER.NXE, NX */ 789 "\026<b21>" /* Undefined */ 790 "\027MMX+" /* AMD MMX Extensions */ 791 "\030<s23>" /* Same */ 792 "\031<s24>" /* Same */ 793 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 794 "\033Page1GB" /* 1-GB large page support */ 795 "\034RDTSCP" /* RDTSCP */ 796 "\035<b28>" /* Undefined */ 797 "\036LM" /* 64 bit long mode */ 798 "\0373DNow!+" /* AMD 3DNow! Extensions */ 799 "\0403DNow!" /* AMD 3DNow! */ 800 ); 801 } 802 803 if (amd_feature2 != 0) { 804 printf("\n AMD Features2=0x%b", amd_feature2, 805 "\020" 806 "\001LAHF" /* LAHF/SAHF in long mode */ 807 "\002CMP" /* CMP legacy */ 808 "\003SVM" /* Secure Virtual Mode */ 809 "\004ExtAPIC" /* Extended APIC register */ 810 "\005CR8" /* CR8 in legacy mode */ 811 "\006<b5>" 812 "\007<b6>" 813 "\010<b7>" 814 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 815 "\012<b9>" 816 "\013<b10>" 817 "\014<b11>" 818 "\015<b12>" 819 "\016<b13>" 820 "\017<b14>" 821 "\020<b15>" 822 "\021<b16>" 823 "\022<b17>" 824 "\023<b18>" 825 "\024<b19>" 826 "\025<b20>" 827 "\026<b21>" 828 "\027<b22>" 829 "\030<b23>" 830 "\031<b24>" 831 "\032<b25>" 832 "\033<b26>" 833 "\034<b27>" 834 "\035<b28>" 835 "\036<b29>" 836 "\037<b30>" 837 "\040<b31>" 838 ); 839 } 840 841 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, 842 "AuthenticAMD") == 0) 843 cpu_feature &= ~CPUID_HTT; 844 845 /* 846 * If this CPU supports P-state invariant TSC then 847 * mention the capability. 848 */ 849 if (!tsc_is_invariant && 850 (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 851 ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 852 I386_CPU_FAMILY(cpu_id) >= 0x10 || 853 cpu_id == 0x60fb2))) { 854 tsc_is_invariant = 1; 855 printf("\n TSC: P-state invariant"); 856 } 857 858 /* 859 * If this CPU supports HTT or CMP then mention the 860 * number of physical/logical cores it contains. 861 */ 862 if (cpu_feature & CPUID_HTT) 863 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 864 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 865 (amd_feature2 & AMDID2_CMP)) 866 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 867 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 868 (cpu_high >= 4)) { 869 cpuid_count(4, 0, regs); 870 if ((regs[0] & 0x1f) != 0) 871 cmp = ((regs[0] >> 26) & 0x3f) + 1; 872 } 873 if (cmp > 1) 874 printf("\n Cores per package: %d", cmp); 875 if ((htt / cmp) > 1) 876 printf("\n Logical CPUs per core: %d", 877 htt / cmp); 878 } 879 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 880 printf(" DIR=0x%04x", cyrix_did); 881 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 882 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 883 #ifndef CYRIX_CACHE_REALLY_WORKS 884 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 885 printf("\n CPU cache: write-through mode"); 886 #endif 887 } 888 if (strcmp(cpu_vendor, "CentaurHauls") == 0) 889 print_via_padlock_info(); 890 891 /* Avoid ugly blank lines: only print newline when we have to. */ 892 if (*cpu_vendor || cpu_id) 893 printf("\n"); 894 895 if (!bootverbose) 896 return; 897 898 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 899 print_AMD_info(); 900 else if (strcmp(cpu_vendor, "GenuineIntel") == 0) 901 print_INTEL_info(); 902 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 || 903 strcmp(cpu_vendor, "TransmetaCPU") == 0) 904 print_transmeta_info(); 905 } 906 907 void 908 panicifcpuunsupported(void) 909 { 910 911 #if !defined(lint) 912 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 913 #error This kernel is not configured for one of the supported CPUs 914 #endif 915 #else /* lint */ 916 #endif /* lint */ 917 /* 918 * Now that we have told the user what they have, 919 * let them know if that machine type isn't configured. 920 */ 921 switch (cpu_class) { 922 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 923 case CPUCLASS_386: 924 #if !defined(I486_CPU) 925 case CPUCLASS_486: 926 #endif 927 #if !defined(I586_CPU) 928 case CPUCLASS_586: 929 #endif 930 #if !defined(I686_CPU) 931 case CPUCLASS_686: 932 #endif 933 panic("CPU class not configured"); 934 default: 935 break; 936 } 937 } 938 939 940 static volatile u_int trap_by_rdmsr; 941 942 /* 943 * Special exception 6 handler. 944 * The rdmsr instruction generates invalid opcodes fault on 486-class 945 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 946 * function identblue() when this handler is called. Stacked eip should 947 * be advanced. 948 */ 949 inthand_t bluetrap6; 950 #ifdef __GNUCLIKE_ASM 951 __asm 952 (" \n\ 953 .text \n\ 954 .p2align 2,0x90 \n\ 955 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 956 " __XSTRING(CNAME(bluetrap6)) ": \n\ 957 ss \n\ 958 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 959 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 960 iret \n\ 961 "); 962 #endif 963 964 /* 965 * Special exception 13 handler. 966 * Accessing non-existent MSR generates general protection fault. 967 */ 968 inthand_t bluetrap13; 969 #ifdef __GNUCLIKE_ASM 970 __asm 971 (" \n\ 972 .text \n\ 973 .p2align 2,0x90 \n\ 974 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 975 " __XSTRING(CNAME(bluetrap13)) ": \n\ 976 ss \n\ 977 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 978 popl %eax /* discard error code */ \n\ 979 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 980 iret \n\ 981 "); 982 #endif 983 984 /* 985 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 986 * support cpuid instruction. This function should be called after 987 * loading interrupt descriptor table register. 988 * 989 * I don't like this method that handles fault, but I couldn't get 990 * information for any other methods. Does blue giant know? 991 */ 992 static int 993 identblue(void) 994 { 995 996 trap_by_rdmsr = 0; 997 998 /* 999 * Cyrix 486-class CPU does not support rdmsr instruction. 1000 * The rdmsr instruction generates invalid opcode fault, and exception 1001 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1002 * bluetrap6() set the magic number to trap_by_rdmsr. 1003 */ 1004 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1005 GSEL(GCODE_SEL, SEL_KPL)); 1006 1007 /* 1008 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1009 * In this case, rdmsr generates general protection fault, and 1010 * exception will be trapped by bluetrap13(). 1011 */ 1012 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1013 GSEL(GCODE_SEL, SEL_KPL)); 1014 1015 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1016 1017 if (trap_by_rdmsr == 0xa8c1d) 1018 return IDENTBLUE_CYRIX486; 1019 else if (trap_by_rdmsr == 0xa89c4) 1020 return IDENTBLUE_CYRIXM2; 1021 return IDENTBLUE_IBMCPU; 1022 } 1023 1024 1025 /* 1026 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1027 * 1028 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1029 * +-------+-------+---------------+ 1030 * | SID | RID | Device ID | 1031 * | (DIR 1) | (DIR 0) | 1032 * +-------+-------+---------------+ 1033 */ 1034 static void 1035 identifycyrix(void) 1036 { 1037 u_int eflags; 1038 int ccr2_test = 0, dir_test = 0; 1039 u_char ccr2, ccr3; 1040 1041 eflags = read_eflags(); 1042 disable_intr(); 1043 1044 ccr2 = read_cyrix_reg(CCR2); 1045 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1046 read_cyrix_reg(CCR2); 1047 if (read_cyrix_reg(CCR2) != ccr2) 1048 ccr2_test = 1; 1049 write_cyrix_reg(CCR2, ccr2); 1050 1051 ccr3 = read_cyrix_reg(CCR3); 1052 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1053 read_cyrix_reg(CCR3); 1054 if (read_cyrix_reg(CCR3) != ccr3) 1055 dir_test = 1; /* CPU supports DIRs. */ 1056 write_cyrix_reg(CCR3, ccr3); 1057 1058 if (dir_test) { 1059 /* Device ID registers are available. */ 1060 cyrix_did = read_cyrix_reg(DIR1) << 8; 1061 cyrix_did += read_cyrix_reg(DIR0); 1062 } else if (ccr2_test) 1063 cyrix_did = 0x0010; /* 486S A-step */ 1064 else 1065 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1066 1067 write_eflags(eflags); 1068 } 1069 1070 /* Update TSC freq with the value indicated by the caller. */ 1071 static void 1072 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 1073 { 1074 /* 1075 * If there was an error during the transition or 1076 * TSC is P-state invariant, don't do anything. 1077 */ 1078 if (status != 0 || tsc_is_invariant) 1079 return; 1080 1081 /* Total setting for this level gives the new frequency in MHz. */ 1082 hw_clockrate = level->total_set.freq; 1083 } 1084 1085 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 1086 EVENTHANDLER_PRI_ANY); 1087 1088 /* 1089 * Final stage of CPU identification. -- Should I check TI? 1090 */ 1091 void 1092 finishidentcpu(void) 1093 { 1094 int isblue = 0; 1095 u_char ccr3; 1096 u_int regs[4]; 1097 1098 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ 1099 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 1100 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 1101 init_exthigh(); 1102 if (cpu_exthigh >= 0x80000001) { 1103 do_cpuid(0x80000001, regs); 1104 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1105 amd_feature2 = regs[2]; 1106 } 1107 if (cpu_exthigh >= 0x80000007) { 1108 do_cpuid(0x80000007, regs); 1109 amd_pminfo = regs[3]; 1110 } 1111 if (cpu_exthigh >= 0x80000008) { 1112 do_cpuid(0x80000008, regs); 1113 cpu_procinfo2 = regs[2]; 1114 } 1115 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 1116 if (cpu == CPU_486) { 1117 /* 1118 * These conditions are equivalent to: 1119 * - CPU does not support cpuid instruction. 1120 * - Cyrix/IBM CPU is detected. 1121 */ 1122 isblue = identblue(); 1123 if (isblue == IDENTBLUE_IBMCPU) { 1124 strcpy(cpu_vendor, "IBM"); 1125 cpu = CPU_BLUE; 1126 return; 1127 } 1128 } 1129 switch (cpu_id & 0xf00) { 1130 case 0x600: 1131 /* 1132 * Cyrix's datasheet does not describe DIRs. 1133 * Therefor, I assume it does not have them 1134 * and use the result of the cpuid instruction. 1135 * XXX they seem to have it for now at least. -Peter 1136 */ 1137 identifycyrix(); 1138 cpu = CPU_M2; 1139 break; 1140 default: 1141 identifycyrix(); 1142 /* 1143 * This routine contains a trick. 1144 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1145 */ 1146 switch (cyrix_did & 0x00f0) { 1147 case 0x00: 1148 case 0xf0: 1149 cpu = CPU_486DLC; 1150 break; 1151 case 0x10: 1152 cpu = CPU_CY486DX; 1153 break; 1154 case 0x20: 1155 if ((cyrix_did & 0x000f) < 8) 1156 cpu = CPU_M1; 1157 else 1158 cpu = CPU_M1SC; 1159 break; 1160 case 0x30: 1161 cpu = CPU_M1; 1162 break; 1163 case 0x40: 1164 /* MediaGX CPU */ 1165 cpu = CPU_M1SC; 1166 break; 1167 default: 1168 /* M2 and later CPUs are treated as M2. */ 1169 cpu = CPU_M2; 1170 1171 /* 1172 * enable cpuid instruction. 1173 */ 1174 ccr3 = read_cyrix_reg(CCR3); 1175 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1176 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1177 write_cyrix_reg(CCR3, ccr3); 1178 1179 do_cpuid(0, regs); 1180 cpu_high = regs[0]; /* eax */ 1181 do_cpuid(1, regs); 1182 cpu_id = regs[0]; /* eax */ 1183 cpu_feature = regs[3]; /* edx */ 1184 break; 1185 } 1186 } 1187 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1188 /* 1189 * There are BlueLightning CPUs that do not change 1190 * undefined flags by dividing 5 by 2. In this case, 1191 * the CPU identification routine in locore.s leaves 1192 * cpu_vendor null string and puts CPU_486 into the 1193 * cpu. 1194 */ 1195 isblue = identblue(); 1196 if (isblue == IDENTBLUE_IBMCPU) { 1197 strcpy(cpu_vendor, "IBM"); 1198 cpu = CPU_BLUE; 1199 return; 1200 } 1201 } 1202 } 1203 1204 static void 1205 print_AMD_assoc(int i) 1206 { 1207 if (i == 255) 1208 printf(", fully associative\n"); 1209 else 1210 printf(", %d-way associative\n", i); 1211 } 1212 1213 static void 1214 print_AMD_info(void) 1215 { 1216 quad_t amd_whcr; 1217 1218 if (cpu_exthigh >= 0x80000005) { 1219 u_int regs[4]; 1220 1221 do_cpuid(0x80000005, regs); 1222 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); 1223 print_AMD_assoc(regs[1] >> 24); 1224 printf("Instruction TLB: %d entries", regs[1] & 0xff); 1225 print_AMD_assoc((regs[1] >> 8) & 0xff); 1226 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1227 printf(", %d bytes/line", regs[2] & 0xff); 1228 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1229 print_AMD_assoc((regs[2] >> 16) & 0xff); 1230 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1231 printf(", %d bytes/line", regs[3] & 0xff); 1232 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1233 print_AMD_assoc((regs[3] >> 16) & 0xff); 1234 if (cpu_exthigh >= 0x80000006) { /* K6-III only */ 1235 do_cpuid(0x80000006, regs); 1236 printf("L2 internal cache: %d kbytes", regs[2] >> 16); 1237 printf(", %d bytes/line", regs[2] & 0xff); 1238 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1239 print_AMD_assoc((regs[2] >> 12) & 0x0f); 1240 } 1241 } 1242 if (((cpu_id & 0xf00) == 0x500) 1243 && (((cpu_id & 0x0f0) > 0x80) 1244 || (((cpu_id & 0x0f0) == 0x80) 1245 && (cpu_id & 0x00f) > 0x07))) { 1246 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1247 amd_whcr = rdmsr(0xc0000082); 1248 if (!(amd_whcr & (0x3ff << 22))) { 1249 printf("Write Allocate Disable\n"); 1250 } else { 1251 printf("Write Allocate Enable Limit: %dM bytes\n", 1252 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1253 printf("Write Allocate 15-16M bytes: %s\n", 1254 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1255 } 1256 } else if (((cpu_id & 0xf00) == 0x500) 1257 && ((cpu_id & 0x0f0) > 0x50)) { 1258 /* K6, K6-2(old core) */ 1259 amd_whcr = rdmsr(0xc0000082); 1260 if (!(amd_whcr & (0x7f << 1))) { 1261 printf("Write Allocate Disable\n"); 1262 } else { 1263 printf("Write Allocate Enable Limit: %dM bytes\n", 1264 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1265 printf("Write Allocate 15-16M bytes: %s\n", 1266 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1267 printf("Hardware Write Allocate Control: %s\n", 1268 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1269 } 1270 } 1271 } 1272 1273 static void 1274 print_INTEL_info(void) 1275 { 1276 u_int regs[4]; 1277 u_int rounds, regnum; 1278 u_int nwaycode, nway; 1279 1280 if (cpu_high >= 2) { 1281 rounds = 0; 1282 do { 1283 do_cpuid(0x2, regs); 1284 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1285 break; /* we have a buggy CPU */ 1286 1287 for (regnum = 0; regnum <= 3; ++regnum) { 1288 if (regs[regnum] & (1<<31)) 1289 continue; 1290 if (regnum != 0) 1291 print_INTEL_TLB(regs[regnum] & 0xff); 1292 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1293 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1294 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1295 } 1296 } while (--rounds > 0); 1297 } 1298 1299 if (cpu_exthigh >= 0x80000006) { 1300 do_cpuid(0x80000006, regs); 1301 nwaycode = (regs[2] >> 12) & 0x0f; 1302 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1303 nway = 1 << (nwaycode / 2); 1304 else 1305 nway = 0; 1306 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line", 1307 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1308 } 1309 1310 printf("\n"); 1311 } 1312 1313 static void 1314 print_INTEL_TLB(u_int data) 1315 { 1316 switch (data) { 1317 case 0x0: 1318 case 0x40: 1319 default: 1320 break; 1321 case 0x1: 1322 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries"); 1323 break; 1324 case 0x2: 1325 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries"); 1326 break; 1327 case 0x3: 1328 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries"); 1329 break; 1330 case 0x4: 1331 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries"); 1332 break; 1333 case 0x6: 1334 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size"); 1335 break; 1336 case 0x8: 1337 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size"); 1338 break; 1339 case 0xa: 1340 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size"); 1341 break; 1342 case 0xc: 1343 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size"); 1344 break; 1345 case 0x22: 1346 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size"); 1347 break; 1348 case 0x23: 1349 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1350 break; 1351 case 0x25: 1352 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size"); 1353 break; 1354 case 0x29: 1355 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size"); 1356 break; 1357 case 0x2c: 1358 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size"); 1359 break; 1360 case 0x30: 1361 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size"); 1362 break; 1363 case 0x39: 1364 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size"); 1365 break; 1366 case 0x3b: 1367 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size"); 1368 break; 1369 case 0x3c: 1370 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size"); 1371 break; 1372 case 0x41: 1373 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size"); 1374 break; 1375 case 0x42: 1376 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size"); 1377 break; 1378 case 0x43: 1379 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size"); 1380 break; 1381 case 0x44: 1382 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size"); 1383 break; 1384 case 0x45: 1385 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size"); 1386 break; 1387 case 0x46: 1388 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size"); 1389 break; 1390 case 0x47: 1391 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size"); 1392 break; 1393 case 0x50: 1394 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries"); 1395 break; 1396 case 0x51: 1397 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries"); 1398 break; 1399 case 0x52: 1400 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries"); 1401 break; 1402 case 0x5b: 1403 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries"); 1404 break; 1405 case 0x5c: 1406 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries"); 1407 break; 1408 case 0x5d: 1409 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries"); 1410 break; 1411 case 0x60: 1412 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size"); 1413 break; 1414 case 0x66: 1415 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size"); 1416 break; 1417 case 0x67: 1418 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size"); 1419 break; 1420 case 0x68: 1421 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size"); 1422 break; 1423 case 0x70: 1424 printf("\nTrace cache: 12K-uops, 8-way set associative"); 1425 break; 1426 case 0x71: 1427 printf("\nTrace cache: 16K-uops, 8-way set associative"); 1428 break; 1429 case 0x72: 1430 printf("\nTrace cache: 32K-uops, 8-way set associative"); 1431 break; 1432 case 0x78: 1433 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size"); 1434 break; 1435 case 0x79: 1436 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size"); 1437 break; 1438 case 0x7a: 1439 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size"); 1440 break; 1441 case 0x7b: 1442 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size"); 1443 break; 1444 case 0x7c: 1445 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1446 break; 1447 case 0x7d: 1448 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size"); 1449 break; 1450 case 0x7f: 1451 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size"); 1452 break; 1453 case 0x82: 1454 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size"); 1455 break; 1456 case 0x83: 1457 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size"); 1458 break; 1459 case 0x84: 1460 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size"); 1461 break; 1462 case 0x85: 1463 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size"); 1464 break; 1465 case 0x86: 1466 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size"); 1467 break; 1468 case 0x87: 1469 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size"); 1470 break; 1471 case 0xb0: 1472 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1473 break; 1474 case 0xb3: 1475 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1476 break; 1477 } 1478 } 1479 1480 1481 static void 1482 setPQL2_AMD(int *const size, int *const ways) 1483 { 1484 if (cpu_exthigh >= 0x80000006) { 1485 u_int regs[4]; 1486 1487 do_cpuid(0x80000006, regs); 1488 *size = regs[2] >> 16; 1489 *ways = (regs[2] >> 12) & 0x0f; 1490 } 1491 } 1492 1493 1494 static void 1495 setPQL2_INTEL(int *const size, int *const ways) 1496 { 1497 u_int rounds, regnum; 1498 u_int regs[4]; 1499 u_int nwaycode; 1500 1501 if (cpu_high >= 2) { 1502 rounds = 0; 1503 do { 1504 do_cpuid(0x2, regs); 1505 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1506 break; /* we have a buggy CPU */ 1507 1508 for (regnum = 0; regnum <= 3; ++regnum) { 1509 if (regs[regnum] & (1<<31)) 1510 continue; 1511 if (regnum != 0) 1512 get_INTEL_TLB(regs[regnum] & 0xff, 1513 size, ways); 1514 get_INTEL_TLB((regs[regnum] >> 8) & 0xff, 1515 size, ways); 1516 get_INTEL_TLB((regs[regnum] >> 16) & 0xff, 1517 size, ways); 1518 get_INTEL_TLB((regs[regnum] >> 24) & 0xff, 1519 size, ways); 1520 } 1521 } while (--rounds > 0); 1522 } 1523 1524 if (cpu_exthigh >= 0x80000006) { 1525 do_cpuid(0x80000006, regs); 1526 if (*size < ((regs[2] >> 16) & 0xffff)) { 1527 *size = (regs[2] >> 16) & 0xffff; 1528 nwaycode = (regs[2] >> 12) & 0x0f; 1529 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1530 *ways = 1 << (nwaycode / 2); 1531 else 1532 *ways = 0; 1533 } 1534 } 1535 } 1536 1537 static void 1538 get_INTEL_TLB(u_int data, int *const size, int *const ways) 1539 { 1540 switch (data) { 1541 default: 1542 break; 1543 case 0x22: 1544 /* 3rd-level cache: 512 KB, 4-way set associative, 1545 * sectored cache, 64 byte line size */ 1546 if (*size < 512) { 1547 *size = 512; 1548 *ways = 4; 1549 } 1550 break; 1551 case 0x23: 1552 /* 3rd-level cache: 1 MB, 8-way set associative, 1553 * sectored cache, 64 byte line size */ 1554 if (*size < 1024) { 1555 *size = 1024; 1556 *ways = 8; 1557 } 1558 break; 1559 case 0x25: 1560 /* 3rd-level cache: 2 MB, 8-way set associative, 1561 * sectored cache, 64 byte line size */ 1562 if (*size < 2048) { 1563 *size = 2048; 1564 *ways = 8; 1565 } 1566 break; 1567 case 0x29: 1568 /* 3rd-level cache: 4 MB, 8-way set associative, 1569 * sectored cache, 64 byte line size */ 1570 if (*size < 4096) { 1571 *size = 4096; 1572 *ways = 8; 1573 } 1574 break; 1575 case 0x39: 1576 /* 2nd-level cache: 128 KB, 4-way set associative, 1577 * sectored cache, 64 byte line size */ 1578 if (*size < 128) { 1579 *size = 128; 1580 *ways = 4; 1581 } 1582 break; 1583 case 0x3b: 1584 /* 2nd-level cache: 128 KB, 2-way set associative, 1585 * sectored cache, 64 byte line size */ 1586 if (*size < 128) { 1587 *size = 128; 1588 *ways = 2; 1589 } 1590 break; 1591 case 0x3c: 1592 /* 2nd-level cache: 256 KB, 4-way set associative, 1593 * sectored cache, 64 byte line size */ 1594 if (*size < 256) { 1595 *size = 256; 1596 *ways = 4; 1597 } 1598 break; 1599 case 0x41: 1600 /* 2nd-level cache: 128 KB, 4-way set associative, 1601 * 32 byte line size */ 1602 if (*size < 128) { 1603 *size = 128; 1604 *ways = 4; 1605 } 1606 break; 1607 case 0x42: 1608 /* 2nd-level cache: 256 KB, 4-way set associative, 1609 * 32 byte line size */ 1610 if (*size < 256) { 1611 *size = 256; 1612 *ways = 4; 1613 } 1614 break; 1615 case 0x43: 1616 /* 2nd-level cache: 512 KB, 4-way set associative, 1617 * 32 byte line size */ 1618 if (*size < 512) { 1619 *size = 512; 1620 *ways = 4; 1621 } 1622 break; 1623 case 0x44: 1624 /* 2nd-level cache: 1 MB, 4-way set associative, 1625 * 32 byte line size */ 1626 if (*size < 1024) { 1627 *size = 1024; 1628 *ways = 4; 1629 } 1630 break; 1631 case 0x45: 1632 /* 2nd-level cache: 2 MB, 4-way set associative, 1633 * 32 byte line size */ 1634 if (*size < 2048) { 1635 *size = 2048; 1636 *ways = 4; 1637 } 1638 break; 1639 case 0x46: 1640 /* 3rd-level cache: 4 MB, 4-way set associative, 1641 * 64 byte line size */ 1642 if (*size < 4096) { 1643 *size = 4096; 1644 *ways = 4; 1645 } 1646 break; 1647 case 0x47: 1648 /* 3rd-level cache: 8 MB, 8-way set associative, 1649 * 64 byte line size */ 1650 if (*size < 8192) { 1651 *size = 8192; 1652 *ways = 8; 1653 } 1654 break; 1655 case 0x78: 1656 /* 2nd-level cache: 1 MB, 4-way set associative, 1657 * 64-byte line size */ 1658 if (*size < 1024) { 1659 *size = 1024; 1660 *ways = 4; 1661 } 1662 break; 1663 case 0x79: 1664 /* 2nd-level cache: 128 KB, 8-way set associative, 1665 * sectored cache, 64 byte line size */ 1666 if (*size < 128) { 1667 *size = 128; 1668 *ways = 8; 1669 } 1670 break; 1671 case 0x7a: 1672 /* 2nd-level cache: 256 KB, 8-way set associative, 1673 * sectored cache, 64 byte line size */ 1674 if (*size < 256) { 1675 *size = 256; 1676 *ways = 8; 1677 } 1678 break; 1679 case 0x7b: 1680 /* 2nd-level cache: 512 KB, 8-way set associative, 1681 * sectored cache, 64 byte line size */ 1682 if (*size < 512) { 1683 *size = 512; 1684 *ways = 8; 1685 } 1686 break; 1687 case 0x7c: 1688 /* 2nd-level cache: 1 MB, 8-way set associative, 1689 * sectored cache, 64 byte line size */ 1690 if (*size < 1024) { 1691 *size = 1024; 1692 *ways = 8; 1693 } 1694 break; 1695 case 0x7d: 1696 /* 2nd-level cache: 2 MB, 8-way set associative, 1697 * 64-byte line size */ 1698 if (*size < 2048) { 1699 *size = 2048; 1700 *ways = 8; 1701 } 1702 break; 1703 case 0x7f: 1704 /* 2nd-level cache: 512 KB, 2-way set associative, 1705 * 64-byte line size */ 1706 if (*size < 512) { 1707 *size = 512; 1708 *ways = 2; 1709 } 1710 break; 1711 case 0x82: 1712 /* 2nd-level cache: 256 KB, 8-way set associative, 1713 * 32 byte line size */ 1714 if (*size < 256) { 1715 *size = 256; 1716 *ways = 8; 1717 } 1718 break; 1719 case 0x83: 1720 /* 2nd-level cache: 512 KB, 8-way set associative, 1721 * 32 byte line size */ 1722 if (*size < 512) { 1723 *size = 512; 1724 *ways = 8; 1725 } 1726 break; 1727 case 0x84: 1728 /* 2nd-level cache: 1 MB, 8-way set associative, 1729 * 32 byte line size */ 1730 if (*size < 1024) { 1731 *size = 1024; 1732 *ways = 8; 1733 } 1734 break; 1735 case 0x85: 1736 /* 2nd-level cache: 2 MB, 8-way set associative, 1737 * 32 byte line size */ 1738 if (*size < 2048) { 1739 *size = 2048; 1740 *ways = 8; 1741 } 1742 break; 1743 case 0x86: 1744 /* 2nd-level cache: 512 KB, 4-way set associative, 1745 * 64 byte line size */ 1746 if (*size < 512) { 1747 *size = 512; 1748 *ways = 4; 1749 } 1750 break; 1751 case 0x87: 1752 /* 2nd-level cache: 1 MB, 8-way set associative, 1753 * 64 byte line size */ 1754 if (*size < 1024) { 1755 *size = 512; 1756 *ways = 8; 1757 } 1758 break; 1759 } 1760 } 1761 1762 void 1763 setPQL2(int *const size, int *const ways) 1764 { 1765 /* make sure the cpu_exthigh variable is initialized */ 1766 init_exthigh(); 1767 1768 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 1769 setPQL2_AMD(size, ways); 1770 else if (strcmp(cpu_vendor, "GenuineIntel") == 0) 1771 setPQL2_INTEL(size, ways); 1772 } 1773 1774 static void 1775 print_transmeta_info(void) 1776 { 1777 u_int regs[4], nreg = 0; 1778 1779 do_cpuid(0x80860000, regs); 1780 nreg = regs[0]; 1781 if (nreg >= 0x80860001) { 1782 do_cpuid(0x80860001, regs); 1783 printf(" Processor revision %u.%u.%u.%u\n", 1784 (regs[1] >> 24) & 0xff, 1785 (regs[1] >> 16) & 0xff, 1786 (regs[1] >> 8) & 0xff, 1787 regs[1] & 0xff); 1788 } 1789 if (nreg >= 0x80860002) { 1790 do_cpuid(0x80860002, regs); 1791 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 1792 (regs[1] >> 24) & 0xff, 1793 (regs[1] >> 16) & 0xff, 1794 (regs[1] >> 8) & 0xff, 1795 regs[1] & 0xff, 1796 regs[2]); 1797 } 1798 if (nreg >= 0x80860006) { 1799 char info[65]; 1800 do_cpuid(0x80860003, (u_int*) &info[0]); 1801 do_cpuid(0x80860004, (u_int*) &info[16]); 1802 do_cpuid(0x80860005, (u_int*) &info[32]); 1803 do_cpuid(0x80860006, (u_int*) &info[48]); 1804 info[64] = 0; 1805 printf(" %s\n", info); 1806 } 1807 } 1808 1809 static void 1810 print_via_padlock_info(void) 1811 { 1812 u_int regs[4]; 1813 1814 /* Check for supported models. */ 1815 switch (cpu_id & 0xff0) { 1816 case 0x690: 1817 if ((cpu_id & 0xf) < 3) 1818 return; 1819 case 0x6a0: 1820 case 0x6d0: 1821 break; 1822 default: 1823 return; 1824 } 1825 1826 do_cpuid(0xc0000000, regs); 1827 if (regs[0] >= 0xc0000001) 1828 do_cpuid(0xc0000001, regs); 1829 else 1830 return; 1831 1832 printf("\n VIA Padlock Features=0x%b", regs[3], 1833 "\020" 1834 "\003RNG" /* RNG */ 1835 "\007AES" /* ACE */ 1836 "\011AES-CTR" /* ACE2 */ 1837 "\013SHA1,SHA256" /* PHE */ 1838 "\015RSA" /* PMM */ 1839 ); 1840 }
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