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sys/i386/i386/identcpu.c
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1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/7.3/sys/i386/i386/identcpu.c 200742 2009-12-20 01:00:41Z avg $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/md_var.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 63 #define IDENTBLUE_CYRIX486 0 64 #define IDENTBLUE_IBMCPU 1 65 #define IDENTBLUE_CYRIXM2 2 66 67 /* XXX - should be in header file: */ 68 void printcpuinfo(void); 69 void finishidentcpu(void); 70 void earlysetcpuclass(void); 71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 72 void enable_K5_wt_alloc(void); 73 void enable_K6_wt_alloc(void); 74 void enable_K6_2_wt_alloc(void); 75 #endif 76 void panicifcpuunsupported(void); 77 78 static void identifycyrix(void); 79 static void init_exthigh(void); 80 static u_int find_cpu_vendor_id(void); 81 static void print_AMD_info(void); 82 static void print_INTEL_info(void); 83 static void print_INTEL_TLB(u_int data); 84 static void print_AMD_assoc(int i); 85 static void print_transmeta_info(void); 86 static void print_via_padlock_info(void); 87 88 int cpu_class; 89 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 90 u_int cyrix_did; /* Device ID of Cyrix CPU */ 91 char machine[] = MACHINE; 92 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 93 machine, 0, "Machine class"); 94 95 static char cpu_model[128]; 96 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 97 cpu_model, 0, "Machine model"); 98 99 static int hw_clockrate; 100 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 101 &hw_clockrate, 0, "CPU instruction clock rate"); 102 103 static char cpu_brand[48]; 104 105 #define MAX_BRAND_INDEX 8 106 107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 108 NULL, /* No brand */ 109 "Intel Celeron", 110 "Intel Pentium III", 111 "Intel Pentium III Xeon", 112 NULL, 113 NULL, 114 NULL, 115 NULL, 116 "Intel Pentium 4" 117 }; 118 119 static struct { 120 char *cpu_name; 121 int cpu_class; 122 } i386_cpus[] = { 123 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 124 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 125 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 126 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 127 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 128 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 129 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 130 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 131 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 132 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 133 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 134 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 135 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 136 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 137 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 138 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 139 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 140 }; 141 142 static struct { 143 char *vendor; 144 u_int vendor_id; 145 } cpu_vendors[] = { 146 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 147 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 148 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 149 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 150 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 151 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 152 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 153 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 154 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 155 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 156 #if 0 157 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 158 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 159 #endif 160 }; 161 162 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 163 int has_f00f_bug = 0; /* Initialized so that it can be patched. */ 164 #endif 165 166 static void 167 init_exthigh(void) 168 { 169 static int done = 0; 170 u_int regs[4]; 171 172 if (done == 0) { 173 if (cpu_high > 0 && 174 (cpu_vendor_id == CPU_VENDOR_INTEL || 175 cpu_vendor_id == CPU_VENDOR_AMD || 176 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 177 cpu_vendor_id == CPU_VENDOR_CENTAUR || 178 cpu_vendor_id == CPU_VENDOR_NSC)) { 179 do_cpuid(0x80000000, regs); 180 if (regs[0] >= 0x80000000) 181 cpu_exthigh = regs[0]; 182 } 183 184 done = 1; 185 } 186 } 187 188 void 189 printcpuinfo(void) 190 { 191 u_int regs[4], i; 192 char *brand; 193 194 cpu_class = i386_cpus[cpu].cpu_class; 195 printf("CPU: "); 196 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); 197 198 /* Check for extended CPUID information and a processor name. */ 199 init_exthigh(); 200 if (cpu_exthigh >= 0x80000004) { 201 brand = cpu_brand; 202 for (i = 0x80000002; i < 0x80000005; i++) { 203 do_cpuid(i, regs); 204 memcpy(brand, regs, sizeof(regs)); 205 brand += sizeof(regs); 206 } 207 } 208 209 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 210 if ((cpu_id & 0xf00) > 0x300) { 211 u_int brand_index; 212 213 cpu_model[0] = '\0'; 214 215 switch (cpu_id & 0x3000) { 216 case 0x1000: 217 strcpy(cpu_model, "Overdrive "); 218 break; 219 case 0x2000: 220 strcpy(cpu_model, "Dual "); 221 break; 222 } 223 224 switch (cpu_id & 0xf00) { 225 case 0x400: 226 strcat(cpu_model, "i486 "); 227 /* Check the particular flavor of 486 */ 228 switch (cpu_id & 0xf0) { 229 case 0x00: 230 case 0x10: 231 strcat(cpu_model, "DX"); 232 break; 233 case 0x20: 234 strcat(cpu_model, "SX"); 235 break; 236 case 0x30: 237 strcat(cpu_model, "DX2"); 238 break; 239 case 0x40: 240 strcat(cpu_model, "SL"); 241 break; 242 case 0x50: 243 strcat(cpu_model, "SX2"); 244 break; 245 case 0x70: 246 strcat(cpu_model, 247 "DX2 Write-Back Enhanced"); 248 break; 249 case 0x80: 250 strcat(cpu_model, "DX4"); 251 break; 252 } 253 break; 254 case 0x500: 255 /* Check the particular flavor of 586 */ 256 strcat(cpu_model, "Pentium"); 257 switch (cpu_id & 0xf0) { 258 case 0x00: 259 strcat(cpu_model, " A-step"); 260 break; 261 case 0x10: 262 strcat(cpu_model, "/P5"); 263 break; 264 case 0x20: 265 strcat(cpu_model, "/P54C"); 266 break; 267 case 0x30: 268 strcat(cpu_model, "/P24T"); 269 break; 270 case 0x40: 271 strcat(cpu_model, "/P55C"); 272 break; 273 case 0x70: 274 strcat(cpu_model, "/P54C"); 275 break; 276 case 0x80: 277 strcat(cpu_model, "/P55C (quarter-micron)"); 278 break; 279 default: 280 /* nothing */ 281 break; 282 } 283 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 284 /* 285 * XXX - If/when Intel fixes the bug, this 286 * should also check the version of the 287 * CPU, not just that it's a Pentium. 288 */ 289 has_f00f_bug = 1; 290 #endif 291 break; 292 case 0x600: 293 /* Check the particular flavor of 686 */ 294 switch (cpu_id & 0xf0) { 295 case 0x00: 296 strcat(cpu_model, "Pentium Pro A-step"); 297 break; 298 case 0x10: 299 strcat(cpu_model, "Pentium Pro"); 300 break; 301 case 0x30: 302 case 0x50: 303 case 0x60: 304 strcat(cpu_model, 305 "Pentium II/Pentium II Xeon/Celeron"); 306 cpu = CPU_PII; 307 break; 308 case 0x70: 309 case 0x80: 310 case 0xa0: 311 case 0xb0: 312 strcat(cpu_model, 313 "Pentium III/Pentium III Xeon/Celeron"); 314 cpu = CPU_PIII; 315 break; 316 default: 317 strcat(cpu_model, "Unknown 80686"); 318 break; 319 } 320 break; 321 case 0xf00: 322 strcat(cpu_model, "Pentium 4"); 323 cpu = CPU_P4; 324 break; 325 default: 326 strcat(cpu_model, "unknown"); 327 break; 328 } 329 330 /* 331 * If we didn't get a brand name from the extended 332 * CPUID, try to look it up in the brand table. 333 */ 334 if (cpu_high > 0 && *cpu_brand == '\0') { 335 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 336 if (brand_index <= MAX_BRAND_INDEX && 337 cpu_brandtable[brand_index] != NULL) 338 strcpy(cpu_brand, 339 cpu_brandtable[brand_index]); 340 } 341 } 342 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 343 /* 344 * Values taken from AMD Processor Recognition 345 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 346 * (also describes ``Features'' encodings. 347 */ 348 strcpy(cpu_model, "AMD "); 349 switch (cpu_id & 0xFF0) { 350 case 0x410: 351 strcat(cpu_model, "Standard Am486DX"); 352 break; 353 case 0x430: 354 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 355 break; 356 case 0x470: 357 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 358 break; 359 case 0x480: 360 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 361 break; 362 case 0x490: 363 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 364 break; 365 case 0x4E0: 366 strcat(cpu_model, "Am5x86 Write-Through"); 367 break; 368 case 0x4F0: 369 strcat(cpu_model, "Am5x86 Write-Back"); 370 break; 371 case 0x500: 372 strcat(cpu_model, "K5 model 0"); 373 tsc_is_broken = 1; 374 break; 375 case 0x510: 376 strcat(cpu_model, "K5 model 1"); 377 break; 378 case 0x520: 379 strcat(cpu_model, "K5 PR166 (model 2)"); 380 break; 381 case 0x530: 382 strcat(cpu_model, "K5 PR200 (model 3)"); 383 break; 384 case 0x560: 385 strcat(cpu_model, "K6"); 386 break; 387 case 0x570: 388 strcat(cpu_model, "K6 266 (model 1)"); 389 break; 390 case 0x580: 391 strcat(cpu_model, "K6-2"); 392 break; 393 case 0x590: 394 strcat(cpu_model, "K6-III"); 395 break; 396 case 0x5a0: 397 strcat(cpu_model, "Geode LX"); 398 /* 399 * Make sure the TSC runs through suspension, 400 * otherwise we can't use it as timecounter 401 */ 402 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 403 break; 404 default: 405 strcat(cpu_model, "Unknown"); 406 break; 407 } 408 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 409 if ((cpu_id & 0xf00) == 0x500) { 410 if (((cpu_id & 0x0f0) > 0) 411 && ((cpu_id & 0x0f0) < 0x60) 412 && ((cpu_id & 0x00f) > 3)) 413 enable_K5_wt_alloc(); 414 else if (((cpu_id & 0x0f0) > 0x80) 415 || (((cpu_id & 0x0f0) == 0x80) 416 && (cpu_id & 0x00f) > 0x07)) 417 enable_K6_2_wt_alloc(); 418 else if ((cpu_id & 0x0f0) > 0x50) 419 enable_K6_wt_alloc(); 420 } 421 #endif 422 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 423 strcpy(cpu_model, "Cyrix "); 424 switch (cpu_id & 0xff0) { 425 case 0x440: 426 strcat(cpu_model, "MediaGX"); 427 break; 428 case 0x520: 429 strcat(cpu_model, "6x86"); 430 break; 431 case 0x540: 432 cpu_class = CPUCLASS_586; 433 strcat(cpu_model, "GXm"); 434 break; 435 case 0x600: 436 strcat(cpu_model, "6x86MX"); 437 break; 438 default: 439 /* 440 * Even though CPU supports the cpuid 441 * instruction, it can be disabled. 442 * Therefore, this routine supports all Cyrix 443 * CPUs. 444 */ 445 switch (cyrix_did & 0xf0) { 446 case 0x00: 447 switch (cyrix_did & 0x0f) { 448 case 0x00: 449 strcat(cpu_model, "486SLC"); 450 break; 451 case 0x01: 452 strcat(cpu_model, "486DLC"); 453 break; 454 case 0x02: 455 strcat(cpu_model, "486SLC2"); 456 break; 457 case 0x03: 458 strcat(cpu_model, "486DLC2"); 459 break; 460 case 0x04: 461 strcat(cpu_model, "486SRx"); 462 break; 463 case 0x05: 464 strcat(cpu_model, "486DRx"); 465 break; 466 case 0x06: 467 strcat(cpu_model, "486SRx2"); 468 break; 469 case 0x07: 470 strcat(cpu_model, "486DRx2"); 471 break; 472 case 0x08: 473 strcat(cpu_model, "486SRu"); 474 break; 475 case 0x09: 476 strcat(cpu_model, "486DRu"); 477 break; 478 case 0x0a: 479 strcat(cpu_model, "486SRu2"); 480 break; 481 case 0x0b: 482 strcat(cpu_model, "486DRu2"); 483 break; 484 default: 485 strcat(cpu_model, "Unknown"); 486 break; 487 } 488 break; 489 case 0x10: 490 switch (cyrix_did & 0x0f) { 491 case 0x00: 492 strcat(cpu_model, "486S"); 493 break; 494 case 0x01: 495 strcat(cpu_model, "486S2"); 496 break; 497 case 0x02: 498 strcat(cpu_model, "486Se"); 499 break; 500 case 0x03: 501 strcat(cpu_model, "486S2e"); 502 break; 503 case 0x0a: 504 strcat(cpu_model, "486DX"); 505 break; 506 case 0x0b: 507 strcat(cpu_model, "486DX2"); 508 break; 509 case 0x0f: 510 strcat(cpu_model, "486DX4"); 511 break; 512 default: 513 strcat(cpu_model, "Unknown"); 514 break; 515 } 516 break; 517 case 0x20: 518 if ((cyrix_did & 0x0f) < 8) 519 strcat(cpu_model, "6x86"); /* Where did you get it? */ 520 else 521 strcat(cpu_model, "5x86"); 522 break; 523 case 0x30: 524 strcat(cpu_model, "6x86"); 525 break; 526 case 0x40: 527 if ((cyrix_did & 0xf000) == 0x3000) { 528 cpu_class = CPUCLASS_586; 529 strcat(cpu_model, "GXm"); 530 } else 531 strcat(cpu_model, "MediaGX"); 532 break; 533 case 0x50: 534 strcat(cpu_model, "6x86MX"); 535 break; 536 case 0xf0: 537 switch (cyrix_did & 0x0f) { 538 case 0x0d: 539 strcat(cpu_model, "Overdrive CPU"); 540 break; 541 case 0x0e: 542 strcpy(cpu_model, "Texas Instruments 486SXL"); 543 break; 544 case 0x0f: 545 strcat(cpu_model, "486SLC/DLC"); 546 break; 547 default: 548 strcat(cpu_model, "Unknown"); 549 break; 550 } 551 break; 552 default: 553 strcat(cpu_model, "Unknown"); 554 break; 555 } 556 break; 557 } 558 } else if (cpu_vendor_id == CPU_VENDOR_RISE) { 559 strcpy(cpu_model, "Rise "); 560 switch (cpu_id & 0xff0) { 561 case 0x500: 562 strcat(cpu_model, "mP6"); 563 break; 564 default: 565 strcat(cpu_model, "Unknown"); 566 } 567 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { 568 switch (cpu_id & 0xff0) { 569 case 0x540: 570 strcpy(cpu_model, "IDT WinChip C6"); 571 tsc_is_broken = 1; 572 break; 573 case 0x580: 574 strcpy(cpu_model, "IDT WinChip 2"); 575 break; 576 case 0x660: 577 strcpy(cpu_model, "VIA C3 Samuel"); 578 break; 579 case 0x670: 580 if (cpu_id & 0x8) 581 strcpy(cpu_model, "VIA C3 Ezra"); 582 else 583 strcpy(cpu_model, "VIA C3 Samuel 2"); 584 break; 585 case 0x680: 586 strcpy(cpu_model, "VIA C3 Ezra-T"); 587 break; 588 case 0x690: 589 strcpy(cpu_model, "VIA C3 Nehemiah"); 590 break; 591 case 0x6a0: 592 case 0x6d0: 593 strcpy(cpu_model, "VIA C7 Esther"); 594 break; 595 case 0x6f0: 596 strcpy(cpu_model, "VIA Nano"); 597 break; 598 default: 599 strcpy(cpu_model, "VIA/IDT Unknown"); 600 } 601 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 602 strcpy(cpu_model, "Blue Lightning CPU"); 603 } else if (cpu_vendor_id == CPU_VENDOR_NSC) { 604 switch (cpu_id & 0xfff) { 605 case 0x540: 606 strcpy(cpu_model, "Geode SC1100"); 607 cpu = CPU_GEODE1100; 608 tsc_is_broken = 1; 609 break; 610 default: 611 strcpy(cpu_model, "Geode/NSC unknown"); 612 break; 613 } 614 } 615 616 /* 617 * Replace cpu_model with cpu_brand minus leading spaces if 618 * we have one. 619 */ 620 brand = cpu_brand; 621 while (*brand == ' ') 622 ++brand; 623 if (*brand != '\0') 624 strcpy(cpu_model, brand); 625 626 printf("%s (", cpu_model); 627 switch(cpu_class) { 628 case CPUCLASS_286: 629 printf("286"); 630 break; 631 case CPUCLASS_386: 632 printf("386"); 633 break; 634 #if defined(I486_CPU) 635 case CPUCLASS_486: 636 printf("486"); 637 bzero_vector = i486_bzero; 638 break; 639 #endif 640 #if defined(I586_CPU) 641 case CPUCLASS_586: 642 hw_clockrate = (tsc_freq + 5000) / 1000000; 643 printf("%jd.%02d-MHz ", 644 (intmax_t)(tsc_freq + 4999) / 1000000, 645 (u_int)((tsc_freq + 4999) / 10000) % 100); 646 printf("586"); 647 break; 648 #endif 649 #if defined(I686_CPU) 650 case CPUCLASS_686: 651 hw_clockrate = (tsc_freq + 5000) / 1000000; 652 printf("%jd.%02d-MHz ", 653 (intmax_t)(tsc_freq + 4999) / 1000000, 654 (u_int)((tsc_freq + 4999) / 10000) % 100); 655 printf("686"); 656 break; 657 #endif 658 default: 659 printf("Unknown"); /* will panic below... */ 660 } 661 printf("-class CPU)\n"); 662 if(*cpu_vendor) 663 printf(" Origin = \"%s\"",cpu_vendor); 664 if(cpu_id) 665 printf(" Id = 0x%x", cpu_id); 666 667 if (cpu_vendor_id == CPU_VENDOR_INTEL || 668 cpu_vendor_id == CPU_VENDOR_AMD || 669 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 670 cpu_vendor_id == CPU_VENDOR_RISE || 671 cpu_vendor_id == CPU_VENDOR_CENTAUR || 672 cpu_vendor_id == CPU_VENDOR_NSC || 673 (cpu_vendor_id == CPU_VENDOR_CYRIX && 674 ((cpu_id & 0xf00) > 0x500))) { 675 printf(" Stepping = %u", cpu_id & 0xf); 676 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 677 printf(" DIR=0x%04x", cyrix_did); 678 if (cpu_high > 0) { 679 u_int cmp = 1, htt = 1; 680 681 /* 682 * Here we should probably set up flags indicating 683 * whether or not various features are available. 684 * The interesting ones are probably VME, PSE, PAE, 685 * and PGE. The code already assumes without bothering 686 * to check that all CPUs >= Pentium have a TSC and 687 * MSRs. 688 */ 689 printf("\n Features=0x%b", cpu_feature, 690 "\020" 691 "\001FPU" /* Integral FPU */ 692 "\002VME" /* Extended VM86 mode support */ 693 "\003DE" /* Debugging Extensions (CR4.DE) */ 694 "\004PSE" /* 4MByte page tables */ 695 "\005TSC" /* Timestamp counter */ 696 "\006MSR" /* Machine specific registers */ 697 "\007PAE" /* Physical address extension */ 698 "\010MCE" /* Machine Check support */ 699 "\011CX8" /* CMPEXCH8 instruction */ 700 "\012APIC" /* SMP local APIC */ 701 "\013oldMTRR" /* Previous implementation of MTRR */ 702 "\014SEP" /* Fast System Call */ 703 "\015MTRR" /* Memory Type Range Registers */ 704 "\016PGE" /* PG_G (global bit) support */ 705 "\017MCA" /* Machine Check Architecture */ 706 "\020CMOV" /* CMOV instruction */ 707 "\021PAT" /* Page attributes table */ 708 "\022PSE36" /* 36 bit address space support */ 709 "\023PN" /* Processor Serial number */ 710 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 711 "\025<b20>" 712 "\026DTS" /* Debug Trace Store */ 713 "\027ACPI" /* ACPI support */ 714 "\030MMX" /* MMX instructions */ 715 "\031FXSR" /* FXSAVE/FXRSTOR */ 716 "\032SSE" /* Streaming SIMD Extensions */ 717 "\033SSE2" /* Streaming SIMD Extensions #2 */ 718 "\034SS" /* Self snoop */ 719 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 720 "\036TM" /* Thermal Monitor clock slowdown */ 721 "\037IA64" /* CPU can execute IA64 instructions */ 722 "\040PBE" /* Pending Break Enable */ 723 ); 724 725 if (cpu_feature2 != 0) { 726 printf("\n Features2=0x%b", cpu_feature2, 727 "\020" 728 "\001SSE3" /* SSE3 */ 729 "\002<b1>" 730 "\003DTES64" /* 64-bit Debug Trace */ 731 "\004MON" /* MONITOR/MWAIT Instructions */ 732 "\005DS_CPL" /* CPL Qualified Debug Store */ 733 "\006VMX" /* Virtual Machine Extensions */ 734 "\007SMX" /* Safer Mode Extensions */ 735 "\010EST" /* Enhanced SpeedStep */ 736 "\011TM2" /* Thermal Monitor 2 */ 737 "\012SSSE3" /* SSSE3 */ 738 "\013CNXT-ID" /* L1 context ID available */ 739 "\014<b11>" 740 "\015<b12>" 741 "\016CX16" /* CMPXCHG16B Instruction */ 742 "\017xTPR" /* Send Task Priority Messages*/ 743 "\020PDCM" /* Perf/Debug Capability MSR */ 744 "\021<b16>" 745 "\022<b17>" 746 "\023DCA" /* Direct Cache Access */ 747 "\024SSE4.1" 748 "\025SSE4.2" 749 "\026x2APIC" /* xAPIC Extensions */ 750 "\027MOVBE" 751 "\030POPCNT" 752 "\031<b24>" 753 "\032<b25>" 754 "\033XSAVE" 755 "\034OSXSAVE" 756 "\035<b28>" 757 "\036<b29>" 758 "\037<b30>" 759 "\040<b31>" 760 ); 761 } 762 763 /* 764 * AMD64 Architecture Programmer's Manual Volume 3: 765 * General-Purpose and System Instructions 766 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 767 * 768 * IA-32 Intel Architecture Software Developer's Manual, 769 * Volume 2A: Instruction Set Reference, A-M 770 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 771 */ 772 if (amd_feature != 0) { 773 printf("\n AMD Features=0x%b", amd_feature, 774 "\020" /* in hex */ 775 "\001<s0>" /* Same */ 776 "\002<s1>" /* Same */ 777 "\003<s2>" /* Same */ 778 "\004<s3>" /* Same */ 779 "\005<s4>" /* Same */ 780 "\006<s5>" /* Same */ 781 "\007<s6>" /* Same */ 782 "\010<s7>" /* Same */ 783 "\011<s8>" /* Same */ 784 "\012<s9>" /* Same */ 785 "\013<b10>" /* Undefined */ 786 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 787 "\015<s12>" /* Same */ 788 "\016<s13>" /* Same */ 789 "\017<s14>" /* Same */ 790 "\020<s15>" /* Same */ 791 "\021<s16>" /* Same */ 792 "\022<s17>" /* Same */ 793 "\023<b18>" /* Reserved, unknown */ 794 "\024MP" /* Multiprocessor Capable */ 795 "\025NX" /* Has EFER.NXE, NX */ 796 "\026<b21>" /* Undefined */ 797 "\027MMX+" /* AMD MMX Extensions */ 798 "\030<s23>" /* Same */ 799 "\031<s24>" /* Same */ 800 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 801 "\033Page1GB" /* 1-GB large page support */ 802 "\034RDTSCP" /* RDTSCP */ 803 "\035<b28>" /* Undefined */ 804 "\036LM" /* 64 bit long mode */ 805 "\0373DNow!+" /* AMD 3DNow! Extensions */ 806 "\0403DNow!" /* AMD 3DNow! */ 807 ); 808 } 809 810 if (amd_feature2 != 0) { 811 printf("\n AMD Features2=0x%b", amd_feature2, 812 "\020" 813 "\001LAHF" /* LAHF/SAHF in long mode */ 814 "\002CMP" /* CMP legacy */ 815 "\003SVM" /* Secure Virtual Mode */ 816 "\004ExtAPIC" /* Extended APIC register */ 817 "\005CR8" /* CR8 in legacy mode */ 818 "\006ABM" /* LZCNT instruction */ 819 "\007SSE4A" /* SSE4A */ 820 "\010MAS" /* Misaligned SSE mode */ 821 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 822 "\012OSVW" /* OS visible workaround */ 823 "\013IBS" /* Instruction based sampling */ 824 "\014SSE5" /* SSE5 */ 825 "\015SKINIT" /* SKINIT/STGI */ 826 "\016WDT" /* Watchdog timer */ 827 "\017<b14>" 828 "\020<b15>" 829 "\021<b16>" 830 "\022<b17>" 831 "\023<b18>" 832 "\024<b19>" 833 "\025<b20>" 834 "\026<b21>" 835 "\027<b22>" 836 "\030<b23>" 837 "\031<b24>" 838 "\032<b25>" 839 "\033<b26>" 840 "\034<b27>" 841 "\035<b28>" 842 "\036<b29>" 843 "\037<b30>" 844 "\040<b31>" 845 ); 846 } 847 848 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 849 print_via_padlock_info(); 850 851 if ((cpu_feature & CPUID_HTT) && 852 cpu_vendor_id == CPU_VENDOR_AMD) 853 cpu_feature &= ~CPUID_HTT; 854 855 /* 856 * If this CPU supports P-state invariant TSC then 857 * mention the capability. 858 */ 859 switch (cpu_vendor_id) { 860 case CPU_VENDOR_AMD: 861 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 862 CPUID_TO_FAMILY(cpu_id) >= 0x10 || 863 cpu_id == 0x60fb2) 864 tsc_is_invariant = 1; 865 break; 866 case CPU_VENDOR_INTEL: 867 if (amd_pminfo & AMDPM_TSC_INVARIANT) 868 tsc_is_invariant = 1; 869 break; 870 case CPU_VENDOR_CENTAUR: 871 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 872 CPUID_TO_MODEL(cpu_id) >= 0xf && 873 (rdmsr(0x1203) & 0x100000000ULL) == 0) 874 tsc_is_invariant = 1; 875 break; 876 } 877 if (tsc_is_invariant) 878 printf("\n TSC: P-state invariant"); 879 880 /* 881 * If this CPU supports HTT or CMP then mention the 882 * number of physical/logical cores it contains. 883 */ 884 if (cpu_feature & CPUID_HTT) 885 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 886 if (cpu_vendor_id == CPU_VENDOR_AMD && 887 (amd_feature2 & AMDID2_CMP)) 888 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 889 else if (cpu_vendor_id == CPU_VENDOR_INTEL && 890 (cpu_high >= 4)) { 891 cpuid_count(4, 0, regs); 892 if ((regs[0] & 0x1f) != 0) 893 cmp = ((regs[0] >> 26) & 0x3f) + 1; 894 } 895 if (cmp > 1) 896 printf("\n Cores per package: %d", cmp); 897 if ((htt / cmp) > 1) 898 printf("\n Logical CPUs per core: %d", 899 htt / cmp); 900 } 901 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 902 printf(" DIR=0x%04x", cyrix_did); 903 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 904 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 905 #ifndef CYRIX_CACHE_REALLY_WORKS 906 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 907 printf("\n CPU cache: write-through mode"); 908 #endif 909 } 910 911 /* Avoid ugly blank lines: only print newline when we have to. */ 912 if (*cpu_vendor || cpu_id) 913 printf("\n"); 914 915 if (!bootverbose) 916 return; 917 918 if (cpu_vendor_id == CPU_VENDOR_AMD) 919 print_AMD_info(); 920 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 921 print_INTEL_info(); 922 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 923 print_transmeta_info(); 924 } 925 926 void 927 panicifcpuunsupported(void) 928 { 929 930 #if !defined(lint) 931 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 932 #error This kernel is not configured for one of the supported CPUs 933 #endif 934 #else /* lint */ 935 #endif /* lint */ 936 /* 937 * Now that we have told the user what they have, 938 * let them know if that machine type isn't configured. 939 */ 940 switch (cpu_class) { 941 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 942 case CPUCLASS_386: 943 #if !defined(I486_CPU) 944 case CPUCLASS_486: 945 #endif 946 #if !defined(I586_CPU) 947 case CPUCLASS_586: 948 #endif 949 #if !defined(I686_CPU) 950 case CPUCLASS_686: 951 #endif 952 panic("CPU class not configured"); 953 default: 954 break; 955 } 956 } 957 958 959 static volatile u_int trap_by_rdmsr; 960 961 /* 962 * Special exception 6 handler. 963 * The rdmsr instruction generates invalid opcodes fault on 486-class 964 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 965 * function identblue() when this handler is called. Stacked eip should 966 * be advanced. 967 */ 968 inthand_t bluetrap6; 969 #ifdef __GNUCLIKE_ASM 970 __asm 971 (" \n\ 972 .text \n\ 973 .p2align 2,0x90 \n\ 974 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 975 " __XSTRING(CNAME(bluetrap6)) ": \n\ 976 ss \n\ 977 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 978 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 979 iret \n\ 980 "); 981 #endif 982 983 /* 984 * Special exception 13 handler. 985 * Accessing non-existent MSR generates general protection fault. 986 */ 987 inthand_t bluetrap13; 988 #ifdef __GNUCLIKE_ASM 989 __asm 990 (" \n\ 991 .text \n\ 992 .p2align 2,0x90 \n\ 993 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 994 " __XSTRING(CNAME(bluetrap13)) ": \n\ 995 ss \n\ 996 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 997 popl %eax /* discard error code */ \n\ 998 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 999 iret \n\ 1000 "); 1001 #endif 1002 1003 /* 1004 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1005 * support cpuid instruction. This function should be called after 1006 * loading interrupt descriptor table register. 1007 * 1008 * I don't like this method that handles fault, but I couldn't get 1009 * information for any other methods. Does blue giant know? 1010 */ 1011 static int 1012 identblue(void) 1013 { 1014 1015 trap_by_rdmsr = 0; 1016 1017 /* 1018 * Cyrix 486-class CPU does not support rdmsr instruction. 1019 * The rdmsr instruction generates invalid opcode fault, and exception 1020 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1021 * bluetrap6() set the magic number to trap_by_rdmsr. 1022 */ 1023 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1024 GSEL(GCODE_SEL, SEL_KPL)); 1025 1026 /* 1027 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1028 * In this case, rdmsr generates general protection fault, and 1029 * exception will be trapped by bluetrap13(). 1030 */ 1031 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1032 GSEL(GCODE_SEL, SEL_KPL)); 1033 1034 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1035 1036 if (trap_by_rdmsr == 0xa8c1d) 1037 return IDENTBLUE_CYRIX486; 1038 else if (trap_by_rdmsr == 0xa89c4) 1039 return IDENTBLUE_CYRIXM2; 1040 return IDENTBLUE_IBMCPU; 1041 } 1042 1043 1044 /* 1045 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1046 * 1047 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1048 * +-------+-------+---------------+ 1049 * | SID | RID | Device ID | 1050 * | (DIR 1) | (DIR 0) | 1051 * +-------+-------+---------------+ 1052 */ 1053 static void 1054 identifycyrix(void) 1055 { 1056 u_int eflags; 1057 int ccr2_test = 0, dir_test = 0; 1058 u_char ccr2, ccr3; 1059 1060 eflags = read_eflags(); 1061 disable_intr(); 1062 1063 ccr2 = read_cyrix_reg(CCR2); 1064 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1065 read_cyrix_reg(CCR2); 1066 if (read_cyrix_reg(CCR2) != ccr2) 1067 ccr2_test = 1; 1068 write_cyrix_reg(CCR2, ccr2); 1069 1070 ccr3 = read_cyrix_reg(CCR3); 1071 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1072 read_cyrix_reg(CCR3); 1073 if (read_cyrix_reg(CCR3) != ccr3) 1074 dir_test = 1; /* CPU supports DIRs. */ 1075 write_cyrix_reg(CCR3, ccr3); 1076 1077 if (dir_test) { 1078 /* Device ID registers are available. */ 1079 cyrix_did = read_cyrix_reg(DIR1) << 8; 1080 cyrix_did += read_cyrix_reg(DIR0); 1081 } else if (ccr2_test) 1082 cyrix_did = 0x0010; /* 486S A-step */ 1083 else 1084 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1085 1086 write_eflags(eflags); 1087 } 1088 1089 /* Update TSC freq with the value indicated by the caller. */ 1090 static void 1091 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 1092 { 1093 /* 1094 * If there was an error during the transition or 1095 * TSC is P-state invariant, don't do anything. 1096 */ 1097 if (status != 0 || tsc_is_invariant) 1098 return; 1099 1100 /* Total setting for this level gives the new frequency in MHz. */ 1101 hw_clockrate = level->total_set.freq; 1102 } 1103 1104 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 1105 EVENTHANDLER_PRI_ANY); 1106 1107 /* 1108 * Final stage of CPU identification. -- Should I check TI? 1109 */ 1110 void 1111 finishidentcpu(void) 1112 { 1113 int isblue = 0; 1114 u_char ccr3; 1115 u_int regs[4]; 1116 1117 cpu_vendor_id = find_cpu_vendor_id(); 1118 1119 /* 1120 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 1121 * function number again if it is set from BIOS. It is necessary 1122 * for probing correct CPU topology later. 1123 * XXX This is only done on the BSP package. 1124 */ 1125 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 && 1126 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) || 1127 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1128 uint64_t msr; 1129 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1130 if ((msr & 0x400000ULL) != 0) { 1131 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 1132 do_cpuid(0, regs); 1133 cpu_high = regs[0]; 1134 } 1135 } 1136 1137 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ 1138 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1139 cpu_vendor_id == CPU_VENDOR_AMD) { 1140 init_exthigh(); 1141 if (cpu_exthigh >= 0x80000001) { 1142 do_cpuid(0x80000001, regs); 1143 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1144 amd_feature2 = regs[2]; 1145 } 1146 if (cpu_exthigh >= 0x80000007) { 1147 do_cpuid(0x80000007, regs); 1148 amd_pminfo = regs[3]; 1149 } 1150 if (cpu_exthigh >= 0x80000008) { 1151 do_cpuid(0x80000008, regs); 1152 cpu_procinfo2 = regs[2]; 1153 } 1154 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1155 if (cpu == CPU_486) { 1156 /* 1157 * These conditions are equivalent to: 1158 * - CPU does not support cpuid instruction. 1159 * - Cyrix/IBM CPU is detected. 1160 */ 1161 isblue = identblue(); 1162 if (isblue == IDENTBLUE_IBMCPU) { 1163 strcpy(cpu_vendor, "IBM"); 1164 cpu_vendor_id = CPU_VENDOR_IBM; 1165 cpu = CPU_BLUE; 1166 return; 1167 } 1168 } 1169 switch (cpu_id & 0xf00) { 1170 case 0x600: 1171 /* 1172 * Cyrix's datasheet does not describe DIRs. 1173 * Therefor, I assume it does not have them 1174 * and use the result of the cpuid instruction. 1175 * XXX they seem to have it for now at least. -Peter 1176 */ 1177 identifycyrix(); 1178 cpu = CPU_M2; 1179 break; 1180 default: 1181 identifycyrix(); 1182 /* 1183 * This routine contains a trick. 1184 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1185 */ 1186 switch (cyrix_did & 0x00f0) { 1187 case 0x00: 1188 case 0xf0: 1189 cpu = CPU_486DLC; 1190 break; 1191 case 0x10: 1192 cpu = CPU_CY486DX; 1193 break; 1194 case 0x20: 1195 if ((cyrix_did & 0x000f) < 8) 1196 cpu = CPU_M1; 1197 else 1198 cpu = CPU_M1SC; 1199 break; 1200 case 0x30: 1201 cpu = CPU_M1; 1202 break; 1203 case 0x40: 1204 /* MediaGX CPU */ 1205 cpu = CPU_M1SC; 1206 break; 1207 default: 1208 /* M2 and later CPUs are treated as M2. */ 1209 cpu = CPU_M2; 1210 1211 /* 1212 * enable cpuid instruction. 1213 */ 1214 ccr3 = read_cyrix_reg(CCR3); 1215 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1216 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1217 write_cyrix_reg(CCR3, ccr3); 1218 1219 do_cpuid(0, regs); 1220 cpu_high = regs[0]; /* eax */ 1221 do_cpuid(1, regs); 1222 cpu_id = regs[0]; /* eax */ 1223 cpu_feature = regs[3]; /* edx */ 1224 break; 1225 } 1226 } 1227 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1228 /* 1229 * There are BlueLightning CPUs that do not change 1230 * undefined flags by dividing 5 by 2. In this case, 1231 * the CPU identification routine in locore.s leaves 1232 * cpu_vendor null string and puts CPU_486 into the 1233 * cpu. 1234 */ 1235 isblue = identblue(); 1236 if (isblue == IDENTBLUE_IBMCPU) { 1237 strcpy(cpu_vendor, "IBM"); 1238 cpu_vendor_id = CPU_VENDOR_IBM; 1239 cpu = CPU_BLUE; 1240 return; 1241 } 1242 } 1243 } 1244 1245 static u_int 1246 find_cpu_vendor_id(void) 1247 { 1248 int i; 1249 1250 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 1251 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1252 return (cpu_vendors[i].vendor_id); 1253 return (0); 1254 } 1255 1256 static void 1257 print_AMD_assoc(int i) 1258 { 1259 if (i == 255) 1260 printf(", fully associative\n"); 1261 else 1262 printf(", %d-way associative\n", i); 1263 } 1264 1265 static void 1266 print_AMD_info(void) 1267 { 1268 quad_t amd_whcr; 1269 1270 if (cpu_exthigh >= 0x80000005) { 1271 u_int regs[4]; 1272 1273 do_cpuid(0x80000005, regs); 1274 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); 1275 print_AMD_assoc(regs[1] >> 24); 1276 printf("Instruction TLB: %d entries", regs[1] & 0xff); 1277 print_AMD_assoc((regs[1] >> 8) & 0xff); 1278 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1279 printf(", %d bytes/line", regs[2] & 0xff); 1280 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1281 print_AMD_assoc((regs[2] >> 16) & 0xff); 1282 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1283 printf(", %d bytes/line", regs[3] & 0xff); 1284 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1285 print_AMD_assoc((regs[3] >> 16) & 0xff); 1286 if (cpu_exthigh >= 0x80000006) { /* K6-III only */ 1287 do_cpuid(0x80000006, regs); 1288 printf("L2 internal cache: %d kbytes", regs[2] >> 16); 1289 printf(", %d bytes/line", regs[2] & 0xff); 1290 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1291 print_AMD_assoc((regs[2] >> 12) & 0x0f); 1292 } 1293 } 1294 if (((cpu_id & 0xf00) == 0x500) 1295 && (((cpu_id & 0x0f0) > 0x80) 1296 || (((cpu_id & 0x0f0) == 0x80) 1297 && (cpu_id & 0x00f) > 0x07))) { 1298 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1299 amd_whcr = rdmsr(0xc0000082); 1300 if (!(amd_whcr & (0x3ff << 22))) { 1301 printf("Write Allocate Disable\n"); 1302 } else { 1303 printf("Write Allocate Enable Limit: %dM bytes\n", 1304 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1305 printf("Write Allocate 15-16M bytes: %s\n", 1306 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1307 } 1308 } else if (((cpu_id & 0xf00) == 0x500) 1309 && ((cpu_id & 0x0f0) > 0x50)) { 1310 /* K6, K6-2(old core) */ 1311 amd_whcr = rdmsr(0xc0000082); 1312 if (!(amd_whcr & (0x7f << 1))) { 1313 printf("Write Allocate Disable\n"); 1314 } else { 1315 printf("Write Allocate Enable Limit: %dM bytes\n", 1316 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1317 printf("Write Allocate 15-16M bytes: %s\n", 1318 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1319 printf("Hardware Write Allocate Control: %s\n", 1320 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1321 } 1322 } 1323 1324 /* 1325 * Opteron Rev E shows a bug as in very rare occasions a read memory 1326 * barrier is not performed as expected if it is followed by a 1327 * non-atomic read-modify-write instruction. 1328 * As long as that bug pops up very rarely (intensive machine usage 1329 * on other operating systems generally generates one unexplainable 1330 * crash any 2 months) and as long as a model specific fix would be 1331 * impratical at this stage, print out a warning string if the broken 1332 * model and family are identified. 1333 */ 1334 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1335 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1336 printf("WARNING: This architecture revision has known SMP " 1337 "hardware bugs which may cause random instability\n"); 1338 } 1339 1340 static void 1341 print_INTEL_info(void) 1342 { 1343 u_int regs[4]; 1344 u_int rounds, regnum; 1345 u_int nwaycode, nway; 1346 1347 if (cpu_high >= 2) { 1348 rounds = 0; 1349 do { 1350 do_cpuid(0x2, regs); 1351 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1352 break; /* we have a buggy CPU */ 1353 1354 for (regnum = 0; regnum <= 3; ++regnum) { 1355 if (regs[regnum] & (1<<31)) 1356 continue; 1357 if (regnum != 0) 1358 print_INTEL_TLB(regs[regnum] & 0xff); 1359 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1360 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1361 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1362 } 1363 } while (--rounds > 0); 1364 } 1365 1366 if (cpu_exthigh >= 0x80000006) { 1367 do_cpuid(0x80000006, regs); 1368 nwaycode = (regs[2] >> 12) & 0x0f; 1369 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1370 nway = 1 << (nwaycode / 2); 1371 else 1372 nway = 0; 1373 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line", 1374 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1375 } 1376 1377 printf("\n"); 1378 } 1379 1380 static void 1381 print_INTEL_TLB(u_int data) 1382 { 1383 switch (data) { 1384 case 0x0: 1385 case 0x40: 1386 default: 1387 break; 1388 case 0x1: 1389 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries"); 1390 break; 1391 case 0x2: 1392 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries"); 1393 break; 1394 case 0x3: 1395 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries"); 1396 break; 1397 case 0x4: 1398 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries"); 1399 break; 1400 case 0x6: 1401 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size"); 1402 break; 1403 case 0x8: 1404 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size"); 1405 break; 1406 case 0xa: 1407 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size"); 1408 break; 1409 case 0xc: 1410 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size"); 1411 break; 1412 case 0x22: 1413 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size"); 1414 break; 1415 case 0x23: 1416 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1417 break; 1418 case 0x25: 1419 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size"); 1420 break; 1421 case 0x29: 1422 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size"); 1423 break; 1424 case 0x2c: 1425 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size"); 1426 break; 1427 case 0x30: 1428 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size"); 1429 break; 1430 case 0x39: 1431 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size"); 1432 break; 1433 case 0x3b: 1434 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size"); 1435 break; 1436 case 0x3c: 1437 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size"); 1438 break; 1439 case 0x41: 1440 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size"); 1441 break; 1442 case 0x42: 1443 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size"); 1444 break; 1445 case 0x43: 1446 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size"); 1447 break; 1448 case 0x44: 1449 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size"); 1450 break; 1451 case 0x45: 1452 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size"); 1453 break; 1454 case 0x46: 1455 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size"); 1456 break; 1457 case 0x47: 1458 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size"); 1459 break; 1460 case 0x50: 1461 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries"); 1462 break; 1463 case 0x51: 1464 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries"); 1465 break; 1466 case 0x52: 1467 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries"); 1468 break; 1469 case 0x5b: 1470 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries"); 1471 break; 1472 case 0x5c: 1473 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries"); 1474 break; 1475 case 0x5d: 1476 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries"); 1477 break; 1478 case 0x60: 1479 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size"); 1480 break; 1481 case 0x66: 1482 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size"); 1483 break; 1484 case 0x67: 1485 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size"); 1486 break; 1487 case 0x68: 1488 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size"); 1489 break; 1490 case 0x70: 1491 printf("\nTrace cache: 12K-uops, 8-way set associative"); 1492 break; 1493 case 0x71: 1494 printf("\nTrace cache: 16K-uops, 8-way set associative"); 1495 break; 1496 case 0x72: 1497 printf("\nTrace cache: 32K-uops, 8-way set associative"); 1498 break; 1499 case 0x78: 1500 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size"); 1501 break; 1502 case 0x79: 1503 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size"); 1504 break; 1505 case 0x7a: 1506 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size"); 1507 break; 1508 case 0x7b: 1509 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size"); 1510 break; 1511 case 0x7c: 1512 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size"); 1513 break; 1514 case 0x7d: 1515 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size"); 1516 break; 1517 case 0x7f: 1518 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size"); 1519 break; 1520 case 0x82: 1521 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size"); 1522 break; 1523 case 0x83: 1524 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size"); 1525 break; 1526 case 0x84: 1527 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size"); 1528 break; 1529 case 0x85: 1530 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size"); 1531 break; 1532 case 0x86: 1533 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size"); 1534 break; 1535 case 0x87: 1536 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size"); 1537 break; 1538 case 0xb0: 1539 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1540 break; 1541 case 0xb3: 1542 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries"); 1543 break; 1544 } 1545 } 1546 1547 static void 1548 print_transmeta_info(void) 1549 { 1550 u_int regs[4], nreg = 0; 1551 1552 do_cpuid(0x80860000, regs); 1553 nreg = regs[0]; 1554 if (nreg >= 0x80860001) { 1555 do_cpuid(0x80860001, regs); 1556 printf(" Processor revision %u.%u.%u.%u\n", 1557 (regs[1] >> 24) & 0xff, 1558 (regs[1] >> 16) & 0xff, 1559 (regs[1] >> 8) & 0xff, 1560 regs[1] & 0xff); 1561 } 1562 if (nreg >= 0x80860002) { 1563 do_cpuid(0x80860002, regs); 1564 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 1565 (regs[1] >> 24) & 0xff, 1566 (regs[1] >> 16) & 0xff, 1567 (regs[1] >> 8) & 0xff, 1568 regs[1] & 0xff, 1569 regs[2]); 1570 } 1571 if (nreg >= 0x80860006) { 1572 char info[65]; 1573 do_cpuid(0x80860003, (u_int*) &info[0]); 1574 do_cpuid(0x80860004, (u_int*) &info[16]); 1575 do_cpuid(0x80860005, (u_int*) &info[32]); 1576 do_cpuid(0x80860006, (u_int*) &info[48]); 1577 info[64] = 0; 1578 printf(" %s\n", info); 1579 } 1580 } 1581 1582 static void 1583 print_via_padlock_info(void) 1584 { 1585 u_int regs[4]; 1586 1587 /* Check for supported models. */ 1588 switch (cpu_id & 0xff0) { 1589 case 0x690: 1590 if ((cpu_id & 0xf) < 3) 1591 return; 1592 case 0x6a0: 1593 case 0x6d0: 1594 case 0x6f0: 1595 break; 1596 default: 1597 return; 1598 } 1599 1600 do_cpuid(0xc0000000, regs); 1601 if (regs[0] >= 0xc0000001) 1602 do_cpuid(0xc0000001, regs); 1603 else 1604 return; 1605 1606 printf("\n VIA Padlock Features=0x%b", regs[3], 1607 "\020" 1608 "\003RNG" /* RNG */ 1609 "\007AES" /* ACE */ 1610 "\011AES-CTR" /* ACE2 */ 1611 "\013SHA1,SHA256" /* PHE */ 1612 "\015RSA" /* PMM */ 1613 ); 1614 }
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