1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
54
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
62
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
66
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
75 #endif
76 void panicifcpuunsupported(void);
77
78 static void identifycyrix(void);
79 static void init_exthigh(void);
80 static u_int find_cpu_vendor_id(void);
81 static void print_AMD_info(void);
82 static void print_INTEL_info(void);
83 static void print_INTEL_TLB(u_int data);
84 static void print_AMD_assoc(int i);
85 static void print_transmeta_info(void);
86 static void print_via_padlock_info(void);
87
88 int cpu_class;
89 u_int cpu_exthigh; /* Highest arg to extended CPUID */
90 u_int cyrix_did; /* Device ID of Cyrix CPU */
91 char machine[] = MACHINE;
92 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
93 machine, 0, "Machine class");
94
95 static char cpu_model[128];
96 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
97 cpu_model, 0, "Machine model");
98
99 static int hw_clockrate;
100 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
101 &hw_clockrate, 0, "CPU instruction clock rate");
102
103 static char cpu_brand[48];
104
105 #define MAX_BRAND_INDEX 8
106
107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
108 NULL, /* No brand */
109 "Intel Celeron",
110 "Intel Pentium III",
111 "Intel Pentium III Xeon",
112 NULL,
113 NULL,
114 NULL,
115 NULL,
116 "Intel Pentium 4"
117 };
118
119 static struct {
120 char *cpu_name;
121 int cpu_class;
122 } i386_cpus[] = {
123 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
124 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
125 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
126 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
127 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
128 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
129 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
130 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
131 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
132 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
133 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
134 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
135 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
136 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
137 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
138 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
139 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
140 };
141
142 static struct {
143 char *vendor;
144 u_int vendor_id;
145 } cpu_vendors[] = {
146 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
147 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
148 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
149 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
150 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
151 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
152 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
153 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
154 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
155 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
156 #if 0
157 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
158 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
159 #endif
160 };
161
162 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
163 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
164 #endif
165
166 static void
167 init_exthigh(void)
168 {
169 static int done = 0;
170 u_int regs[4];
171
172 if (done == 0) {
173 if (cpu_high > 0 &&
174 (cpu_vendor_id == CPU_VENDOR_INTEL ||
175 cpu_vendor_id == CPU_VENDOR_AMD ||
176 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
177 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
178 cpu_vendor_id == CPU_VENDOR_NSC)) {
179 do_cpuid(0x80000000, regs);
180 if (regs[0] >= 0x80000000)
181 cpu_exthigh = regs[0];
182 }
183
184 done = 1;
185 }
186 }
187
188 void
189 printcpuinfo(void)
190 {
191 u_int regs[4], i;
192 char *brand;
193
194 cpu_class = i386_cpus[cpu].cpu_class;
195 printf("CPU: ");
196 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
197
198 /* Check for extended CPUID information and a processor name. */
199 init_exthigh();
200 if (cpu_exthigh >= 0x80000004) {
201 brand = cpu_brand;
202 for (i = 0x80000002; i < 0x80000005; i++) {
203 do_cpuid(i, regs);
204 memcpy(brand, regs, sizeof(regs));
205 brand += sizeof(regs);
206 }
207 }
208
209 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
210 if ((cpu_id & 0xf00) > 0x300) {
211 u_int brand_index;
212
213 cpu_model[0] = '\0';
214
215 switch (cpu_id & 0x3000) {
216 case 0x1000:
217 strcpy(cpu_model, "Overdrive ");
218 break;
219 case 0x2000:
220 strcpy(cpu_model, "Dual ");
221 break;
222 }
223
224 switch (cpu_id & 0xf00) {
225 case 0x400:
226 strcat(cpu_model, "i486 ");
227 /* Check the particular flavor of 486 */
228 switch (cpu_id & 0xf0) {
229 case 0x00:
230 case 0x10:
231 strcat(cpu_model, "DX");
232 break;
233 case 0x20:
234 strcat(cpu_model, "SX");
235 break;
236 case 0x30:
237 strcat(cpu_model, "DX2");
238 break;
239 case 0x40:
240 strcat(cpu_model, "SL");
241 break;
242 case 0x50:
243 strcat(cpu_model, "SX2");
244 break;
245 case 0x70:
246 strcat(cpu_model,
247 "DX2 Write-Back Enhanced");
248 break;
249 case 0x80:
250 strcat(cpu_model, "DX4");
251 break;
252 }
253 break;
254 case 0x500:
255 /* Check the particular flavor of 586 */
256 strcat(cpu_model, "Pentium");
257 switch (cpu_id & 0xf0) {
258 case 0x00:
259 strcat(cpu_model, " A-step");
260 break;
261 case 0x10:
262 strcat(cpu_model, "/P5");
263 break;
264 case 0x20:
265 strcat(cpu_model, "/P54C");
266 break;
267 case 0x30:
268 strcat(cpu_model, "/P24T");
269 break;
270 case 0x40:
271 strcat(cpu_model, "/P55C");
272 break;
273 case 0x70:
274 strcat(cpu_model, "/P54C");
275 break;
276 case 0x80:
277 strcat(cpu_model, "/P55C (quarter-micron)");
278 break;
279 default:
280 /* nothing */
281 break;
282 }
283 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
284 /*
285 * XXX - If/when Intel fixes the bug, this
286 * should also check the version of the
287 * CPU, not just that it's a Pentium.
288 */
289 has_f00f_bug = 1;
290 #endif
291 break;
292 case 0x600:
293 /* Check the particular flavor of 686 */
294 switch (cpu_id & 0xf0) {
295 case 0x00:
296 strcat(cpu_model, "Pentium Pro A-step");
297 break;
298 case 0x10:
299 strcat(cpu_model, "Pentium Pro");
300 break;
301 case 0x30:
302 case 0x50:
303 case 0x60:
304 strcat(cpu_model,
305 "Pentium II/Pentium II Xeon/Celeron");
306 cpu = CPU_PII;
307 break;
308 case 0x70:
309 case 0x80:
310 case 0xa0:
311 case 0xb0:
312 strcat(cpu_model,
313 "Pentium III/Pentium III Xeon/Celeron");
314 cpu = CPU_PIII;
315 break;
316 default:
317 strcat(cpu_model, "Unknown 80686");
318 break;
319 }
320 break;
321 case 0xf00:
322 strcat(cpu_model, "Pentium 4");
323 cpu = CPU_P4;
324 break;
325 default:
326 strcat(cpu_model, "unknown");
327 break;
328 }
329
330 /*
331 * If we didn't get a brand name from the extended
332 * CPUID, try to look it up in the brand table.
333 */
334 if (cpu_high > 0 && *cpu_brand == '\0') {
335 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
336 if (brand_index <= MAX_BRAND_INDEX &&
337 cpu_brandtable[brand_index] != NULL)
338 strcpy(cpu_brand,
339 cpu_brandtable[brand_index]);
340 }
341 }
342 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
343 /*
344 * Values taken from AMD Processor Recognition
345 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
346 * (also describes ``Features'' encodings.
347 */
348 strcpy(cpu_model, "AMD ");
349 switch (cpu_id & 0xFF0) {
350 case 0x410:
351 strcat(cpu_model, "Standard Am486DX");
352 break;
353 case 0x430:
354 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
355 break;
356 case 0x470:
357 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
358 break;
359 case 0x480:
360 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
361 break;
362 case 0x490:
363 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
364 break;
365 case 0x4E0:
366 strcat(cpu_model, "Am5x86 Write-Through");
367 break;
368 case 0x4F0:
369 strcat(cpu_model, "Am5x86 Write-Back");
370 break;
371 case 0x500:
372 strcat(cpu_model, "K5 model 0");
373 tsc_is_broken = 1;
374 break;
375 case 0x510:
376 strcat(cpu_model, "K5 model 1");
377 break;
378 case 0x520:
379 strcat(cpu_model, "K5 PR166 (model 2)");
380 break;
381 case 0x530:
382 strcat(cpu_model, "K5 PR200 (model 3)");
383 break;
384 case 0x560:
385 strcat(cpu_model, "K6");
386 break;
387 case 0x570:
388 strcat(cpu_model, "K6 266 (model 1)");
389 break;
390 case 0x580:
391 strcat(cpu_model, "K6-2");
392 break;
393 case 0x590:
394 strcat(cpu_model, "K6-III");
395 break;
396 case 0x5a0:
397 strcat(cpu_model, "Geode LX");
398 /*
399 * Make sure the TSC runs through suspension,
400 * otherwise we can't use it as timecounter
401 */
402 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
403 break;
404 default:
405 strcat(cpu_model, "Unknown");
406 break;
407 }
408 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
409 if ((cpu_id & 0xf00) == 0x500) {
410 if (((cpu_id & 0x0f0) > 0)
411 && ((cpu_id & 0x0f0) < 0x60)
412 && ((cpu_id & 0x00f) > 3))
413 enable_K5_wt_alloc();
414 else if (((cpu_id & 0x0f0) > 0x80)
415 || (((cpu_id & 0x0f0) == 0x80)
416 && (cpu_id & 0x00f) > 0x07))
417 enable_K6_2_wt_alloc();
418 else if ((cpu_id & 0x0f0) > 0x50)
419 enable_K6_wt_alloc();
420 }
421 #endif
422 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
423 strcpy(cpu_model, "Cyrix ");
424 switch (cpu_id & 0xff0) {
425 case 0x440:
426 strcat(cpu_model, "MediaGX");
427 break;
428 case 0x520:
429 strcat(cpu_model, "6x86");
430 break;
431 case 0x540:
432 cpu_class = CPUCLASS_586;
433 strcat(cpu_model, "GXm");
434 break;
435 case 0x600:
436 strcat(cpu_model, "6x86MX");
437 break;
438 default:
439 /*
440 * Even though CPU supports the cpuid
441 * instruction, it can be disabled.
442 * Therefore, this routine supports all Cyrix
443 * CPUs.
444 */
445 switch (cyrix_did & 0xf0) {
446 case 0x00:
447 switch (cyrix_did & 0x0f) {
448 case 0x00:
449 strcat(cpu_model, "486SLC");
450 break;
451 case 0x01:
452 strcat(cpu_model, "486DLC");
453 break;
454 case 0x02:
455 strcat(cpu_model, "486SLC2");
456 break;
457 case 0x03:
458 strcat(cpu_model, "486DLC2");
459 break;
460 case 0x04:
461 strcat(cpu_model, "486SRx");
462 break;
463 case 0x05:
464 strcat(cpu_model, "486DRx");
465 break;
466 case 0x06:
467 strcat(cpu_model, "486SRx2");
468 break;
469 case 0x07:
470 strcat(cpu_model, "486DRx2");
471 break;
472 case 0x08:
473 strcat(cpu_model, "486SRu");
474 break;
475 case 0x09:
476 strcat(cpu_model, "486DRu");
477 break;
478 case 0x0a:
479 strcat(cpu_model, "486SRu2");
480 break;
481 case 0x0b:
482 strcat(cpu_model, "486DRu2");
483 break;
484 default:
485 strcat(cpu_model, "Unknown");
486 break;
487 }
488 break;
489 case 0x10:
490 switch (cyrix_did & 0x0f) {
491 case 0x00:
492 strcat(cpu_model, "486S");
493 break;
494 case 0x01:
495 strcat(cpu_model, "486S2");
496 break;
497 case 0x02:
498 strcat(cpu_model, "486Se");
499 break;
500 case 0x03:
501 strcat(cpu_model, "486S2e");
502 break;
503 case 0x0a:
504 strcat(cpu_model, "486DX");
505 break;
506 case 0x0b:
507 strcat(cpu_model, "486DX2");
508 break;
509 case 0x0f:
510 strcat(cpu_model, "486DX4");
511 break;
512 default:
513 strcat(cpu_model, "Unknown");
514 break;
515 }
516 break;
517 case 0x20:
518 if ((cyrix_did & 0x0f) < 8)
519 strcat(cpu_model, "6x86"); /* Where did you get it? */
520 else
521 strcat(cpu_model, "5x86");
522 break;
523 case 0x30:
524 strcat(cpu_model, "6x86");
525 break;
526 case 0x40:
527 if ((cyrix_did & 0xf000) == 0x3000) {
528 cpu_class = CPUCLASS_586;
529 strcat(cpu_model, "GXm");
530 } else
531 strcat(cpu_model, "MediaGX");
532 break;
533 case 0x50:
534 strcat(cpu_model, "6x86MX");
535 break;
536 case 0xf0:
537 switch (cyrix_did & 0x0f) {
538 case 0x0d:
539 strcat(cpu_model, "Overdrive CPU");
540 break;
541 case 0x0e:
542 strcpy(cpu_model, "Texas Instruments 486SXL");
543 break;
544 case 0x0f:
545 strcat(cpu_model, "486SLC/DLC");
546 break;
547 default:
548 strcat(cpu_model, "Unknown");
549 break;
550 }
551 break;
552 default:
553 strcat(cpu_model, "Unknown");
554 break;
555 }
556 break;
557 }
558 } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
559 strcpy(cpu_model, "Rise ");
560 switch (cpu_id & 0xff0) {
561 case 0x500:
562 strcat(cpu_model, "mP6");
563 break;
564 default:
565 strcat(cpu_model, "Unknown");
566 }
567 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
568 switch (cpu_id & 0xff0) {
569 case 0x540:
570 strcpy(cpu_model, "IDT WinChip C6");
571 tsc_is_broken = 1;
572 break;
573 case 0x580:
574 strcpy(cpu_model, "IDT WinChip 2");
575 break;
576 case 0x660:
577 strcpy(cpu_model, "VIA C3 Samuel");
578 break;
579 case 0x670:
580 if (cpu_id & 0x8)
581 strcpy(cpu_model, "VIA C3 Ezra");
582 else
583 strcpy(cpu_model, "VIA C3 Samuel 2");
584 break;
585 case 0x680:
586 strcpy(cpu_model, "VIA C3 Ezra-T");
587 break;
588 case 0x690:
589 strcpy(cpu_model, "VIA C3 Nehemiah");
590 break;
591 case 0x6a0:
592 case 0x6d0:
593 strcpy(cpu_model, "VIA C7 Esther");
594 break;
595 case 0x6f0:
596 strcpy(cpu_model, "VIA Nano");
597 break;
598 default:
599 strcpy(cpu_model, "VIA/IDT Unknown");
600 }
601 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
602 strcpy(cpu_model, "Blue Lightning CPU");
603 } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
604 switch (cpu_id & 0xfff) {
605 case 0x540:
606 strcpy(cpu_model, "Geode SC1100");
607 cpu = CPU_GEODE1100;
608 tsc_is_broken = 1;
609 break;
610 default:
611 strcpy(cpu_model, "Geode/NSC unknown");
612 break;
613 }
614 }
615
616 /*
617 * Replace cpu_model with cpu_brand minus leading spaces if
618 * we have one.
619 */
620 brand = cpu_brand;
621 while (*brand == ' ')
622 ++brand;
623 if (*brand != '\0')
624 strcpy(cpu_model, brand);
625
626 printf("%s (", cpu_model);
627 switch(cpu_class) {
628 case CPUCLASS_286:
629 printf("286");
630 break;
631 case CPUCLASS_386:
632 printf("386");
633 break;
634 #if defined(I486_CPU)
635 case CPUCLASS_486:
636 printf("486");
637 break;
638 #endif
639 #if defined(I586_CPU)
640 case CPUCLASS_586:
641 hw_clockrate = (tsc_freq + 5000) / 1000000;
642 printf("%jd.%02d-MHz ",
643 (intmax_t)(tsc_freq + 4999) / 1000000,
644 (u_int)((tsc_freq + 4999) / 10000) % 100);
645 printf("586");
646 break;
647 #endif
648 #if defined(I686_CPU)
649 case CPUCLASS_686:
650 hw_clockrate = (tsc_freq + 5000) / 1000000;
651 printf("%jd.%02d-MHz ",
652 (intmax_t)(tsc_freq + 4999) / 1000000,
653 (u_int)((tsc_freq + 4999) / 10000) % 100);
654 printf("686");
655 break;
656 #endif
657 default:
658 printf("Unknown"); /* will panic below... */
659 }
660 printf("-class CPU)\n");
661 if(*cpu_vendor)
662 printf(" Origin = \"%s\"",cpu_vendor);
663 if(cpu_id)
664 printf(" Id = 0x%x", cpu_id);
665
666 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
667 cpu_vendor_id == CPU_VENDOR_AMD ||
668 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
669 cpu_vendor_id == CPU_VENDOR_RISE ||
670 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
671 cpu_vendor_id == CPU_VENDOR_NSC ||
672 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
673 ((cpu_id & 0xf00) > 0x500))) {
674 printf(" Family = %x", CPUID_TO_FAMILY(cpu_id));
675 printf(" Model = %x", CPUID_TO_MODEL(cpu_id));
676 printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
677 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
678 printf("\n DIR=0x%04x", cyrix_did);
679 /*
680 * AMD CPUID Specification
681 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
682 *
683 * Intel Processor Identification and CPUID Instruction
684 * http://www.intel.com/assets/pdf/appnote/241618.pdf
685 */
686 if (cpu_high > 0) {
687
688 /*
689 * Here we should probably set up flags indicating
690 * whether or not various features are available.
691 * The interesting ones are probably VME, PSE, PAE,
692 * and PGE. The code already assumes without bothering
693 * to check that all CPUs >= Pentium have a TSC and
694 * MSRs.
695 */
696 printf("\n Features=0x%b", cpu_feature,
697 "\020"
698 "\001FPU" /* Integral FPU */
699 "\002VME" /* Extended VM86 mode support */
700 "\003DE" /* Debugging Extensions (CR4.DE) */
701 "\004PSE" /* 4MByte page tables */
702 "\005TSC" /* Timestamp counter */
703 "\006MSR" /* Machine specific registers */
704 "\007PAE" /* Physical address extension */
705 "\010MCE" /* Machine Check support */
706 "\011CX8" /* CMPEXCH8 instruction */
707 "\012APIC" /* SMP local APIC */
708 "\013oldMTRR" /* Previous implementation of MTRR */
709 "\014SEP" /* Fast System Call */
710 "\015MTRR" /* Memory Type Range Registers */
711 "\016PGE" /* PG_G (global bit) support */
712 "\017MCA" /* Machine Check Architecture */
713 "\020CMOV" /* CMOV instruction */
714 "\021PAT" /* Page attributes table */
715 "\022PSE36" /* 36 bit address space support */
716 "\023PN" /* Processor Serial number */
717 "\024CLFLUSH" /* Has the CLFLUSH instruction */
718 "\025<b20>"
719 "\026DTS" /* Debug Trace Store */
720 "\027ACPI" /* ACPI support */
721 "\030MMX" /* MMX instructions */
722 "\031FXSR" /* FXSAVE/FXRSTOR */
723 "\032SSE" /* Streaming SIMD Extensions */
724 "\033SSE2" /* Streaming SIMD Extensions #2 */
725 "\034SS" /* Self snoop */
726 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
727 "\036TM" /* Thermal Monitor clock slowdown */
728 "\037IA64" /* CPU can execute IA64 instructions */
729 "\040PBE" /* Pending Break Enable */
730 );
731
732 if (cpu_feature2 != 0) {
733 printf("\n Features2=0x%b", cpu_feature2,
734 "\020"
735 "\001SSE3" /* SSE3 */
736 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
737 "\003DTES64" /* 64-bit Debug Trace */
738 "\004MON" /* MONITOR/MWAIT Instructions */
739 "\005DS_CPL" /* CPL Qualified Debug Store */
740 "\006VMX" /* Virtual Machine Extensions */
741 "\007SMX" /* Safer Mode Extensions */
742 "\010EST" /* Enhanced SpeedStep */
743 "\011TM2" /* Thermal Monitor 2 */
744 "\012SSSE3" /* SSSE3 */
745 "\013CNXT-ID" /* L1 context ID available */
746 "\014<b11>"
747 "\015FMA" /* Fused Multiply Add */
748 "\016CX16" /* CMPXCHG16B Instruction */
749 "\017xTPR" /* Send Task Priority Messages*/
750 "\020PDCM" /* Perf/Debug Capability MSR */
751 "\021<b16>"
752 "\022PCID" /* Process-context Identifiers*/
753 "\023DCA" /* Direct Cache Access */
754 "\024SSE4.1" /* SSE 4.1 */
755 "\025SSE4.2" /* SSE 4.2 */
756 "\026x2APIC" /* xAPIC Extensions */
757 "\027MOVBE" /* MOVBE Instruction */
758 "\030POPCNT" /* POPCNT Instruction */
759 "\031TSCDLT" /* TSC-Deadline Timer */
760 "\032AESNI" /* AES Crypto */
761 "\033XSAVE" /* XSAVE/XRSTOR States */
762 "\034OSXSAVE" /* OS-Enabled State Management*/
763 "\035AVX" /* Advanced Vector Extensions */
764 "\036F16C" /* Half-precision conversions */
765 "\037RDRAND" /* RDRAND Instruction */
766 "\040HV" /* Hypervisor */
767 );
768 }
769
770 if (amd_feature != 0) {
771 printf("\n AMD Features=0x%b", amd_feature,
772 "\020" /* in hex */
773 "\001<s0>" /* Same */
774 "\002<s1>" /* Same */
775 "\003<s2>" /* Same */
776 "\004<s3>" /* Same */
777 "\005<s4>" /* Same */
778 "\006<s5>" /* Same */
779 "\007<s6>" /* Same */
780 "\010<s7>" /* Same */
781 "\011<s8>" /* Same */
782 "\012<s9>" /* Same */
783 "\013<b10>" /* Undefined */
784 "\014SYSCALL" /* Have SYSCALL/SYSRET */
785 "\015<s12>" /* Same */
786 "\016<s13>" /* Same */
787 "\017<s14>" /* Same */
788 "\020<s15>" /* Same */
789 "\021<s16>" /* Same */
790 "\022<s17>" /* Same */
791 "\023<b18>" /* Reserved, unknown */
792 "\024MP" /* Multiprocessor Capable */
793 "\025NX" /* Has EFER.NXE, NX */
794 "\026<b21>" /* Undefined */
795 "\027MMX+" /* AMD MMX Extensions */
796 "\030<s23>" /* Same */
797 "\031<s24>" /* Same */
798 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
799 "\033Page1GB" /* 1-GB large page support */
800 "\034RDTSCP" /* RDTSCP */
801 "\035<b28>" /* Undefined */
802 "\036LM" /* 64 bit long mode */
803 "\0373DNow!+" /* AMD 3DNow! Extensions */
804 "\0403DNow!" /* AMD 3DNow! */
805 );
806 }
807
808 if (amd_feature2 != 0) {
809 printf("\n AMD Features2=0x%b", amd_feature2,
810 "\020"
811 "\001LAHF" /* LAHF/SAHF in long mode */
812 "\002CMP" /* CMP legacy */
813 "\003SVM" /* Secure Virtual Mode */
814 "\004ExtAPIC" /* Extended APIC register */
815 "\005CR8" /* CR8 in legacy mode */
816 "\006ABM" /* LZCNT instruction */
817 "\007SSE4A" /* SSE4A */
818 "\010MAS" /* Misaligned SSE mode */
819 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
820 "\012OSVW" /* OS visible workaround */
821 "\013IBS" /* Instruction based sampling */
822 "\014XOP" /* XOP extended instructions */
823 "\015SKINIT" /* SKINIT/STGI */
824 "\016WDT" /* Watchdog timer */
825 "\017<b14>"
826 "\020LWP" /* Lightweight Profiling */
827 "\021FMA4" /* 4-operand FMA instructions */
828 "\022<b17>"
829 "\023<b18>"
830 "\024NodeId" /* NodeId MSR support */
831 "\025<b20>"
832 "\026TBM" /* Trailing Bit Manipulation */
833 "\027Topology" /* Topology Extensions */
834 "\030<b23>"
835 "\031<b24>"
836 "\032<b25>"
837 "\033<b26>"
838 "\034<b27>"
839 "\035<b28>"
840 "\036<b29>"
841 "\037<b30>"
842 "\040<b31>"
843 );
844 }
845
846 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
847 print_via_padlock_info();
848
849 if ((cpu_feature & CPUID_HTT) &&
850 cpu_vendor_id == CPU_VENDOR_AMD)
851 cpu_feature &= ~CPUID_HTT;
852
853 /*
854 * If this CPU supports P-state invariant TSC then
855 * mention the capability.
856 */
857 switch (cpu_vendor_id) {
858 case CPU_VENDOR_AMD:
859 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
860 CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
861 cpu_id == 0x60fb2)
862 tsc_is_invariant = 1;
863 break;
864 case CPU_VENDOR_INTEL:
865 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
866 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
867 CPUID_TO_MODEL(cpu_id) >= 0xe) ||
868 (CPUID_TO_FAMILY(cpu_id) == 0xf &&
869 CPUID_TO_MODEL(cpu_id) >= 0x3))
870 tsc_is_invariant = 1;
871 break;
872 case CPU_VENDOR_CENTAUR:
873 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
874 CPUID_TO_MODEL(cpu_id) >= 0xf &&
875 (rdmsr(0x1203) & 0x100000000ULL) == 0)
876 tsc_is_invariant = 1;
877 break;
878 }
879 if (tsc_is_invariant)
880 printf("\n TSC: P-state invariant");
881
882 }
883 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
884 printf(" DIR=0x%04x", cyrix_did);
885 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
886 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
887 #ifndef CYRIX_CACHE_REALLY_WORKS
888 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
889 printf("\n CPU cache: write-through mode");
890 #endif
891 }
892
893 /* Avoid ugly blank lines: only print newline when we have to. */
894 if (*cpu_vendor || cpu_id)
895 printf("\n");
896
897 if (!bootverbose)
898 return;
899
900 if (cpu_vendor_id == CPU_VENDOR_AMD)
901 print_AMD_info();
902 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
903 print_INTEL_info();
904 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
905 print_transmeta_info();
906 }
907
908 void
909 panicifcpuunsupported(void)
910 {
911
912 #if !defined(lint)
913 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
914 #error This kernel is not configured for one of the supported CPUs
915 #endif
916 #else /* lint */
917 #endif /* lint */
918 /*
919 * Now that we have told the user what they have,
920 * let them know if that machine type isn't configured.
921 */
922 switch (cpu_class) {
923 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
924 case CPUCLASS_386:
925 #if !defined(I486_CPU)
926 case CPUCLASS_486:
927 #endif
928 #if !defined(I586_CPU)
929 case CPUCLASS_586:
930 #endif
931 #if !defined(I686_CPU)
932 case CPUCLASS_686:
933 #endif
934 panic("CPU class not configured");
935 default:
936 break;
937 }
938 }
939
940
941 static volatile u_int trap_by_rdmsr;
942
943 /*
944 * Special exception 6 handler.
945 * The rdmsr instruction generates invalid opcodes fault on 486-class
946 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
947 * function identblue() when this handler is called. Stacked eip should
948 * be advanced.
949 */
950 inthand_t bluetrap6;
951 #ifdef __GNUCLIKE_ASM
952 __asm
953 (" \n\
954 .text \n\
955 .p2align 2,0x90 \n\
956 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
957 " __XSTRING(CNAME(bluetrap6)) ": \n\
958 ss \n\
959 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
960 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
961 iret \n\
962 ");
963 #endif
964
965 /*
966 * Special exception 13 handler.
967 * Accessing non-existent MSR generates general protection fault.
968 */
969 inthand_t bluetrap13;
970 #ifdef __GNUCLIKE_ASM
971 __asm
972 (" \n\
973 .text \n\
974 .p2align 2,0x90 \n\
975 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
976 " __XSTRING(CNAME(bluetrap13)) ": \n\
977 ss \n\
978 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
979 popl %eax /* discard error code */ \n\
980 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
981 iret \n\
982 ");
983 #endif
984
985 /*
986 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
987 * support cpuid instruction. This function should be called after
988 * loading interrupt descriptor table register.
989 *
990 * I don't like this method that handles fault, but I couldn't get
991 * information for any other methods. Does blue giant know?
992 */
993 static int
994 identblue(void)
995 {
996
997 trap_by_rdmsr = 0;
998
999 /*
1000 * Cyrix 486-class CPU does not support rdmsr instruction.
1001 * The rdmsr instruction generates invalid opcode fault, and exception
1002 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1003 * bluetrap6() set the magic number to trap_by_rdmsr.
1004 */
1005 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1006 GSEL(GCODE_SEL, SEL_KPL));
1007
1008 /*
1009 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1010 * In this case, rdmsr generates general protection fault, and
1011 * exception will be trapped by bluetrap13().
1012 */
1013 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1014 GSEL(GCODE_SEL, SEL_KPL));
1015
1016 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1017
1018 if (trap_by_rdmsr == 0xa8c1d)
1019 return IDENTBLUE_CYRIX486;
1020 else if (trap_by_rdmsr == 0xa89c4)
1021 return IDENTBLUE_CYRIXM2;
1022 return IDENTBLUE_IBMCPU;
1023 }
1024
1025
1026 /*
1027 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1028 *
1029 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1030 * +-------+-------+---------------+
1031 * | SID | RID | Device ID |
1032 * | (DIR 1) | (DIR 0) |
1033 * +-------+-------+---------------+
1034 */
1035 static void
1036 identifycyrix(void)
1037 {
1038 register_t saveintr;
1039 int ccr2_test = 0, dir_test = 0;
1040 u_char ccr2, ccr3;
1041
1042 saveintr = intr_disable();
1043
1044 ccr2 = read_cyrix_reg(CCR2);
1045 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1046 read_cyrix_reg(CCR2);
1047 if (read_cyrix_reg(CCR2) != ccr2)
1048 ccr2_test = 1;
1049 write_cyrix_reg(CCR2, ccr2);
1050
1051 ccr3 = read_cyrix_reg(CCR3);
1052 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1053 read_cyrix_reg(CCR3);
1054 if (read_cyrix_reg(CCR3) != ccr3)
1055 dir_test = 1; /* CPU supports DIRs. */
1056 write_cyrix_reg(CCR3, ccr3);
1057
1058 if (dir_test) {
1059 /* Device ID registers are available. */
1060 cyrix_did = read_cyrix_reg(DIR1) << 8;
1061 cyrix_did += read_cyrix_reg(DIR0);
1062 } else if (ccr2_test)
1063 cyrix_did = 0x0010; /* 486S A-step */
1064 else
1065 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1066
1067 intr_restore(saveintr);
1068 }
1069
1070 /* Update TSC freq with the value indicated by the caller. */
1071 static void
1072 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
1073 {
1074 /*
1075 * If there was an error during the transition or
1076 * TSC is P-state invariant, don't do anything.
1077 */
1078 if (status != 0 || tsc_is_invariant)
1079 return;
1080
1081 /* Total setting for this level gives the new frequency in MHz. */
1082 hw_clockrate = level->total_set.freq;
1083 }
1084
1085 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
1086 EVENTHANDLER_PRI_ANY);
1087
1088 /*
1089 * Final stage of CPU identification. -- Should I check TI?
1090 */
1091 void
1092 finishidentcpu(void)
1093 {
1094 int isblue = 0;
1095 u_char ccr3;
1096 u_int regs[4];
1097
1098 cpu_vendor_id = find_cpu_vendor_id();
1099
1100 /*
1101 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1102 * function number again if it is set from BIOS. It is necessary
1103 * for probing correct CPU topology later.
1104 * XXX This is only done on the BSP package.
1105 */
1106 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1107 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1108 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1109 uint64_t msr;
1110 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1111 if ((msr & 0x400000ULL) != 0) {
1112 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1113 do_cpuid(0, regs);
1114 cpu_high = regs[0];
1115 }
1116 }
1117
1118 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1119 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1120 cpu_vendor_id == CPU_VENDOR_AMD) {
1121 init_exthigh();
1122 if (cpu_exthigh >= 0x80000001) {
1123 do_cpuid(0x80000001, regs);
1124 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1125 amd_feature2 = regs[2];
1126 }
1127 if (cpu_exthigh >= 0x80000007) {
1128 do_cpuid(0x80000007, regs);
1129 amd_pminfo = regs[3];
1130 }
1131 if (cpu_exthigh >= 0x80000008) {
1132 do_cpuid(0x80000008, regs);
1133 cpu_procinfo2 = regs[2];
1134 }
1135 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1136 if (cpu == CPU_486) {
1137 /*
1138 * These conditions are equivalent to:
1139 * - CPU does not support cpuid instruction.
1140 * - Cyrix/IBM CPU is detected.
1141 */
1142 isblue = identblue();
1143 if (isblue == IDENTBLUE_IBMCPU) {
1144 strcpy(cpu_vendor, "IBM");
1145 cpu_vendor_id = CPU_VENDOR_IBM;
1146 cpu = CPU_BLUE;
1147 return;
1148 }
1149 }
1150 switch (cpu_id & 0xf00) {
1151 case 0x600:
1152 /*
1153 * Cyrix's datasheet does not describe DIRs.
1154 * Therefor, I assume it does not have them
1155 * and use the result of the cpuid instruction.
1156 * XXX they seem to have it for now at least. -Peter
1157 */
1158 identifycyrix();
1159 cpu = CPU_M2;
1160 break;
1161 default:
1162 identifycyrix();
1163 /*
1164 * This routine contains a trick.
1165 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1166 */
1167 switch (cyrix_did & 0x00f0) {
1168 case 0x00:
1169 case 0xf0:
1170 cpu = CPU_486DLC;
1171 break;
1172 case 0x10:
1173 cpu = CPU_CY486DX;
1174 break;
1175 case 0x20:
1176 if ((cyrix_did & 0x000f) < 8)
1177 cpu = CPU_M1;
1178 else
1179 cpu = CPU_M1SC;
1180 break;
1181 case 0x30:
1182 cpu = CPU_M1;
1183 break;
1184 case 0x40:
1185 /* MediaGX CPU */
1186 cpu = CPU_M1SC;
1187 break;
1188 default:
1189 /* M2 and later CPUs are treated as M2. */
1190 cpu = CPU_M2;
1191
1192 /*
1193 * enable cpuid instruction.
1194 */
1195 ccr3 = read_cyrix_reg(CCR3);
1196 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1197 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1198 write_cyrix_reg(CCR3, ccr3);
1199
1200 do_cpuid(0, regs);
1201 cpu_high = regs[0]; /* eax */
1202 do_cpuid(1, regs);
1203 cpu_id = regs[0]; /* eax */
1204 cpu_feature = regs[3]; /* edx */
1205 break;
1206 }
1207 }
1208 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1209 /*
1210 * There are BlueLightning CPUs that do not change
1211 * undefined flags by dividing 5 by 2. In this case,
1212 * the CPU identification routine in locore.s leaves
1213 * cpu_vendor null string and puts CPU_486 into the
1214 * cpu.
1215 */
1216 isblue = identblue();
1217 if (isblue == IDENTBLUE_IBMCPU) {
1218 strcpy(cpu_vendor, "IBM");
1219 cpu_vendor_id = CPU_VENDOR_IBM;
1220 cpu = CPU_BLUE;
1221 return;
1222 }
1223 }
1224 }
1225
1226 static u_int
1227 find_cpu_vendor_id(void)
1228 {
1229 int i;
1230
1231 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1232 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1233 return (cpu_vendors[i].vendor_id);
1234 return (0);
1235 }
1236
1237 static void
1238 print_AMD_assoc(int i)
1239 {
1240 if (i == 255)
1241 printf(", fully associative\n");
1242 else
1243 printf(", %d-way associative\n", i);
1244 }
1245
1246 static void
1247 print_AMD_info(void)
1248 {
1249 quad_t amd_whcr;
1250
1251 if (cpu_exthigh >= 0x80000005) {
1252 u_int regs[4];
1253
1254 do_cpuid(0x80000005, regs);
1255 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1256 print_AMD_assoc(regs[1] >> 24);
1257 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1258 print_AMD_assoc((regs[1] >> 8) & 0xff);
1259 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1260 printf(", %d bytes/line", regs[2] & 0xff);
1261 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1262 print_AMD_assoc((regs[2] >> 16) & 0xff);
1263 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1264 printf(", %d bytes/line", regs[3] & 0xff);
1265 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1266 print_AMD_assoc((regs[3] >> 16) & 0xff);
1267 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1268 do_cpuid(0x80000006, regs);
1269 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1270 printf(", %d bytes/line", regs[2] & 0xff);
1271 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1272 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1273 }
1274 }
1275 if (((cpu_id & 0xf00) == 0x500)
1276 && (((cpu_id & 0x0f0) > 0x80)
1277 || (((cpu_id & 0x0f0) == 0x80)
1278 && (cpu_id & 0x00f) > 0x07))) {
1279 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1280 amd_whcr = rdmsr(0xc0000082);
1281 if (!(amd_whcr & (0x3ff << 22))) {
1282 printf("Write Allocate Disable\n");
1283 } else {
1284 printf("Write Allocate Enable Limit: %dM bytes\n",
1285 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1286 printf("Write Allocate 15-16M bytes: %s\n",
1287 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1288 }
1289 } else if (((cpu_id & 0xf00) == 0x500)
1290 && ((cpu_id & 0x0f0) > 0x50)) {
1291 /* K6, K6-2(old core) */
1292 amd_whcr = rdmsr(0xc0000082);
1293 if (!(amd_whcr & (0x7f << 1))) {
1294 printf("Write Allocate Disable\n");
1295 } else {
1296 printf("Write Allocate Enable Limit: %dM bytes\n",
1297 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1298 printf("Write Allocate 15-16M bytes: %s\n",
1299 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1300 printf("Hardware Write Allocate Control: %s\n",
1301 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1302 }
1303 }
1304
1305 /*
1306 * Opteron Rev E shows a bug as in very rare occasions a read memory
1307 * barrier is not performed as expected if it is followed by a
1308 * non-atomic read-modify-write instruction.
1309 * As long as that bug pops up very rarely (intensive machine usage
1310 * on other operating systems generally generates one unexplainable
1311 * crash any 2 months) and as long as a model specific fix would be
1312 * impratical at this stage, print out a warning string if the broken
1313 * model and family are identified.
1314 */
1315 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1316 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1317 printf("WARNING: This architecture revision has known SMP "
1318 "hardware bugs which may cause random instability\n");
1319 }
1320
1321 static void
1322 print_INTEL_info(void)
1323 {
1324 u_int regs[4];
1325 u_int rounds, regnum;
1326 u_int nwaycode, nway;
1327
1328 if (cpu_high >= 2) {
1329 rounds = 0;
1330 do {
1331 do_cpuid(0x2, regs);
1332 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1333 break; /* we have a buggy CPU */
1334
1335 for (regnum = 0; regnum <= 3; ++regnum) {
1336 if (regs[regnum] & (1<<31))
1337 continue;
1338 if (regnum != 0)
1339 print_INTEL_TLB(regs[regnum] & 0xff);
1340 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1341 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1342 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1343 }
1344 } while (--rounds > 0);
1345 }
1346
1347 if (cpu_exthigh >= 0x80000006) {
1348 do_cpuid(0x80000006, regs);
1349 nwaycode = (regs[2] >> 12) & 0x0f;
1350 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1351 nway = 1 << (nwaycode / 2);
1352 else
1353 nway = 0;
1354 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1355 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1356 }
1357
1358 printf("\n");
1359 }
1360
1361 static void
1362 print_INTEL_TLB(u_int data)
1363 {
1364 switch (data) {
1365 case 0x0:
1366 case 0x40:
1367 default:
1368 break;
1369 case 0x1:
1370 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1371 break;
1372 case 0x2:
1373 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1374 break;
1375 case 0x3:
1376 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1377 break;
1378 case 0x4:
1379 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1380 break;
1381 case 0x6:
1382 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1383 break;
1384 case 0x8:
1385 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1386 break;
1387 case 0xa:
1388 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1389 break;
1390 case 0xc:
1391 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1392 break;
1393 case 0x22:
1394 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1395 break;
1396 case 0x23:
1397 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1398 break;
1399 case 0x25:
1400 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1401 break;
1402 case 0x29:
1403 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1404 break;
1405 case 0x2c:
1406 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1407 break;
1408 case 0x30:
1409 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1410 break;
1411 case 0x39:
1412 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1413 break;
1414 case 0x3b:
1415 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1416 break;
1417 case 0x3c:
1418 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1419 break;
1420 case 0x41:
1421 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1422 break;
1423 case 0x42:
1424 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1425 break;
1426 case 0x43:
1427 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1428 break;
1429 case 0x44:
1430 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1431 break;
1432 case 0x45:
1433 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1434 break;
1435 case 0x46:
1436 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1437 break;
1438 case 0x47:
1439 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1440 break;
1441 case 0x50:
1442 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1443 break;
1444 case 0x51:
1445 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1446 break;
1447 case 0x52:
1448 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1449 break;
1450 case 0x5b:
1451 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1452 break;
1453 case 0x5c:
1454 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1455 break;
1456 case 0x5d:
1457 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1458 break;
1459 case 0x60:
1460 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1461 break;
1462 case 0x66:
1463 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1464 break;
1465 case 0x67:
1466 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1467 break;
1468 case 0x68:
1469 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1470 break;
1471 case 0x70:
1472 printf("\nTrace cache: 12K-uops, 8-way set associative");
1473 break;
1474 case 0x71:
1475 printf("\nTrace cache: 16K-uops, 8-way set associative");
1476 break;
1477 case 0x72:
1478 printf("\nTrace cache: 32K-uops, 8-way set associative");
1479 break;
1480 case 0x78:
1481 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1482 break;
1483 case 0x79:
1484 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1485 break;
1486 case 0x7a:
1487 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1488 break;
1489 case 0x7b:
1490 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1491 break;
1492 case 0x7c:
1493 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1494 break;
1495 case 0x7d:
1496 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1497 break;
1498 case 0x7f:
1499 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1500 break;
1501 case 0x82:
1502 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1503 break;
1504 case 0x83:
1505 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1506 break;
1507 case 0x84:
1508 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1509 break;
1510 case 0x85:
1511 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1512 break;
1513 case 0x86:
1514 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1515 break;
1516 case 0x87:
1517 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1518 break;
1519 case 0xb0:
1520 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1521 break;
1522 case 0xb3:
1523 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1524 break;
1525 }
1526 }
1527
1528 static void
1529 print_transmeta_info(void)
1530 {
1531 u_int regs[4], nreg = 0;
1532
1533 do_cpuid(0x80860000, regs);
1534 nreg = regs[0];
1535 if (nreg >= 0x80860001) {
1536 do_cpuid(0x80860001, regs);
1537 printf(" Processor revision %u.%u.%u.%u\n",
1538 (regs[1] >> 24) & 0xff,
1539 (regs[1] >> 16) & 0xff,
1540 (regs[1] >> 8) & 0xff,
1541 regs[1] & 0xff);
1542 }
1543 if (nreg >= 0x80860002) {
1544 do_cpuid(0x80860002, regs);
1545 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1546 (regs[1] >> 24) & 0xff,
1547 (regs[1] >> 16) & 0xff,
1548 (regs[1] >> 8) & 0xff,
1549 regs[1] & 0xff,
1550 regs[2]);
1551 }
1552 if (nreg >= 0x80860006) {
1553 char info[65];
1554 do_cpuid(0x80860003, (u_int*) &info[0]);
1555 do_cpuid(0x80860004, (u_int*) &info[16]);
1556 do_cpuid(0x80860005, (u_int*) &info[32]);
1557 do_cpuid(0x80860006, (u_int*) &info[48]);
1558 info[64] = 0;
1559 printf(" %s\n", info);
1560 }
1561 }
1562
1563 static void
1564 print_via_padlock_info(void)
1565 {
1566 u_int regs[4];
1567
1568 /* Check for supported models. */
1569 switch (cpu_id & 0xff0) {
1570 case 0x690:
1571 if ((cpu_id & 0xf) < 3)
1572 return;
1573 case 0x6a0:
1574 case 0x6d0:
1575 case 0x6f0:
1576 break;
1577 default:
1578 return;
1579 }
1580
1581 do_cpuid(0xc0000000, regs);
1582 if (regs[0] >= 0xc0000001)
1583 do_cpuid(0xc0000001, regs);
1584 else
1585 return;
1586
1587 printf("\n VIA Padlock Features=0x%b", regs[3],
1588 "\020"
1589 "\003RNG" /* RNG */
1590 "\007AES" /* ACE */
1591 "\011AES-CTR" /* ACE2 */
1592 "\013SHA1,SHA256" /* PHE */
1593 "\015RSA" /* PMM */
1594 );
1595 }
Cache object: a78dfbcfa7b197e11fcdd9bbb18703b6
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