The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/identcpu.c

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    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: stable/9/sys/i386/i386/identcpu.c 258161 2013-11-15 07:26:50Z kib $");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/cpu.h>
   49 #include <sys/eventhandler.h>
   50 #include <sys/systm.h>
   51 #include <sys/kernel.h>
   52 #include <sys/sysctl.h>
   53 #include <sys/power.h>
   54 
   55 #include <machine/asmacros.h>
   56 #include <machine/clock.h>
   57 #include <machine/cputypes.h>
   58 #include <machine/intr_machdep.h>
   59 #include <machine/md_var.h>
   60 #include <machine/segments.h>
   61 #include <machine/specialreg.h>
   62 
   63 #define IDENTBLUE_CYRIX486      0
   64 #define IDENTBLUE_IBMCPU        1
   65 #define IDENTBLUE_CYRIXM2       2
   66 
   67 /* XXX - should be in header file: */
   68 void printcpuinfo(void);
   69 void finishidentcpu(void);
   70 void earlysetcpuclass(void);
   71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   72 void    enable_K5_wt_alloc(void);
   73 void    enable_K6_wt_alloc(void);
   74 void    enable_K6_2_wt_alloc(void);
   75 #endif
   76 void panicifcpuunsupported(void);
   77 
   78 static void identifycyrix(void);
   79 static void init_exthigh(void);
   80 static u_int find_cpu_vendor_id(void);
   81 static void print_AMD_info(void);
   82 static void print_INTEL_info(void);
   83 static void print_INTEL_TLB(u_int data);
   84 static void print_AMD_assoc(int i);
   85 static void print_transmeta_info(void);
   86 static void print_via_padlock_info(void);
   87 
   88 int     cpu_class;
   89 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   90 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
   91 char machine[] = MACHINE;
   92 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   93     machine, 0, "Machine class");
   94 
   95 static char cpu_model[128];
   96 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   97     cpu_model, 0, "Machine model");
   98 
   99 static int hw_clockrate;
  100 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
  101     &hw_clockrate, 0, "CPU instruction clock rate");
  102 
  103 static eventhandler_tag tsc_post_tag;
  104 
  105 static char cpu_brand[48];
  106 
  107 #define MAX_BRAND_INDEX 8
  108 
  109 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
  110         NULL,                   /* No brand */
  111         "Intel Celeron",
  112         "Intel Pentium III",
  113         "Intel Pentium III Xeon",
  114         NULL,
  115         NULL,
  116         NULL,
  117         NULL,
  118         "Intel Pentium 4"
  119 };
  120 
  121 static struct {
  122         char    *cpu_name;
  123         int     cpu_class;
  124 } i386_cpus[] = {
  125         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
  126         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
  127         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
  128         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
  129         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
  130         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
  131         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
  132         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
  133         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
  134         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
  135         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
  136         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
  137         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
  138         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
  139         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
  140         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
  141         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
  142 };
  143 
  144 static struct {
  145         char    *vendor;
  146         u_int   vendor_id;
  147 } cpu_vendors[] = {
  148         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
  149         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
  150         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
  151         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
  152         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
  153         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
  154         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
  155         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
  156         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
  157         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
  158 #if 0
  159         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
  160         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
  161 #endif
  162 };
  163 
  164 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  165 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
  166 #endif
  167 
  168 static void
  169 init_exthigh(void)
  170 {
  171         static int done = 0;
  172         u_int regs[4];
  173 
  174         if (done == 0) {
  175                 if (cpu_high > 0 &&
  176                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
  177                     cpu_vendor_id == CPU_VENDOR_AMD ||
  178                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
  179                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
  180                     cpu_vendor_id == CPU_VENDOR_NSC)) {
  181                         do_cpuid(0x80000000, regs);
  182                         if (regs[0] >= 0x80000000)
  183                                 cpu_exthigh = regs[0];
  184                 }
  185 
  186                 done = 1;
  187         }
  188 }
  189 
  190 void
  191 printcpuinfo(void)
  192 {
  193         u_int regs[4], i;
  194         char *brand;
  195 
  196         cpu_class = i386_cpus[cpu].cpu_class;
  197         printf("CPU: ");
  198         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
  199 
  200         /* Check for extended CPUID information and a processor name. */
  201         init_exthigh();
  202         if (cpu_exthigh >= 0x80000004) {
  203                 brand = cpu_brand;
  204                 for (i = 0x80000002; i < 0x80000005; i++) {
  205                         do_cpuid(i, regs);
  206                         memcpy(brand, regs, sizeof(regs));
  207                         brand += sizeof(regs);
  208                 }
  209         }
  210 
  211         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  212                 if ((cpu_id & 0xf00) > 0x300) {
  213                         u_int brand_index;
  214 
  215                         cpu_model[0] = '\0';
  216 
  217                         switch (cpu_id & 0x3000) {
  218                         case 0x1000:
  219                                 strcpy(cpu_model, "Overdrive ");
  220                                 break;
  221                         case 0x2000:
  222                                 strcpy(cpu_model, "Dual ");
  223                                 break;
  224                         }
  225 
  226                         switch (cpu_id & 0xf00) {
  227                         case 0x400:
  228                                 strcat(cpu_model, "i486 ");
  229                                 /* Check the particular flavor of 486 */
  230                                 switch (cpu_id & 0xf0) {
  231                                 case 0x00:
  232                                 case 0x10:
  233                                         strcat(cpu_model, "DX");
  234                                         break;
  235                                 case 0x20:
  236                                         strcat(cpu_model, "SX");
  237                                         break;
  238                                 case 0x30:
  239                                         strcat(cpu_model, "DX2");
  240                                         break;
  241                                 case 0x40:
  242                                         strcat(cpu_model, "SL");
  243                                         break;
  244                                 case 0x50:
  245                                         strcat(cpu_model, "SX2");
  246                                         break;
  247                                 case 0x70:
  248                                         strcat(cpu_model,
  249                                             "DX2 Write-Back Enhanced");
  250                                         break;
  251                                 case 0x80:
  252                                         strcat(cpu_model, "DX4");
  253                                         break;
  254                                 }
  255                                 break;
  256                         case 0x500:
  257                                 /* Check the particular flavor of 586 */
  258                                 strcat(cpu_model, "Pentium");
  259                                 switch (cpu_id & 0xf0) {
  260                                 case 0x00:
  261                                         strcat(cpu_model, " A-step");
  262                                         break;
  263                                 case 0x10:
  264                                         strcat(cpu_model, "/P5");
  265                                         break;
  266                                 case 0x20:
  267                                         strcat(cpu_model, "/P54C");
  268                                         break;
  269                                 case 0x30:
  270                                         strcat(cpu_model, "/P24T");
  271                                         break;
  272                                 case 0x40:
  273                                         strcat(cpu_model, "/P55C");
  274                                         break;
  275                                 case 0x70:
  276                                         strcat(cpu_model, "/P54C");
  277                                         break;
  278                                 case 0x80:
  279                                         strcat(cpu_model, "/P55C (quarter-micron)");
  280                                         break;
  281                                 default:
  282                                         /* nothing */
  283                                         break;
  284                                 }
  285 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  286                                 /*
  287                                  * XXX - If/when Intel fixes the bug, this
  288                                  * should also check the version of the
  289                                  * CPU, not just that it's a Pentium.
  290                                  */
  291                                 has_f00f_bug = 1;
  292 #endif
  293                                 break;
  294                         case 0x600:
  295                                 /* Check the particular flavor of 686 */
  296                                 switch (cpu_id & 0xf0) {
  297                                 case 0x00:
  298                                         strcat(cpu_model, "Pentium Pro A-step");
  299                                         break;
  300                                 case 0x10:
  301                                         strcat(cpu_model, "Pentium Pro");
  302                                         break;
  303                                 case 0x30:
  304                                 case 0x50:
  305                                 case 0x60:
  306                                         strcat(cpu_model,
  307                                 "Pentium II/Pentium II Xeon/Celeron");
  308                                         cpu = CPU_PII;
  309                                         break;
  310                                 case 0x70:
  311                                 case 0x80:
  312                                 case 0xa0:
  313                                 case 0xb0:
  314                                         strcat(cpu_model,
  315                                         "Pentium III/Pentium III Xeon/Celeron");
  316                                         cpu = CPU_PIII;
  317                                         break;
  318                                 default:
  319                                         strcat(cpu_model, "Unknown 80686");
  320                                         break;
  321                                 }
  322                                 break;
  323                         case 0xf00:
  324                                 strcat(cpu_model, "Pentium 4");
  325                                 cpu = CPU_P4;
  326                                 break;
  327                         default:
  328                                 strcat(cpu_model, "unknown");
  329                                 break;
  330                         }
  331 
  332                         /*
  333                          * If we didn't get a brand name from the extended
  334                          * CPUID, try to look it up in the brand table.
  335                          */
  336                         if (cpu_high > 0 && *cpu_brand == '\0') {
  337                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
  338                                 if (brand_index <= MAX_BRAND_INDEX &&
  339                                     cpu_brandtable[brand_index] != NULL)
  340                                         strcpy(cpu_brand,
  341                                             cpu_brandtable[brand_index]);
  342                         }
  343                 }
  344         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
  345                 /*
  346                  * Values taken from AMD Processor Recognition
  347                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  348                  * (also describes ``Features'' encodings.
  349                  */
  350                 strcpy(cpu_model, "AMD ");
  351                 switch (cpu_id & 0xFF0) {
  352                 case 0x410:
  353                         strcat(cpu_model, "Standard Am486DX");
  354                         break;
  355                 case 0x430:
  356                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
  357                         break;
  358                 case 0x470:
  359                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
  360                         break;
  361                 case 0x480:
  362                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
  363                         break;
  364                 case 0x490:
  365                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
  366                         break;
  367                 case 0x4E0:
  368                         strcat(cpu_model, "Am5x86 Write-Through");
  369                         break;
  370                 case 0x4F0:
  371                         strcat(cpu_model, "Am5x86 Write-Back");
  372                         break;
  373                 case 0x500:
  374                         strcat(cpu_model, "K5 model 0");
  375                         tsc_freq = 0;
  376                         break;
  377                 case 0x510:
  378                         strcat(cpu_model, "K5 model 1");
  379                         break;
  380                 case 0x520:
  381                         strcat(cpu_model, "K5 PR166 (model 2)");
  382                         break;
  383                 case 0x530:
  384                         strcat(cpu_model, "K5 PR200 (model 3)");
  385                         break;
  386                 case 0x560:
  387                         strcat(cpu_model, "K6");
  388                         break;
  389                 case 0x570:
  390                         strcat(cpu_model, "K6 266 (model 1)");
  391                         break;
  392                 case 0x580:
  393                         strcat(cpu_model, "K6-2");
  394                         break;
  395                 case 0x590:
  396                         strcat(cpu_model, "K6-III");
  397                         break;
  398                 case 0x5a0:
  399                         strcat(cpu_model, "Geode LX");
  400                         /*
  401                          * Make sure the TSC runs through suspension,
  402                          * otherwise we can't use it as timecounter
  403                          */
  404                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
  405                         break;
  406                 default:
  407                         strcat(cpu_model, "Unknown");
  408                         break;
  409                 }
  410 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  411                 if ((cpu_id & 0xf00) == 0x500) {
  412                         if (((cpu_id & 0x0f0) > 0)
  413                             && ((cpu_id & 0x0f0) < 0x60)
  414                             && ((cpu_id & 0x00f) > 3))
  415                                 enable_K5_wt_alloc();
  416                         else if (((cpu_id & 0x0f0) > 0x80)
  417                                  || (((cpu_id & 0x0f0) == 0x80)
  418                                      && (cpu_id & 0x00f) > 0x07))
  419                                 enable_K6_2_wt_alloc();
  420                         else if ((cpu_id & 0x0f0) > 0x50)
  421                                 enable_K6_wt_alloc();
  422                 }
  423 #endif
  424         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
  425                 strcpy(cpu_model, "Cyrix ");
  426                 switch (cpu_id & 0xff0) {
  427                 case 0x440:
  428                         strcat(cpu_model, "MediaGX");
  429                         break;
  430                 case 0x520:
  431                         strcat(cpu_model, "6x86");
  432                         break;
  433                 case 0x540:
  434                         cpu_class = CPUCLASS_586;
  435                         strcat(cpu_model, "GXm");
  436                         break;
  437                 case 0x600:
  438                         strcat(cpu_model, "6x86MX");
  439                         break;
  440                 default:
  441                         /*
  442                          * Even though CPU supports the cpuid
  443                          * instruction, it can be disabled.
  444                          * Therefore, this routine supports all Cyrix
  445                          * CPUs.
  446                          */
  447                         switch (cyrix_did & 0xf0) {
  448                         case 0x00:
  449                                 switch (cyrix_did & 0x0f) {
  450                                 case 0x00:
  451                                         strcat(cpu_model, "486SLC");
  452                                         break;
  453                                 case 0x01:
  454                                         strcat(cpu_model, "486DLC");
  455                                         break;
  456                                 case 0x02:
  457                                         strcat(cpu_model, "486SLC2");
  458                                         break;
  459                                 case 0x03:
  460                                         strcat(cpu_model, "486DLC2");
  461                                         break;
  462                                 case 0x04:
  463                                         strcat(cpu_model, "486SRx");
  464                                         break;
  465                                 case 0x05:
  466                                         strcat(cpu_model, "486DRx");
  467                                         break;
  468                                 case 0x06:
  469                                         strcat(cpu_model, "486SRx2");
  470                                         break;
  471                                 case 0x07:
  472                                         strcat(cpu_model, "486DRx2");
  473                                         break;
  474                                 case 0x08:
  475                                         strcat(cpu_model, "486SRu");
  476                                         break;
  477                                 case 0x09:
  478                                         strcat(cpu_model, "486DRu");
  479                                         break;
  480                                 case 0x0a:
  481                                         strcat(cpu_model, "486SRu2");
  482                                         break;
  483                                 case 0x0b:
  484                                         strcat(cpu_model, "486DRu2");
  485                                         break;
  486                                 default:
  487                                         strcat(cpu_model, "Unknown");
  488                                         break;
  489                                 }
  490                                 break;
  491                         case 0x10:
  492                                 switch (cyrix_did & 0x0f) {
  493                                 case 0x00:
  494                                         strcat(cpu_model, "486S");
  495                                         break;
  496                                 case 0x01:
  497                                         strcat(cpu_model, "486S2");
  498                                         break;
  499                                 case 0x02:
  500                                         strcat(cpu_model, "486Se");
  501                                         break;
  502                                 case 0x03:
  503                                         strcat(cpu_model, "486S2e");
  504                                         break;
  505                                 case 0x0a:
  506                                         strcat(cpu_model, "486DX");
  507                                         break;
  508                                 case 0x0b:
  509                                         strcat(cpu_model, "486DX2");
  510                                         break;
  511                                 case 0x0f:
  512                                         strcat(cpu_model, "486DX4");
  513                                         break;
  514                                 default:
  515                                         strcat(cpu_model, "Unknown");
  516                                         break;
  517                                 }
  518                                 break;
  519                         case 0x20:
  520                                 if ((cyrix_did & 0x0f) < 8)
  521                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
  522                                 else
  523                                         strcat(cpu_model, "5x86");
  524                                 break;
  525                         case 0x30:
  526                                 strcat(cpu_model, "6x86");
  527                                 break;
  528                         case 0x40:
  529                                 if ((cyrix_did & 0xf000) == 0x3000) {
  530                                         cpu_class = CPUCLASS_586;
  531                                         strcat(cpu_model, "GXm");
  532                                 } else
  533                                         strcat(cpu_model, "MediaGX");
  534                                 break;
  535                         case 0x50:
  536                                 strcat(cpu_model, "6x86MX");
  537                                 break;
  538                         case 0xf0:
  539                                 switch (cyrix_did & 0x0f) {
  540                                 case 0x0d:
  541                                         strcat(cpu_model, "Overdrive CPU");
  542                                         break;
  543                                 case 0x0e:
  544                                         strcpy(cpu_model, "Texas Instruments 486SXL");
  545                                         break;
  546                                 case 0x0f:
  547                                         strcat(cpu_model, "486SLC/DLC");
  548                                         break;
  549                                 default:
  550                                         strcat(cpu_model, "Unknown");
  551                                         break;
  552                                 }
  553                                 break;
  554                         default:
  555                                 strcat(cpu_model, "Unknown");
  556                                 break;
  557                         }
  558                         break;
  559                 }
  560         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
  561                 strcpy(cpu_model, "Rise ");
  562                 switch (cpu_id & 0xff0) {
  563                 case 0x500:     /* 6401 and 6441 (Kirin) */
  564                 case 0x520:     /* 6510 (Lynx) */
  565                         strcat(cpu_model, "mP6");
  566                         break;
  567                 default:
  568                         strcat(cpu_model, "Unknown");
  569                 }
  570         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
  571                 switch (cpu_id & 0xff0) {
  572                 case 0x540:
  573                         strcpy(cpu_model, "IDT WinChip C6");
  574                         /*
  575                          * http://www.centtech.com/c6_data_sheet.pdf
  576                          *
  577                          * I-12 RDTSC may return incoherent values in EDX:EAX
  578                          * I-13 RDTSC hangs when certain event counters are used
  579                          */
  580                         tsc_freq = 0;
  581                         break;
  582                 case 0x580:
  583                         strcpy(cpu_model, "IDT WinChip 2");
  584                         break;
  585                 case 0x590:
  586                         strcpy(cpu_model, "IDT WinChip 3");
  587                         break;
  588                 case 0x660:
  589                         strcpy(cpu_model, "VIA C3 Samuel");
  590                         break;
  591                 case 0x670:
  592                         if (cpu_id & 0x8)
  593                                 strcpy(cpu_model, "VIA C3 Ezra");
  594                         else
  595                                 strcpy(cpu_model, "VIA C3 Samuel 2");
  596                         break;
  597                 case 0x680:
  598                         strcpy(cpu_model, "VIA C3 Ezra-T");
  599                         break;
  600                 case 0x690:
  601                         strcpy(cpu_model, "VIA C3 Nehemiah");
  602                         break;
  603                 case 0x6a0:
  604                 case 0x6d0:
  605                         strcpy(cpu_model, "VIA C7 Esther");
  606                         break;
  607                 case 0x6f0:
  608                         strcpy(cpu_model, "VIA Nano");
  609                         break;
  610                 default:
  611                         strcpy(cpu_model, "VIA/IDT Unknown");
  612                 }
  613         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
  614                 strcpy(cpu_model, "Blue Lightning CPU");
  615         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
  616                 switch (cpu_id & 0xff0) {
  617                 case 0x540:
  618                         strcpy(cpu_model, "Geode SC1100");
  619                         cpu = CPU_GEODE1100;
  620                         if ((cpu_id & CPUID_STEPPING) == 0)
  621                                 tsc_freq = 0;
  622                         break;
  623                 default:
  624                         strcpy(cpu_model, "Geode/NSC unknown");
  625                         break;
  626                 }
  627         }
  628 
  629         /*
  630          * Replace cpu_model with cpu_brand minus leading spaces if
  631          * we have one.
  632          */
  633         brand = cpu_brand;
  634         while (*brand == ' ')
  635                 ++brand;
  636         if (*brand != '\0')
  637                 strcpy(cpu_model, brand);
  638 
  639         printf("%s (", cpu_model);
  640         switch(cpu_class) {
  641         case CPUCLASS_286:
  642                 printf("286");
  643                 break;
  644         case CPUCLASS_386:
  645                 printf("386");
  646                 break;
  647 #if defined(I486_CPU)
  648         case CPUCLASS_486:
  649                 printf("486");
  650                 break;
  651 #endif
  652 #if defined(I586_CPU)
  653         case CPUCLASS_586:
  654                 if (tsc_freq != 0) {
  655                         hw_clockrate = (tsc_freq + 5000) / 1000000;
  656                         printf("%jd.%02d-MHz ",
  657                                (intmax_t)(tsc_freq + 4999) / 1000000,
  658                                (u_int)((tsc_freq + 4999) / 10000) % 100);
  659                 }
  660                 printf("586");
  661                 break;
  662 #endif
  663 #if defined(I686_CPU)
  664         case CPUCLASS_686:
  665                 if (tsc_freq != 0) {
  666                         hw_clockrate = (tsc_freq + 5000) / 1000000;
  667                         printf("%jd.%02d-MHz ",
  668                                (intmax_t)(tsc_freq + 4999) / 1000000,
  669                                (u_int)((tsc_freq + 4999) / 10000) % 100);
  670                 }
  671                 printf("686");
  672                 break;
  673 #endif
  674         default:
  675                 printf("Unknown");      /* will panic below... */
  676         }
  677         printf("-class CPU)\n");
  678         if(*cpu_vendor)
  679                 printf("  Origin = \"%s\"",cpu_vendor);
  680         if(cpu_id)
  681                 printf("  Id = 0x%x", cpu_id);
  682 
  683         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
  684             cpu_vendor_id == CPU_VENDOR_AMD ||
  685             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
  686             cpu_vendor_id == CPU_VENDOR_RISE ||
  687             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
  688             cpu_vendor_id == CPU_VENDOR_NSC ||
  689                 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
  690                  ((cpu_id & 0xf00) > 0x500))) {
  691                 printf("  Family = 0x%x", CPUID_TO_FAMILY(cpu_id));
  692                 printf("  Model = 0x%x", CPUID_TO_MODEL(cpu_id));
  693                 printf("  Stepping = %u", cpu_id & CPUID_STEPPING);
  694                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
  695                         printf("\n  DIR=0x%04x", cyrix_did);
  696                 /*
  697                  * AMD CPUID Specification
  698                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
  699                  *
  700                  * Intel Processor Identification and CPUID Instruction
  701                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
  702                  */
  703                 if (cpu_high > 0) {
  704 
  705                         /*
  706                          * Here we should probably set up flags indicating
  707                          * whether or not various features are available.
  708                          * The interesting ones are probably VME, PSE, PAE,
  709                          * and PGE.  The code already assumes without bothering
  710                          * to check that all CPUs >= Pentium have a TSC and
  711                          * MSRs.
  712                          */
  713                         printf("\n  Features=0x%b", cpu_feature,
  714                         "\020"
  715                         "\001FPU"       /* Integral FPU */
  716                         "\002VME"       /* Extended VM86 mode support */
  717                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  718                         "\004PSE"       /* 4MByte page tables */
  719                         "\005TSC"       /* Timestamp counter */
  720                         "\006MSR"       /* Machine specific registers */
  721                         "\007PAE"       /* Physical address extension */
  722                         "\010MCE"       /* Machine Check support */
  723                         "\011CX8"       /* CMPEXCH8 instruction */
  724                         "\012APIC"      /* SMP local APIC */
  725                         "\013oldMTRR"   /* Previous implementation of MTRR */
  726                         "\014SEP"       /* Fast System Call */
  727                         "\015MTRR"      /* Memory Type Range Registers */
  728                         "\016PGE"       /* PG_G (global bit) support */
  729                         "\017MCA"       /* Machine Check Architecture */
  730                         "\020CMOV"      /* CMOV instruction */
  731                         "\021PAT"       /* Page attributes table */
  732                         "\022PSE36"     /* 36 bit address space support */
  733                         "\023PN"        /* Processor Serial number */
  734                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  735                         "\025<b20>"
  736                         "\026DTS"       /* Debug Trace Store */
  737                         "\027ACPI"      /* ACPI support */
  738                         "\030MMX"       /* MMX instructions */
  739                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  740                         "\032SSE"       /* Streaming SIMD Extensions */
  741                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  742                         "\034SS"        /* Self snoop */
  743                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  744                         "\036TM"        /* Thermal Monitor clock slowdown */
  745                         "\037IA64"      /* CPU can execute IA64 instructions */
  746                         "\040PBE"       /* Pending Break Enable */
  747                         );
  748 
  749                         if (cpu_feature2 != 0) {
  750                                 printf("\n  Features2=0x%b", cpu_feature2,
  751                                 "\020"
  752                                 "\001SSE3"      /* SSE3 */
  753                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
  754                                 "\003DTES64"    /* 64-bit Debug Trace */
  755                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  756                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  757                                 "\006VMX"       /* Virtual Machine Extensions */
  758                                 "\007SMX"       /* Safer Mode Extensions */
  759                                 "\010EST"       /* Enhanced SpeedStep */
  760                                 "\011TM2"       /* Thermal Monitor 2 */
  761                                 "\012SSSE3"     /* SSSE3 */
  762                                 "\013CNXT-ID"   /* L1 context ID available */
  763                                 "\014<b11>"
  764                                 "\015FMA"       /* Fused Multiply Add */
  765                                 "\016CX16"      /* CMPXCHG16B Instruction */
  766                                 "\017xTPR"      /* Send Task Priority Messages*/
  767                                 "\020PDCM"      /* Perf/Debug Capability MSR */
  768                                 "\021<b16>"
  769                                 "\022PCID"      /* Process-context Identifiers*/
  770                                 "\023DCA"       /* Direct Cache Access */
  771                                 "\024SSE4.1"    /* SSE 4.1 */
  772                                 "\025SSE4.2"    /* SSE 4.2 */
  773                                 "\026x2APIC"    /* xAPIC Extensions */
  774                                 "\027MOVBE"     /* MOVBE Instruction */
  775                                 "\030POPCNT"    /* POPCNT Instruction */
  776                                 "\031TSCDLT"    /* TSC-Deadline Timer */
  777                                 "\032AESNI"     /* AES Crypto */
  778                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
  779                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
  780                                 "\035AVX"       /* Advanced Vector Extensions */
  781                                 "\036F16C"      /* Half-precision conversions */
  782                                 "\037RDRAND"    /* RDRAND Instruction */
  783                                 "\040HV"        /* Hypervisor */
  784                                 );
  785                         }
  786 
  787                         if (amd_feature != 0) {
  788                                 printf("\n  AMD Features=0x%b", amd_feature,
  789                                 "\020"          /* in hex */
  790                                 "\001<s0>"      /* Same */
  791                                 "\002<s1>"      /* Same */
  792                                 "\003<s2>"      /* Same */
  793                                 "\004<s3>"      /* Same */
  794                                 "\005<s4>"      /* Same */
  795                                 "\006<s5>"      /* Same */
  796                                 "\007<s6>"      /* Same */
  797                                 "\010<s7>"      /* Same */
  798                                 "\011<s8>"      /* Same */
  799                                 "\012<s9>"      /* Same */
  800                                 "\013<b10>"     /* Undefined */
  801                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  802                                 "\015<s12>"     /* Same */
  803                                 "\016<s13>"     /* Same */
  804                                 "\017<s14>"     /* Same */
  805                                 "\020<s15>"     /* Same */
  806                                 "\021<s16>"     /* Same */
  807                                 "\022<s17>"     /* Same */
  808                                 "\023<b18>"     /* Reserved, unknown */
  809                                 "\024MP"        /* Multiprocessor Capable */
  810                                 "\025NX"        /* Has EFER.NXE, NX */
  811                                 "\026<b21>"     /* Undefined */
  812                                 "\027MMX+"      /* AMD MMX Extensions */
  813                                 "\030<s23>"     /* Same */
  814                                 "\031<s24>"     /* Same */
  815                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
  816                                 "\033Page1GB"   /* 1-GB large page support */
  817                                 "\034RDTSCP"    /* RDTSCP */
  818                                 "\035<b28>"     /* Undefined */
  819                                 "\036LM"        /* 64 bit long mode */
  820                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
  821                                 "\0403DNow!"    /* AMD 3DNow! */
  822                                 );
  823                         }
  824 
  825                         if (amd_feature2 != 0) {
  826                                 printf("\n  AMD Features2=0x%b", amd_feature2,
  827                                 "\020"
  828                                 "\001LAHF"      /* LAHF/SAHF in long mode */
  829                                 "\002CMP"       /* CMP legacy */
  830                                 "\003SVM"       /* Secure Virtual Mode */
  831                                 "\004ExtAPIC"   /* Extended APIC register */
  832                                 "\005CR8"       /* CR8 in legacy mode */
  833                                 "\006ABM"       /* LZCNT instruction */
  834                                 "\007SSE4A"     /* SSE4A */
  835                                 "\010MAS"       /* Misaligned SSE mode */
  836                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
  837                                 "\012OSVW"      /* OS visible workaround */
  838                                 "\013IBS"       /* Instruction based sampling */
  839                                 "\014XOP"       /* XOP extended instructions */
  840                                 "\015SKINIT"    /* SKINIT/STGI */
  841                                 "\016WDT"       /* Watchdog timer */
  842                                 "\017<b14>"
  843                                 "\020LWP"       /* Lightweight Profiling */
  844                                 "\021FMA4"      /* 4-operand FMA instructions */
  845                                 "\022TCE"       /* Translation Cache Extension */
  846                                 "\023<b18>"
  847                                 "\024NodeId"    /* NodeId MSR support */
  848                                 "\025<b20>"
  849                                 "\026TBM"       /* Trailing Bit Manipulation */
  850                                 "\027Topology"  /* Topology Extensions */
  851                                 "\030PCXC"      /* Core perf count */
  852                                 "\031PNXC"      /* NB perf count */
  853                                 "\032<b25>"
  854                                 "\033DBE"       /* Data Breakpoint extension */
  855                                 "\034PTSC"      /* Performance TSC */
  856                                 "\035PL2I"      /* L2I perf count */
  857                                 "\036<b29>"
  858                                 "\037<b30>"
  859                                 "\040<b31>"
  860                                 );
  861                         }
  862 
  863                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
  864                                 print_via_padlock_info();
  865 
  866                         if ((cpu_feature & CPUID_HTT) &&
  867                             cpu_vendor_id == CPU_VENDOR_AMD)
  868                                 cpu_feature &= ~CPUID_HTT;
  869 
  870                         /*
  871                          * If this CPU supports P-state invariant TSC then
  872                          * mention the capability.
  873                          */
  874                         if (tsc_is_invariant) {
  875                                 printf("\n  TSC: P-state invariant");
  876                                 if (tsc_perf_stat)
  877                                         printf(", performance statistics");
  878                         }
  879 
  880                 }
  881         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
  882                 printf("  DIR=0x%04x", cyrix_did);
  883                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
  884                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
  885 #ifndef CYRIX_CACHE_REALLY_WORKS
  886                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
  887                         printf("\n  CPU cache: write-through mode");
  888 #endif
  889         }
  890 
  891         /* Avoid ugly blank lines: only print newline when we have to. */
  892         if (*cpu_vendor || cpu_id)
  893                 printf("\n");
  894 
  895         if (!bootverbose)
  896                 return;
  897 
  898         if (cpu_vendor_id == CPU_VENDOR_AMD)
  899                 print_AMD_info();
  900         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
  901                 print_INTEL_info();
  902         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
  903                 print_transmeta_info();
  904 }
  905 
  906 void
  907 panicifcpuunsupported(void)
  908 {
  909 
  910 #if !defined(lint)
  911 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
  912 #error This kernel is not configured for one of the supported CPUs
  913 #endif
  914 #else /* lint */
  915 #endif /* lint */
  916         /*
  917          * Now that we have told the user what they have,
  918          * let them know if that machine type isn't configured.
  919          */
  920         switch (cpu_class) {
  921         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
  922         case CPUCLASS_386:
  923 #if !defined(I486_CPU)
  924         case CPUCLASS_486:
  925 #endif
  926 #if !defined(I586_CPU)
  927         case CPUCLASS_586:
  928 #endif
  929 #if !defined(I686_CPU)
  930         case CPUCLASS_686:
  931 #endif
  932                 panic("CPU class not configured");
  933         default:
  934                 break;
  935         }
  936 }
  937 
  938 
  939 static  volatile u_int trap_by_rdmsr;
  940 
  941 /*
  942  * Special exception 6 handler.
  943  * The rdmsr instruction generates invalid opcodes fault on 486-class
  944  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
  945  * function identblue() when this handler is called.  Stacked eip should
  946  * be advanced.
  947  */
  948 inthand_t       bluetrap6;
  949 #ifdef __GNUCLIKE_ASM
  950 __asm
  951 ("                                                                      \n\
  952         .text                                                           \n\
  953         .p2align 2,0x90                                                 \n\
  954         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
  955 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
  956         ss                                                              \n\
  957         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  958         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  959         iret                                                            \n\
  960 ");
  961 #endif
  962 
  963 /*
  964  * Special exception 13 handler.
  965  * Accessing non-existent MSR generates general protection fault.
  966  */
  967 inthand_t       bluetrap13;
  968 #ifdef __GNUCLIKE_ASM
  969 __asm
  970 ("                                                                      \n\
  971         .text                                                           \n\
  972         .p2align 2,0x90                                                 \n\
  973         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
  974 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
  975         ss                                                              \n\
  976         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
  977         popl    %eax            /* discard error code */                \n\
  978         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
  979         iret                                                            \n\
  980 ");
  981 #endif
  982 
  983 /*
  984  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
  985  * support cpuid instruction.  This function should be called after
  986  * loading interrupt descriptor table register.
  987  *
  988  * I don't like this method that handles fault, but I couldn't get
  989  * information for any other methods.  Does blue giant know?
  990  */
  991 static int
  992 identblue(void)
  993 {
  994 
  995         trap_by_rdmsr = 0;
  996 
  997         /*
  998          * Cyrix 486-class CPU does not support rdmsr instruction.
  999          * The rdmsr instruction generates invalid opcode fault, and exception
 1000          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
 1001          * bluetrap6() set the magic number to trap_by_rdmsr.
 1002          */
 1003         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
 1004             GSEL(GCODE_SEL, SEL_KPL));
 1005 
 1006         /*
 1007          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
 1008          * In this case, rdmsr generates general protection fault, and
 1009          * exception will be trapped by bluetrap13().
 1010          */
 1011         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
 1012             GSEL(GCODE_SEL, SEL_KPL));
 1013 
 1014         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 1015 
 1016         if (trap_by_rdmsr == 0xa8c1d)
 1017                 return IDENTBLUE_CYRIX486;
 1018         else if (trap_by_rdmsr == 0xa89c4)
 1019                 return IDENTBLUE_CYRIXM2;
 1020         return IDENTBLUE_IBMCPU;
 1021 }
 1022 
 1023 
 1024 /*
 1025  * identifycyrix() set lower 16 bits of cyrix_did as follows:
 1026  *
 1027  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
 1028  * +-------+-------+---------------+
 1029  * |  SID  |  RID  |   Device ID   |
 1030  * |    (DIR 1)    |    (DIR 0)    |
 1031  * +-------+-------+---------------+
 1032  */
 1033 static void
 1034 identifycyrix(void)
 1035 {
 1036         register_t saveintr;
 1037         int     ccr2_test = 0, dir_test = 0;
 1038         u_char  ccr2, ccr3;
 1039 
 1040         saveintr = intr_disable();
 1041 
 1042         ccr2 = read_cyrix_reg(CCR2);
 1043         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
 1044         read_cyrix_reg(CCR2);
 1045         if (read_cyrix_reg(CCR2) != ccr2)
 1046                 ccr2_test = 1;
 1047         write_cyrix_reg(CCR2, ccr2);
 1048 
 1049         ccr3 = read_cyrix_reg(CCR3);
 1050         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
 1051         read_cyrix_reg(CCR3);
 1052         if (read_cyrix_reg(CCR3) != ccr3)
 1053                 dir_test = 1;                                   /* CPU supports DIRs. */
 1054         write_cyrix_reg(CCR3, ccr3);
 1055 
 1056         if (dir_test) {
 1057                 /* Device ID registers are available. */
 1058                 cyrix_did = read_cyrix_reg(DIR1) << 8;
 1059                 cyrix_did += read_cyrix_reg(DIR0);
 1060         } else if (ccr2_test)
 1061                 cyrix_did = 0x0010;             /* 486S A-step */
 1062         else
 1063                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
 1064 
 1065         intr_restore(saveintr);
 1066 }
 1067 
 1068 /* Update TSC freq with the value indicated by the caller. */
 1069 static void
 1070 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
 1071 {
 1072 
 1073         /* If there was an error during the transition, don't do anything. */
 1074         if (status != 0)
 1075                 return;
 1076 
 1077         /* Total setting for this level gives the new frequency in MHz. */
 1078         hw_clockrate = level->total_set.freq;
 1079 }
 1080 
 1081 static void
 1082 hook_tsc_freq(void *arg __unused)
 1083 {
 1084 
 1085         if (tsc_is_invariant)
 1086                 return;
 1087 
 1088         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
 1089             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
 1090 }
 1091 
 1092 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
 1093 
 1094 /*
 1095  * Final stage of CPU identification. -- Should I check TI?
 1096  */
 1097 void
 1098 finishidentcpu(void)
 1099 {
 1100         int     isblue = 0;
 1101         u_char  ccr3;
 1102         u_int   regs[4];
 1103 
 1104         cpu_vendor_id = find_cpu_vendor_id();
 1105 
 1106         /*
 1107          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
 1108          * function number again if it is set from BIOS.  It is necessary
 1109          * for probing correct CPU topology later.
 1110          * XXX This is only done on the BSP package.
 1111          */
 1112         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
 1113             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
 1114             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
 1115                 uint64_t msr;
 1116                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
 1117                 if ((msr & 0x400000ULL) != 0) {
 1118                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
 1119                         do_cpuid(0, regs);
 1120                         cpu_high = regs[0];
 1121                 }
 1122         }
 1123 
 1124         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
 1125         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 1126             cpu_vendor_id == CPU_VENDOR_AMD) {
 1127                 init_exthigh();
 1128                 if (cpu_exthigh >= 0x80000001) {
 1129                         do_cpuid(0x80000001, regs);
 1130                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 1131                         amd_feature2 = regs[2];
 1132                 }
 1133                 if (cpu_exthigh >= 0x80000007) {
 1134                         do_cpuid(0x80000007, regs);
 1135                         amd_pminfo = regs[3];
 1136                 }
 1137                 if (cpu_exthigh >= 0x80000008) {
 1138                         do_cpuid(0x80000008, regs);
 1139                         cpu_procinfo2 = regs[2];
 1140                 }
 1141         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 1142                 init_exthigh();
 1143                 if (cpu_exthigh >= 0x80000001) {
 1144                         do_cpuid(0x80000001, regs);
 1145                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 1146                 }
 1147         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 1148                 if (cpu == CPU_486) {
 1149                         /*
 1150                          * These conditions are equivalent to:
 1151                          *     - CPU does not support cpuid instruction.
 1152                          *     - Cyrix/IBM CPU is detected.
 1153                          */
 1154                         isblue = identblue();
 1155                         if (isblue == IDENTBLUE_IBMCPU) {
 1156                                 strcpy(cpu_vendor, "IBM");
 1157                                 cpu_vendor_id = CPU_VENDOR_IBM;
 1158                                 cpu = CPU_BLUE;
 1159                                 return;
 1160                         }
 1161                 }
 1162                 switch (cpu_id & 0xf00) {
 1163                 case 0x600:
 1164                         /*
 1165                          * Cyrix's datasheet does not describe DIRs.
 1166                          * Therefor, I assume it does not have them
 1167                          * and use the result of the cpuid instruction.
 1168                          * XXX they seem to have it for now at least. -Peter
 1169                          */
 1170                         identifycyrix();
 1171                         cpu = CPU_M2;
 1172                         break;
 1173                 default:
 1174                         identifycyrix();
 1175                         /*
 1176                          * This routine contains a trick.
 1177                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 1178                          */
 1179                         switch (cyrix_did & 0x00f0) {
 1180                         case 0x00:
 1181                         case 0xf0:
 1182                                 cpu = CPU_486DLC;
 1183                                 break;
 1184                         case 0x10:
 1185                                 cpu = CPU_CY486DX;
 1186                                 break;
 1187                         case 0x20:
 1188                                 if ((cyrix_did & 0x000f) < 8)
 1189                                         cpu = CPU_M1;
 1190                                 else
 1191                                         cpu = CPU_M1SC;
 1192                                 break;
 1193                         case 0x30:
 1194                                 cpu = CPU_M1;
 1195                                 break;
 1196                         case 0x40:
 1197                                 /* MediaGX CPU */
 1198                                 cpu = CPU_M1SC;
 1199                                 break;
 1200                         default:
 1201                                 /* M2 and later CPUs are treated as M2. */
 1202                                 cpu = CPU_M2;
 1203 
 1204                                 /*
 1205                                  * enable cpuid instruction.
 1206                                  */
 1207                                 ccr3 = read_cyrix_reg(CCR3);
 1208                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 1209                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 1210                                 write_cyrix_reg(CCR3, ccr3);
 1211 
 1212                                 do_cpuid(0, regs);
 1213                                 cpu_high = regs[0];     /* eax */
 1214                                 do_cpuid(1, regs);
 1215                                 cpu_id = regs[0];       /* eax */
 1216                                 cpu_feature = regs[3];  /* edx */
 1217                                 break;
 1218                         }
 1219                 }
 1220         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 1221                 /*
 1222                  * There are BlueLightning CPUs that do not change
 1223                  * undefined flags by dividing 5 by 2.  In this case,
 1224                  * the CPU identification routine in locore.s leaves
 1225                  * cpu_vendor null string and puts CPU_486 into the
 1226                  * cpu.
 1227                  */
 1228                 isblue = identblue();
 1229                 if (isblue == IDENTBLUE_IBMCPU) {
 1230                         strcpy(cpu_vendor, "IBM");
 1231                         cpu_vendor_id = CPU_VENDOR_IBM;
 1232                         cpu = CPU_BLUE;
 1233                         return;
 1234                 }
 1235         }
 1236 }
 1237 
 1238 static u_int
 1239 find_cpu_vendor_id(void)
 1240 {
 1241         int     i;
 1242 
 1243         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
 1244                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
 1245                         return (cpu_vendors[i].vendor_id);
 1246         return (0);
 1247 }
 1248 
 1249 static void
 1250 print_AMD_assoc(int i)
 1251 {
 1252         if (i == 255)
 1253                 printf(", fully associative\n");
 1254         else
 1255                 printf(", %d-way associative\n", i);
 1256 }
 1257 
 1258 static void
 1259 print_AMD_info(void)
 1260 {
 1261         quad_t amd_whcr;
 1262 
 1263         if (cpu_exthigh >= 0x80000005) {
 1264                 u_int regs[4];
 1265 
 1266                 do_cpuid(0x80000005, regs);
 1267                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
 1268                 print_AMD_assoc(regs[1] >> 24);
 1269                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
 1270                 print_AMD_assoc((regs[1] >> 8) & 0xff);
 1271                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
 1272                 printf(", %d bytes/line", regs[2] & 0xff);
 1273                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 1274                 print_AMD_assoc((regs[2] >> 16) & 0xff);
 1275                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 1276                 printf(", %d bytes/line", regs[3] & 0xff);
 1277                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 1278                 print_AMD_assoc((regs[3] >> 16) & 0xff);
 1279                 if (cpu_exthigh >= 0x80000006) {        /* K6-III only */
 1280                         do_cpuid(0x80000006, regs);
 1281                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
 1282                         printf(", %d bytes/line", regs[2] & 0xff);
 1283                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 1284                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
 1285                 }
 1286         }
 1287         if (((cpu_id & 0xf00) == 0x500)
 1288             && (((cpu_id & 0x0f0) > 0x80)
 1289                 || (((cpu_id & 0x0f0) == 0x80)
 1290                     && (cpu_id & 0x00f) > 0x07))) {
 1291                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
 1292                 amd_whcr = rdmsr(0xc0000082);
 1293                 if (!(amd_whcr & (0x3ff << 22))) {
 1294                         printf("Write Allocate Disable\n");
 1295                 } else {
 1296                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1297                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
 1298                         printf("Write Allocate 15-16M bytes: %s\n",
 1299                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
 1300                 }
 1301         } else if (((cpu_id & 0xf00) == 0x500)
 1302                    && ((cpu_id & 0x0f0) > 0x50)) {
 1303                 /* K6, K6-2(old core) */
 1304                 amd_whcr = rdmsr(0xc0000082);
 1305                 if (!(amd_whcr & (0x7f << 1))) {
 1306                         printf("Write Allocate Disable\n");
 1307                 } else {
 1308                         printf("Write Allocate Enable Limit: %dM bytes\n",
 1309                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
 1310                         printf("Write Allocate 15-16M bytes: %s\n",
 1311                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
 1312                         printf("Hardware Write Allocate Control: %s\n",
 1313                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
 1314                 }
 1315         }
 1316 
 1317         /*
 1318          * Opteron Rev E shows a bug as in very rare occasions a read memory
 1319          * barrier is not performed as expected if it is followed by a
 1320          * non-atomic read-modify-write instruction.
 1321          * As long as that bug pops up very rarely (intensive machine usage
 1322          * on other operating systems generally generates one unexplainable
 1323          * crash any 2 months) and as long as a model specific fix would be
 1324          * impratical at this stage, print out a warning string if the broken
 1325          * model and family are identified.
 1326          */
 1327         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
 1328             CPUID_TO_MODEL(cpu_id) <= 0x3f)
 1329                 printf("WARNING: This architecture revision has known SMP "
 1330                     "hardware bugs which may cause random instability\n");
 1331 }
 1332 
 1333 static void
 1334 print_INTEL_info(void)
 1335 {
 1336         u_int regs[4];
 1337         u_int rounds, regnum;
 1338         u_int nwaycode, nway;
 1339 
 1340         if (cpu_high >= 2) {
 1341                 rounds = 0;
 1342                 do {
 1343                         do_cpuid(0x2, regs);
 1344                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
 1345                                 break;  /* we have a buggy CPU */
 1346 
 1347                         for (regnum = 0; regnum <= 3; ++regnum) {
 1348                                 if (regs[regnum] & (1<<31))
 1349                                         continue;
 1350                                 if (regnum != 0)
 1351                                         print_INTEL_TLB(regs[regnum] & 0xff);
 1352                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
 1353                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
 1354                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
 1355                         }
 1356                 } while (--rounds > 0);
 1357         }
 1358 
 1359         if (cpu_exthigh >= 0x80000006) {
 1360                 do_cpuid(0x80000006, regs);
 1361                 nwaycode = (regs[2] >> 12) & 0x0f;
 1362                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
 1363                         nway = 1 << (nwaycode / 2);
 1364                 else
 1365                         nway = 0;
 1366                 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
 1367                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
 1368         }
 1369 
 1370         printf("\n");
 1371 }
 1372 
 1373 static void
 1374 print_INTEL_TLB(u_int data)
 1375 {
 1376         switch (data) {
 1377         case 0x0:
 1378         case 0x40:
 1379         default:
 1380                 break;
 1381         case 0x1:
 1382                 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
 1383                 break;
 1384         case 0x2:
 1385                 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
 1386                 break;
 1387         case 0x3:
 1388                 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
 1389                 break;
 1390         case 0x4:
 1391                 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
 1392                 break;
 1393         case 0x6:
 1394                 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
 1395                 break;
 1396         case 0x8:
 1397                 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
 1398                 break;
 1399         case 0xa:
 1400                 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
 1401                 break;
 1402         case 0xc:
 1403                 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
 1404                 break;
 1405         case 0x22:
 1406                 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
 1407                 break;
 1408         case 0x23:
 1409                 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
 1410                 break;
 1411         case 0x25:
 1412                 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
 1413                 break;
 1414         case 0x29:
 1415                 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
 1416                 break;
 1417         case 0x2c:
 1418                 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
 1419                 break;
 1420         case 0x30:
 1421                 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
 1422                 break;
 1423         case 0x39:
 1424                 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
 1425                 break;
 1426         case 0x3b:
 1427                 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
 1428                 break;
 1429         case 0x3c:
 1430                 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
 1431                 break;
 1432         case 0x41:
 1433                 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
 1434                 break;
 1435         case 0x42:
 1436                 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
 1437                 break;
 1438         case 0x43:
 1439                 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
 1440                 break;
 1441         case 0x44:
 1442                 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
 1443                 break;
 1444         case 0x45:
 1445                 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
 1446                 break;
 1447         case 0x46:
 1448                 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
 1449                 break;
 1450         case 0x47:
 1451                 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
 1452                 break;
 1453         case 0x50:
 1454                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
 1455                 break;
 1456         case 0x51:
 1457                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
 1458                 break;
 1459         case 0x52:
 1460                 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
 1461                 break;
 1462         case 0x5b:
 1463                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
 1464                 break;
 1465         case 0x5c:
 1466                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
 1467                 break;
 1468         case 0x5d:
 1469                 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
 1470                 break;
 1471         case 0x60:
 1472                 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
 1473                 break;
 1474         case 0x66:
 1475                 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
 1476                 break;
 1477         case 0x67:
 1478                 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
 1479                 break;
 1480         case 0x68:
 1481                 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
 1482                 break;
 1483         case 0x70:
 1484                 printf("\nTrace cache: 12K-uops, 8-way set associative");
 1485                 break;
 1486         case 0x71:
 1487                 printf("\nTrace cache: 16K-uops, 8-way set associative");
 1488                 break;
 1489         case 0x72:
 1490                 printf("\nTrace cache: 32K-uops, 8-way set associative");
 1491                 break;
 1492         case 0x78:
 1493                 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
 1494                 break;
 1495         case 0x79:
 1496                 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
 1497                 break;
 1498         case 0x7a:
 1499                 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
 1500                 break;
 1501         case 0x7b:
 1502                 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
 1503                 break;
 1504         case 0x7c:
 1505                 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
 1506                 break;
 1507         case 0x7d:
 1508                 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
 1509                 break;
 1510         case 0x7f:
 1511                 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
 1512                 break;
 1513         case 0x82:
 1514                 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
 1515                 break;
 1516         case 0x83:
 1517                 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
 1518                 break;
 1519         case 0x84:
 1520                 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
 1521                 break;
 1522         case 0x85:
 1523                 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
 1524                 break;
 1525         case 0x86:
 1526                 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
 1527                 break;
 1528         case 0x87:
 1529                 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
 1530                 break;
 1531         case 0xb0:
 1532                 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
 1533                 break;
 1534         case 0xb3:
 1535                 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
 1536                 break;
 1537         }
 1538 }
 1539 
 1540 static void
 1541 print_transmeta_info(void)
 1542 {
 1543         u_int regs[4], nreg = 0;
 1544 
 1545         do_cpuid(0x80860000, regs);
 1546         nreg = regs[0];
 1547         if (nreg >= 0x80860001) {
 1548                 do_cpuid(0x80860001, regs);
 1549                 printf("  Processor revision %u.%u.%u.%u\n",
 1550                        (regs[1] >> 24) & 0xff,
 1551                        (regs[1] >> 16) & 0xff,
 1552                        (regs[1] >> 8) & 0xff,
 1553                        regs[1] & 0xff);
 1554         }
 1555         if (nreg >= 0x80860002) {
 1556                 do_cpuid(0x80860002, regs);
 1557                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
 1558                        (regs[1] >> 24) & 0xff,
 1559                        (regs[1] >> 16) & 0xff,
 1560                        (regs[1] >> 8) & 0xff,
 1561                        regs[1] & 0xff,
 1562                        regs[2]);
 1563         }
 1564         if (nreg >= 0x80860006) {
 1565                 char info[65];
 1566                 do_cpuid(0x80860003, (u_int*) &info[0]);
 1567                 do_cpuid(0x80860004, (u_int*) &info[16]);
 1568                 do_cpuid(0x80860005, (u_int*) &info[32]);
 1569                 do_cpuid(0x80860006, (u_int*) &info[48]);
 1570                 info[64] = 0;
 1571                 printf("  %s\n", info);
 1572         }
 1573 }
 1574 
 1575 static void
 1576 print_via_padlock_info(void)
 1577 {
 1578         u_int regs[4];
 1579 
 1580         do_cpuid(0xc0000001, regs);
 1581         printf("\n  VIA Padlock Features=0x%b", regs[3],
 1582         "\020"
 1583         "\003RNG"               /* RNG */
 1584         "\007AES"               /* ACE */
 1585         "\011AES-CTR"           /* ACE2 */
 1586         "\013SHA1,SHA256"       /* PHE */
 1587         "\015RSA"               /* PMM */
 1588         );
 1589 }

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