1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/10.0/sys/i386/i386/initcpu.c 254384 2013-08-15 21:09:05Z jkim $");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46
47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
48 #define CPU_ENABLE_SSE
49 #endif
50
51 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
52 void enable_K5_wt_alloc(void);
53 void enable_K6_wt_alloc(void);
54 void enable_K6_2_wt_alloc(void);
55 #endif
56
57 #ifdef I486_CPU
58 static void init_5x86(void);
59 static void init_bluelightning(void);
60 static void init_486dlc(void);
61 static void init_cy486dx(void);
62 #ifdef CPU_I486_ON_386
63 static void init_i486_on_386(void);
64 #endif
65 static void init_6x86(void);
66 #endif /* I486_CPU */
67
68 #ifdef I686_CPU
69 static void init_6x86MX(void);
70 static void init_ppro(void);
71 static void init_mendocino(void);
72 #endif
73
74 static int hw_instruction_sse;
75 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
77 /*
78 * -1: automatic (default)
79 * 0: keep enable CLFLUSH
80 * 1: force disable CLFLUSH
81 */
82 static int hw_clflush_disable = -1;
83
84 /* Must *NOT* be BSS or locore will bzero these after setting them */
85 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
86 u_int cpu_feature = 0; /* Feature flags */
87 u_int cpu_feature2 = 0; /* Feature flags */
88 u_int amd_feature = 0; /* AMD feature flags */
89 u_int amd_feature2 = 0; /* AMD feature flags */
90 u_int amd_pminfo = 0; /* AMD advanced power management info */
91 u_int via_feature_rng = 0; /* VIA RNG features */
92 u_int via_feature_xcrypt = 0; /* VIA ACE features */
93 u_int cpu_high = 0; /* Highest arg to CPUID */
94 u_int cpu_id = 0; /* Stepping ID */
95 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
96 u_int cpu_procinfo2 = 0; /* Multicore info */
97 char cpu_vendor[20] = ""; /* CPU Origin code */
98 u_int cpu_vendor_id = 0; /* CPU vendor ID */
99 u_int cpu_clflush_line_size = 32;
100 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
101 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
102 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
103
104 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
105 &via_feature_rng, 0, "VIA RNG feature available in CPU");
106 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
107 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
108
109 #ifdef CPU_ENABLE_SSE
110 u_int cpu_fxsr; /* SSE enabled */
111 u_int cpu_mxcsr_mask; /* valid bits in mxcsr */
112 #endif
113
114 #ifdef I486_CPU
115 /*
116 * IBM Blue Lightning
117 */
118 static void
119 init_bluelightning(void)
120 {
121 register_t saveintr;
122
123 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
124 need_post_dma_flush = 1;
125 #endif
126
127 saveintr = intr_disable();
128
129 load_cr0(rcr0() | CR0_CD | CR0_NW);
130 invd();
131
132 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
133 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
134 #else
135 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
136 #endif
137 /* Enables 13MB and 0-640KB cache. */
138 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
139 #ifdef CPU_BLUELIGHTNING_3X
140 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
141 #else
142 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
143 #endif
144
145 /* Enable caching in CR0. */
146 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
147 invd();
148 intr_restore(saveintr);
149 }
150
151 /*
152 * Cyrix 486SLC/DLC/SR/DR series
153 */
154 static void
155 init_486dlc(void)
156 {
157 register_t saveintr;
158 u_char ccr0;
159
160 saveintr = intr_disable();
161 invd();
162
163 ccr0 = read_cyrix_reg(CCR0);
164 #ifndef CYRIX_CACHE_WORKS
165 ccr0 |= CCR0_NC1 | CCR0_BARB;
166 write_cyrix_reg(CCR0, ccr0);
167 invd();
168 #else
169 ccr0 &= ~CCR0_NC0;
170 #ifndef CYRIX_CACHE_REALLY_WORKS
171 ccr0 |= CCR0_NC1 | CCR0_BARB;
172 #else
173 ccr0 |= CCR0_NC1;
174 #endif
175 #ifdef CPU_DIRECT_MAPPED_CACHE
176 ccr0 |= CCR0_CO; /* Direct mapped mode. */
177 #endif
178 write_cyrix_reg(CCR0, ccr0);
179
180 /* Clear non-cacheable region. */
181 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
182 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
183 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
184 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
185
186 write_cyrix_reg(0, 0); /* dummy write */
187
188 /* Enable caching in CR0. */
189 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
190 invd();
191 #endif /* !CYRIX_CACHE_WORKS */
192 intr_restore(saveintr);
193 }
194
195
196 /*
197 * Cyrix 486S/DX series
198 */
199 static void
200 init_cy486dx(void)
201 {
202 register_t saveintr;
203 u_char ccr2;
204
205 saveintr = intr_disable();
206 invd();
207
208 ccr2 = read_cyrix_reg(CCR2);
209 #ifdef CPU_SUSP_HLT
210 ccr2 |= CCR2_SUSP_HLT;
211 #endif
212
213 #ifdef PC98
214 /* Enables WB cache interface pin and Lock NW bit in CR0. */
215 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
216 /* Unlock NW bit in CR0. */
217 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
218 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
219 #endif
220
221 write_cyrix_reg(CCR2, ccr2);
222 intr_restore(saveintr);
223 }
224
225
226 /*
227 * Cyrix 5x86
228 */
229 static void
230 init_5x86(void)
231 {
232 register_t saveintr;
233 u_char ccr2, ccr3, ccr4, pcr0;
234
235 saveintr = intr_disable();
236
237 load_cr0(rcr0() | CR0_CD | CR0_NW);
238 wbinvd();
239
240 (void)read_cyrix_reg(CCR3); /* dummy */
241
242 /* Initialize CCR2. */
243 ccr2 = read_cyrix_reg(CCR2);
244 ccr2 |= CCR2_WB;
245 #ifdef CPU_SUSP_HLT
246 ccr2 |= CCR2_SUSP_HLT;
247 #else
248 ccr2 &= ~CCR2_SUSP_HLT;
249 #endif
250 ccr2 |= CCR2_WT1;
251 write_cyrix_reg(CCR2, ccr2);
252
253 /* Initialize CCR4. */
254 ccr3 = read_cyrix_reg(CCR3);
255 write_cyrix_reg(CCR3, CCR3_MAPEN0);
256
257 ccr4 = read_cyrix_reg(CCR4);
258 ccr4 |= CCR4_DTE;
259 ccr4 |= CCR4_MEM;
260 #ifdef CPU_FASTER_5X86_FPU
261 ccr4 |= CCR4_FASTFPE;
262 #else
263 ccr4 &= ~CCR4_FASTFPE;
264 #endif
265 ccr4 &= ~CCR4_IOMASK;
266 /********************************************************************
267 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
268 * should be 0 for errata fix.
269 ********************************************************************/
270 #ifdef CPU_IORT
271 ccr4 |= CPU_IORT & CCR4_IOMASK;
272 #endif
273 write_cyrix_reg(CCR4, ccr4);
274
275 /* Initialize PCR0. */
276 /****************************************************************
277 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
278 * BTB_EN might make your system unstable.
279 ****************************************************************/
280 pcr0 = read_cyrix_reg(PCR0);
281 #ifdef CPU_RSTK_EN
282 pcr0 |= PCR0_RSTK;
283 #else
284 pcr0 &= ~PCR0_RSTK;
285 #endif
286 #ifdef CPU_BTB_EN
287 pcr0 |= PCR0_BTB;
288 #else
289 pcr0 &= ~PCR0_BTB;
290 #endif
291 #ifdef CPU_LOOP_EN
292 pcr0 |= PCR0_LOOP;
293 #else
294 pcr0 &= ~PCR0_LOOP;
295 #endif
296
297 /****************************************************************
298 * WARNING: if you use a memory mapped I/O device, don't use
299 * DISABLE_5X86_LSSER option, which may reorder memory mapped
300 * I/O access.
301 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
302 ****************************************************************/
303 #ifdef CPU_DISABLE_5X86_LSSER
304 pcr0 &= ~PCR0_LSSER;
305 #else
306 pcr0 |= PCR0_LSSER;
307 #endif
308 write_cyrix_reg(PCR0, pcr0);
309
310 /* Restore CCR3. */
311 write_cyrix_reg(CCR3, ccr3);
312
313 (void)read_cyrix_reg(0x80); /* dummy */
314
315 /* Unlock NW bit in CR0. */
316 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
317 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
318 /* Lock NW bit in CR0. */
319 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
320
321 intr_restore(saveintr);
322 }
323
324 #ifdef CPU_I486_ON_386
325 /*
326 * There are i486 based upgrade products for i386 machines.
327 * In this case, BIOS doesn't enable CPU cache.
328 */
329 static void
330 init_i486_on_386(void)
331 {
332 register_t saveintr;
333
334 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
335 need_post_dma_flush = 1;
336 #endif
337
338 saveintr = intr_disable();
339
340 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
341
342 intr_restore(saveintr);
343 }
344 #endif
345
346 /*
347 * Cyrix 6x86
348 *
349 * XXX - What should I do here? Please let me know.
350 */
351 static void
352 init_6x86(void)
353 {
354 register_t saveintr;
355 u_char ccr3, ccr4;
356
357 saveintr = intr_disable();
358
359 load_cr0(rcr0() | CR0_CD | CR0_NW);
360 wbinvd();
361
362 /* Initialize CCR0. */
363 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
364
365 /* Initialize CCR1. */
366 #ifdef CPU_CYRIX_NO_LOCK
367 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
368 #else
369 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
370 #endif
371
372 /* Initialize CCR2. */
373 #ifdef CPU_SUSP_HLT
374 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
375 #else
376 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
377 #endif
378
379 ccr3 = read_cyrix_reg(CCR3);
380 write_cyrix_reg(CCR3, CCR3_MAPEN0);
381
382 /* Initialize CCR4. */
383 ccr4 = read_cyrix_reg(CCR4);
384 ccr4 |= CCR4_DTE;
385 ccr4 &= ~CCR4_IOMASK;
386 #ifdef CPU_IORT
387 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
388 #else
389 write_cyrix_reg(CCR4, ccr4 | 7);
390 #endif
391
392 /* Initialize CCR5. */
393 #ifdef CPU_WT_ALLOC
394 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
395 #endif
396
397 /* Restore CCR3. */
398 write_cyrix_reg(CCR3, ccr3);
399
400 /* Unlock NW bit in CR0. */
401 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
402
403 /*
404 * Earlier revision of the 6x86 CPU could crash the system if
405 * L1 cache is in write-back mode.
406 */
407 if ((cyrix_did & 0xff00) > 0x1600)
408 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
409 else {
410 /* Revision 2.6 and lower. */
411 #ifdef CYRIX_CACHE_REALLY_WORKS
412 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
413 #else
414 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
415 #endif
416 }
417
418 /* Lock NW bit in CR0. */
419 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
420
421 intr_restore(saveintr);
422 }
423 #endif /* I486_CPU */
424
425 #ifdef I586_CPU
426 /*
427 * Rise mP6
428 */
429 static void
430 init_rise(void)
431 {
432
433 /*
434 * The CMPXCHG8B instruction is always available but hidden.
435 */
436 cpu_feature |= CPUID_CX8;
437 }
438
439 /*
440 * IDT WinChip C6/2/2A/2B/3
441 *
442 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
443 */
444 static void
445 init_winchip(void)
446 {
447 u_int regs[4];
448 uint64_t fcr;
449
450 fcr = rdmsr(0x0107);
451
452 /*
453 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
454 */
455 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
456 fcr &= ~(1ULL << 11);
457
458 /*
459 * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
460 */
461 if (CPUID_TO_MODEL(cpu_id) >= 8)
462 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
463
464 wrmsr(0x0107, fcr);
465 do_cpuid(1, regs);
466 cpu_feature = regs[3];
467 }
468 #endif
469
470 #ifdef I686_CPU
471 /*
472 * Cyrix 6x86MX (code-named M2)
473 *
474 * XXX - What should I do here? Please let me know.
475 */
476 static void
477 init_6x86MX(void)
478 {
479 register_t saveintr;
480 u_char ccr3, ccr4;
481
482 saveintr = intr_disable();
483
484 load_cr0(rcr0() | CR0_CD | CR0_NW);
485 wbinvd();
486
487 /* Initialize CCR0. */
488 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
489
490 /* Initialize CCR1. */
491 #ifdef CPU_CYRIX_NO_LOCK
492 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
493 #else
494 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
495 #endif
496
497 /* Initialize CCR2. */
498 #ifdef CPU_SUSP_HLT
499 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
500 #else
501 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
502 #endif
503
504 ccr3 = read_cyrix_reg(CCR3);
505 write_cyrix_reg(CCR3, CCR3_MAPEN0);
506
507 /* Initialize CCR4. */
508 ccr4 = read_cyrix_reg(CCR4);
509 ccr4 &= ~CCR4_IOMASK;
510 #ifdef CPU_IORT
511 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
512 #else
513 write_cyrix_reg(CCR4, ccr4 | 7);
514 #endif
515
516 /* Initialize CCR5. */
517 #ifdef CPU_WT_ALLOC
518 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
519 #endif
520
521 /* Restore CCR3. */
522 write_cyrix_reg(CCR3, ccr3);
523
524 /* Unlock NW bit in CR0. */
525 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
526
527 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
528
529 /* Lock NW bit in CR0. */
530 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
531
532 intr_restore(saveintr);
533 }
534
535 static void
536 init_ppro(void)
537 {
538 u_int64_t apicbase;
539
540 /*
541 * Local APIC should be disabled if it is not going to be used.
542 */
543 apicbase = rdmsr(MSR_APICBASE);
544 apicbase &= ~APICBASE_ENABLED;
545 wrmsr(MSR_APICBASE, apicbase);
546 }
547
548 /*
549 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
550 * L2 cache).
551 */
552 static void
553 init_mendocino(void)
554 {
555 #ifdef CPU_PPRO2CELERON
556 register_t saveintr;
557 u_int64_t bbl_cr_ctl3;
558
559 saveintr = intr_disable();
560
561 load_cr0(rcr0() | CR0_CD | CR0_NW);
562 wbinvd();
563
564 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
565
566 /* If the L2 cache is configured, do nothing. */
567 if (!(bbl_cr_ctl3 & 1)) {
568 bbl_cr_ctl3 = 0x134052bLL;
569
570 /* Set L2 Cache Latency (Default: 5). */
571 #ifdef CPU_CELERON_L2_LATENCY
572 #if CPU_L2_LATENCY > 15
573 #error invalid CPU_L2_LATENCY.
574 #endif
575 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
576 #else
577 bbl_cr_ctl3 |= 5 << 1;
578 #endif
579 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
580 }
581
582 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
583 intr_restore(saveintr);
584 #endif /* CPU_PPRO2CELERON */
585 }
586
587 /*
588 * Initialize special VIA features
589 */
590 static void
591 init_via(void)
592 {
593 u_int regs[4], val;
594 uint64_t fcr;
595
596 /*
597 * Explicitly enable CX8 and PGE on C3.
598 *
599 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
600 */
601 if (CPUID_TO_MODEL(cpu_id) <= 9)
602 fcr = (1 << 1) | (1 << 7);
603 else
604 fcr = 0;
605
606 /*
607 * Check extended CPUID for PadLock features.
608 *
609 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
610 */
611 do_cpuid(0xc0000000, regs);
612 if (regs[0] >= 0xc0000001) {
613 do_cpuid(0xc0000001, regs);
614 val = regs[3];
615 } else
616 val = 0;
617
618 /* Enable RNG if present. */
619 if ((val & VIA_CPUID_HAS_RNG) != 0) {
620 via_feature_rng = VIA_HAS_RNG;
621 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
622 }
623
624 /* Enable PadLock if present. */
625 if ((val & VIA_CPUID_HAS_ACE) != 0)
626 via_feature_xcrypt |= VIA_HAS_AES;
627 if ((val & VIA_CPUID_HAS_ACE2) != 0)
628 via_feature_xcrypt |= VIA_HAS_AESCTR;
629 if ((val & VIA_CPUID_HAS_PHE) != 0)
630 via_feature_xcrypt |= VIA_HAS_SHA;
631 if ((val & VIA_CPUID_HAS_PMM) != 0)
632 via_feature_xcrypt |= VIA_HAS_MM;
633 if (via_feature_xcrypt != 0)
634 fcr |= 1 << 28;
635
636 wrmsr(0x1107, rdmsr(0x1107) | fcr);
637 }
638
639 #endif /* I686_CPU */
640
641 #if defined(I586_CPU) || defined(I686_CPU)
642 static void
643 init_transmeta(void)
644 {
645 u_int regs[0];
646
647 /* Expose all hidden features. */
648 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
649 do_cpuid(1, regs);
650 cpu_feature = regs[3];
651 }
652 #endif
653
654 /*
655 * Initialize CR4 (Control register 4) to enable SSE instructions.
656 */
657 void
658 enable_sse(void)
659 {
660 #if defined(CPU_ENABLE_SSE)
661 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
662 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
663 cpu_fxsr = hw_instruction_sse = 1;
664 }
665 #endif
666 }
667
668 extern int elf32_nxstack;
669
670 void
671 initializecpu(void)
672 {
673
674 switch (cpu) {
675 #ifdef I486_CPU
676 case CPU_BLUE:
677 init_bluelightning();
678 break;
679 case CPU_486DLC:
680 init_486dlc();
681 break;
682 case CPU_CY486DX:
683 init_cy486dx();
684 break;
685 case CPU_M1SC:
686 init_5x86();
687 break;
688 #ifdef CPU_I486_ON_386
689 case CPU_486:
690 init_i486_on_386();
691 break;
692 #endif
693 case CPU_M1:
694 init_6x86();
695 break;
696 #endif /* I486_CPU */
697 #ifdef I586_CPU
698 case CPU_586:
699 switch (cpu_vendor_id) {
700 case CPU_VENDOR_CENTAUR:
701 init_winchip();
702 break;
703 case CPU_VENDOR_TRANSMETA:
704 init_transmeta();
705 break;
706 case CPU_VENDOR_RISE:
707 init_rise();
708 break;
709 }
710 break;
711 #endif
712 #ifdef I686_CPU
713 case CPU_M2:
714 init_6x86MX();
715 break;
716 case CPU_686:
717 switch (cpu_vendor_id) {
718 case CPU_VENDOR_INTEL:
719 switch (cpu_id & 0xff0) {
720 case 0x610:
721 init_ppro();
722 break;
723 case 0x660:
724 init_mendocino();
725 break;
726 }
727 break;
728 #ifdef CPU_ATHLON_SSE_HACK
729 case CPU_VENDOR_AMD:
730 /*
731 * Sometimes the BIOS doesn't enable SSE instructions.
732 * According to AMD document 20734, the mobile
733 * Duron, the (mobile) Athlon 4 and the Athlon MP
734 * support SSE. These correspond to cpu_id 0x66X
735 * or 0x67X.
736 */
737 if ((cpu_feature & CPUID_XMM) == 0 &&
738 ((cpu_id & ~0xf) == 0x660 ||
739 (cpu_id & ~0xf) == 0x670 ||
740 (cpu_id & ~0xf) == 0x680)) {
741 u_int regs[4];
742 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
743 do_cpuid(1, regs);
744 cpu_feature = regs[3];
745 }
746 break;
747 #endif
748 case CPU_VENDOR_CENTAUR:
749 init_via();
750 break;
751 case CPU_VENDOR_TRANSMETA:
752 init_transmeta();
753 break;
754 }
755 #ifdef PAE
756 if ((amd_feature & AMDID_NX) != 0) {
757 uint64_t msr;
758
759 msr = rdmsr(MSR_EFER) | EFER_NXE;
760 wrmsr(MSR_EFER, msr);
761 pg_nx = PG_NX;
762 elf32_nxstack = 1;
763 }
764 #endif
765 break;
766 #endif
767 default:
768 break;
769 }
770 enable_sse();
771
772 /*
773 * CPUID with %eax = 1, %ebx returns
774 * Bits 15-8: CLFLUSH line size
775 * (Value * 8 = cache line size in bytes)
776 */
777 if ((cpu_feature & CPUID_CLFSH) != 0)
778 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
779 /*
780 * XXXKIB: (temporary) hack to work around traps generated
781 * when CLFLUSHing APIC register window under virtualization
782 * environments. These environments tend to disable the
783 * CPUID_SS feature even though the native CPU supports it.
784 */
785 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
786 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
787 cpu_feature &= ~CPUID_CLFSH;
788 /*
789 * Allow to disable CLFLUSH feature manually by
790 * hw.clflush_disable tunable.
791 */
792 if (hw_clflush_disable == 1)
793 cpu_feature &= ~CPUID_CLFSH;
794
795 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
796 /*
797 * OS should flush L1 cache by itself because no PC-98 supports
798 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
799 * when need_pre_dma_flush = 1, use invd instruction after DMA
800 * transfer when need_post_dma_flush = 1. If your CPU upgrade
801 * product supports hardware cache control, you can add the
802 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
803 * This option eliminates unneeded cache flush instruction(s).
804 */
805 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
806 switch (cpu) {
807 #ifdef I486_CPU
808 case CPU_486DLC:
809 need_post_dma_flush = 1;
810 break;
811 case CPU_M1SC:
812 need_pre_dma_flush = 1;
813 break;
814 case CPU_CY486DX:
815 need_pre_dma_flush = 1;
816 #ifdef CPU_I486_ON_386
817 need_post_dma_flush = 1;
818 #endif
819 break;
820 #endif
821 default:
822 break;
823 }
824 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
825 switch (cpu_id & 0xFF0) {
826 case 0x470: /* Enhanced Am486DX2 WB */
827 case 0x490: /* Enhanced Am486DX4 WB */
828 case 0x4F0: /* Am5x86 WB */
829 need_pre_dma_flush = 1;
830 break;
831 }
832 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
833 need_post_dma_flush = 1;
834 } else {
835 #ifdef CPU_I486_ON_386
836 need_pre_dma_flush = 1;
837 #endif
838 }
839 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
840 }
841
842 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
843 /*
844 * Enable write allocate feature of AMD processors.
845 * Following two functions require the Maxmem variable being set.
846 */
847 void
848 enable_K5_wt_alloc(void)
849 {
850 u_int64_t msr;
851 register_t saveintr;
852
853 /*
854 * Write allocate is supported only on models 1, 2, and 3, with
855 * a stepping of 4 or greater.
856 */
857 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
858 saveintr = intr_disable();
859 msr = rdmsr(0x83); /* HWCR */
860 wrmsr(0x83, msr & !(0x10));
861
862 /*
863 * We have to tell the chip where the top of memory is,
864 * since video cards could have frame bufferes there,
865 * memory-mapped I/O could be there, etc.
866 */
867 if(Maxmem > 0)
868 msr = Maxmem / 16;
869 else
870 msr = 0;
871 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
872 #ifdef PC98
873 if (!(inb(0x43b) & 4)) {
874 wrmsr(0x86, 0x0ff00f0);
875 msr |= AMD_WT_ALLOC_PRE;
876 }
877 #else
878 /*
879 * There is no way to know wheter 15-16M hole exists or not.
880 * Therefore, we disable write allocate for this range.
881 */
882 wrmsr(0x86, 0x0ff00f0);
883 msr |= AMD_WT_ALLOC_PRE;
884 #endif
885 wrmsr(0x85, msr);
886
887 msr=rdmsr(0x83);
888 wrmsr(0x83, msr|0x10); /* enable write allocate */
889 intr_restore(saveintr);
890 }
891 }
892
893 void
894 enable_K6_wt_alloc(void)
895 {
896 quad_t size;
897 u_int64_t whcr;
898 register_t saveintr;
899
900 saveintr = intr_disable();
901 wbinvd();
902
903 #ifdef CPU_DISABLE_CACHE
904 /*
905 * Certain K6-2 box becomes unstable when write allocation is
906 * enabled.
907 */
908 /*
909 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
910 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
911 * All other bits in TR12 have no effect on the processer's operation.
912 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
913 * on the AMD-K6.
914 */
915 wrmsr(0x0000000e, (u_int64_t)0x0008);
916 #endif
917 /* Don't assume that memory size is aligned with 4M. */
918 if (Maxmem > 0)
919 size = ((Maxmem >> 8) + 3) >> 2;
920 else
921 size = 0;
922
923 /* Limit is 508M bytes. */
924 if (size > 0x7f)
925 size = 0x7f;
926 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
927
928 #if defined(PC98) || defined(NO_MEMORY_HOLE)
929 if (whcr & (0x7fLL << 1)) {
930 #ifdef PC98
931 /*
932 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
933 * 15-16M range.
934 */
935 if (!(inb(0x43b) & 4))
936 whcr &= ~0x0001LL;
937 else
938 #endif
939 whcr |= 0x0001LL;
940 }
941 #else
942 /*
943 * There is no way to know wheter 15-16M hole exists or not.
944 * Therefore, we disable write allocate for this range.
945 */
946 whcr &= ~0x0001LL;
947 #endif
948 wrmsr(0x0c0000082, whcr);
949
950 intr_restore(saveintr);
951 }
952
953 void
954 enable_K6_2_wt_alloc(void)
955 {
956 quad_t size;
957 u_int64_t whcr;
958 register_t saveintr;
959
960 saveintr = intr_disable();
961 wbinvd();
962
963 #ifdef CPU_DISABLE_CACHE
964 /*
965 * Certain K6-2 box becomes unstable when write allocation is
966 * enabled.
967 */
968 /*
969 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
970 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
971 * All other bits in TR12 have no effect on the processer's operation.
972 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
973 * on the AMD-K6.
974 */
975 wrmsr(0x0000000e, (u_int64_t)0x0008);
976 #endif
977 /* Don't assume that memory size is aligned with 4M. */
978 if (Maxmem > 0)
979 size = ((Maxmem >> 8) + 3) >> 2;
980 else
981 size = 0;
982
983 /* Limit is 4092M bytes. */
984 if (size > 0x3fff)
985 size = 0x3ff;
986 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
987
988 #if defined(PC98) || defined(NO_MEMORY_HOLE)
989 if (whcr & (0x3ffLL << 22)) {
990 #ifdef PC98
991 /*
992 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
993 * 15-16M range.
994 */
995 if (!(inb(0x43b) & 4))
996 whcr &= ~(1LL << 16);
997 else
998 #endif
999 whcr |= 1LL << 16;
1000 }
1001 #else
1002 /*
1003 * There is no way to know wheter 15-16M hole exists or not.
1004 * Therefore, we disable write allocate for this range.
1005 */
1006 whcr &= ~(1LL << 16);
1007 #endif
1008 wrmsr(0x0c0000082, whcr);
1009
1010 intr_restore(saveintr);
1011 }
1012 #endif /* I585_CPU && CPU_WT_ALLOC */
1013
1014 #include "opt_ddb.h"
1015 #ifdef DDB
1016 #include <ddb/ddb.h>
1017
1018 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1019 {
1020 register_t saveintr;
1021 u_int cr0;
1022 u_char ccr1, ccr2, ccr3;
1023 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1024
1025 cr0 = rcr0();
1026 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1027 saveintr = intr_disable();
1028
1029
1030 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1031 ccr0 = read_cyrix_reg(CCR0);
1032 }
1033 ccr1 = read_cyrix_reg(CCR1);
1034 ccr2 = read_cyrix_reg(CCR2);
1035 ccr3 = read_cyrix_reg(CCR3);
1036 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1037 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1038 ccr4 = read_cyrix_reg(CCR4);
1039 if ((cpu == CPU_M1) || (cpu == CPU_M2))
1040 ccr5 = read_cyrix_reg(CCR5);
1041 else
1042 pcr0 = read_cyrix_reg(PCR0);
1043 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
1044 }
1045 intr_restore(saveintr);
1046
1047 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1048 printf("CCR0=%x, ", (u_int)ccr0);
1049
1050 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1051 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1052 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1053 printf(", CCR4=%x, ", (u_int)ccr4);
1054 if (cpu == CPU_M1SC)
1055 printf("PCR0=%x\n", pcr0);
1056 else
1057 printf("CCR5=%x\n", ccr5);
1058 }
1059 }
1060 printf("CR0=%x\n", cr0);
1061 }
1062 #endif /* DDB */
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