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sys/i386/i386/initcpu.c
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1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/11.2/sys/i386/i386/initcpu.c 331722 2018-03-29 02:50:57Z eadler $"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 #ifdef I486_CPU 48 static void init_5x86(void); 49 static void init_bluelightning(void); 50 static void init_486dlc(void); 51 static void init_cy486dx(void); 52 #ifdef CPU_I486_ON_386 53 static void init_i486_on_386(void); 54 #endif 55 static void init_6x86(void); 56 #endif /* I486_CPU */ 57 58 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 59 static void enable_K5_wt_alloc(void); 60 static void enable_K6_wt_alloc(void); 61 static void enable_K6_2_wt_alloc(void); 62 #endif 63 64 #ifdef I686_CPU 65 static void init_6x86MX(void); 66 static void init_ppro(void); 67 static void init_mendocino(void); 68 #endif 69 70 static int hw_instruction_sse; 71 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 72 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 73 /* 74 * -1: automatic (default) 75 * 0: keep enable CLFLUSH 76 * 1: force disable CLFLUSH 77 */ 78 static int hw_clflush_disable = -1; 79 80 u_int cyrix_did; /* Device ID of Cyrix CPU */ 81 82 #ifdef I486_CPU 83 /* 84 * IBM Blue Lightning 85 */ 86 static void 87 init_bluelightning(void) 88 { 89 register_t saveintr; 90 91 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 92 need_post_dma_flush = 1; 93 #endif 94 95 saveintr = intr_disable(); 96 97 load_cr0(rcr0() | CR0_CD | CR0_NW); 98 invd(); 99 100 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 101 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 102 #else 103 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 104 #endif 105 /* Enables 13MB and 0-640KB cache. */ 106 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 107 #ifdef CPU_BLUELIGHTNING_3X 108 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 109 #else 110 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 111 #endif 112 113 /* Enable caching in CR0. */ 114 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 115 invd(); 116 intr_restore(saveintr); 117 } 118 119 /* 120 * Cyrix 486SLC/DLC/SR/DR series 121 */ 122 static void 123 init_486dlc(void) 124 { 125 register_t saveintr; 126 u_char ccr0; 127 128 saveintr = intr_disable(); 129 invd(); 130 131 ccr0 = read_cyrix_reg(CCR0); 132 #ifndef CYRIX_CACHE_WORKS 133 ccr0 |= CCR0_NC1 | CCR0_BARB; 134 write_cyrix_reg(CCR0, ccr0); 135 invd(); 136 #else 137 ccr0 &= ~CCR0_NC0; 138 #ifndef CYRIX_CACHE_REALLY_WORKS 139 ccr0 |= CCR0_NC1 | CCR0_BARB; 140 #else 141 ccr0 |= CCR0_NC1; 142 #endif 143 #ifdef CPU_DIRECT_MAPPED_CACHE 144 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 145 #endif 146 write_cyrix_reg(CCR0, ccr0); 147 148 /* Clear non-cacheable region. */ 149 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 150 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 151 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 152 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 153 154 write_cyrix_reg(0, 0); /* dummy write */ 155 156 /* Enable caching in CR0. */ 157 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 158 invd(); 159 #endif /* !CYRIX_CACHE_WORKS */ 160 intr_restore(saveintr); 161 } 162 163 164 /* 165 * Cyrix 486S/DX series 166 */ 167 static void 168 init_cy486dx(void) 169 { 170 register_t saveintr; 171 u_char ccr2; 172 173 saveintr = intr_disable(); 174 invd(); 175 176 ccr2 = read_cyrix_reg(CCR2); 177 #ifdef CPU_SUSP_HLT 178 ccr2 |= CCR2_SUSP_HLT; 179 #endif 180 181 #ifdef PC98 182 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 183 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 184 /* Unlock NW bit in CR0. */ 185 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 186 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 187 #endif 188 189 write_cyrix_reg(CCR2, ccr2); 190 intr_restore(saveintr); 191 } 192 193 194 /* 195 * Cyrix 5x86 196 */ 197 static void 198 init_5x86(void) 199 { 200 register_t saveintr; 201 u_char ccr2, ccr3, ccr4, pcr0; 202 203 saveintr = intr_disable(); 204 205 load_cr0(rcr0() | CR0_CD | CR0_NW); 206 wbinvd(); 207 208 (void)read_cyrix_reg(CCR3); /* dummy */ 209 210 /* Initialize CCR2. */ 211 ccr2 = read_cyrix_reg(CCR2); 212 ccr2 |= CCR2_WB; 213 #ifdef CPU_SUSP_HLT 214 ccr2 |= CCR2_SUSP_HLT; 215 #else 216 ccr2 &= ~CCR2_SUSP_HLT; 217 #endif 218 ccr2 |= CCR2_WT1; 219 write_cyrix_reg(CCR2, ccr2); 220 221 /* Initialize CCR4. */ 222 ccr3 = read_cyrix_reg(CCR3); 223 write_cyrix_reg(CCR3, CCR3_MAPEN0); 224 225 ccr4 = read_cyrix_reg(CCR4); 226 ccr4 |= CCR4_DTE; 227 ccr4 |= CCR4_MEM; 228 #ifdef CPU_FASTER_5X86_FPU 229 ccr4 |= CCR4_FASTFPE; 230 #else 231 ccr4 &= ~CCR4_FASTFPE; 232 #endif 233 ccr4 &= ~CCR4_IOMASK; 234 /******************************************************************** 235 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 236 * should be 0 for errata fix. 237 ********************************************************************/ 238 #ifdef CPU_IORT 239 ccr4 |= CPU_IORT & CCR4_IOMASK; 240 #endif 241 write_cyrix_reg(CCR4, ccr4); 242 243 /* Initialize PCR0. */ 244 /**************************************************************** 245 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 246 * BTB_EN might make your system unstable. 247 ****************************************************************/ 248 pcr0 = read_cyrix_reg(PCR0); 249 #ifdef CPU_RSTK_EN 250 pcr0 |= PCR0_RSTK; 251 #else 252 pcr0 &= ~PCR0_RSTK; 253 #endif 254 #ifdef CPU_BTB_EN 255 pcr0 |= PCR0_BTB; 256 #else 257 pcr0 &= ~PCR0_BTB; 258 #endif 259 #ifdef CPU_LOOP_EN 260 pcr0 |= PCR0_LOOP; 261 #else 262 pcr0 &= ~PCR0_LOOP; 263 #endif 264 265 /**************************************************************** 266 * WARNING: if you use a memory mapped I/O device, don't use 267 * DISABLE_5X86_LSSER option, which may reorder memory mapped 268 * I/O access. 269 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 270 ****************************************************************/ 271 #ifdef CPU_DISABLE_5X86_LSSER 272 pcr0 &= ~PCR0_LSSER; 273 #else 274 pcr0 |= PCR0_LSSER; 275 #endif 276 write_cyrix_reg(PCR0, pcr0); 277 278 /* Restore CCR3. */ 279 write_cyrix_reg(CCR3, ccr3); 280 281 (void)read_cyrix_reg(0x80); /* dummy */ 282 283 /* Unlock NW bit in CR0. */ 284 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 285 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 286 /* Lock NW bit in CR0. */ 287 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 288 289 intr_restore(saveintr); 290 } 291 292 #ifdef CPU_I486_ON_386 293 /* 294 * There are i486 based upgrade products for i386 machines. 295 * In this case, BIOS doesn't enable CPU cache. 296 */ 297 static void 298 init_i486_on_386(void) 299 { 300 register_t saveintr; 301 302 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 303 need_post_dma_flush = 1; 304 #endif 305 306 saveintr = intr_disable(); 307 308 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 309 310 intr_restore(saveintr); 311 } 312 #endif 313 314 /* 315 * Cyrix 6x86 316 * 317 * XXX - What should I do here? Please let me know. 318 */ 319 static void 320 init_6x86(void) 321 { 322 register_t saveintr; 323 u_char ccr3, ccr4; 324 325 saveintr = intr_disable(); 326 327 load_cr0(rcr0() | CR0_CD | CR0_NW); 328 wbinvd(); 329 330 /* Initialize CCR0. */ 331 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 332 333 /* Initialize CCR1. */ 334 #ifdef CPU_CYRIX_NO_LOCK 335 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 336 #else 337 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 338 #endif 339 340 /* Initialize CCR2. */ 341 #ifdef CPU_SUSP_HLT 342 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 343 #else 344 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 345 #endif 346 347 ccr3 = read_cyrix_reg(CCR3); 348 write_cyrix_reg(CCR3, CCR3_MAPEN0); 349 350 /* Initialize CCR4. */ 351 ccr4 = read_cyrix_reg(CCR4); 352 ccr4 |= CCR4_DTE; 353 ccr4 &= ~CCR4_IOMASK; 354 #ifdef CPU_IORT 355 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 356 #else 357 write_cyrix_reg(CCR4, ccr4 | 7); 358 #endif 359 360 /* Initialize CCR5. */ 361 #ifdef CPU_WT_ALLOC 362 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 363 #endif 364 365 /* Restore CCR3. */ 366 write_cyrix_reg(CCR3, ccr3); 367 368 /* Unlock NW bit in CR0. */ 369 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 370 371 /* 372 * Earlier revision of the 6x86 CPU could crash the system if 373 * L1 cache is in write-back mode. 374 */ 375 if ((cyrix_did & 0xff00) > 0x1600) 376 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 377 else { 378 /* Revision 2.6 and lower. */ 379 #ifdef CYRIX_CACHE_REALLY_WORKS 380 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 381 #else 382 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 383 #endif 384 } 385 386 /* Lock NW bit in CR0. */ 387 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 388 389 intr_restore(saveintr); 390 } 391 #endif /* I486_CPU */ 392 393 #ifdef I586_CPU 394 /* 395 * Rise mP6 396 */ 397 static void 398 init_rise(void) 399 { 400 401 /* 402 * The CMPXCHG8B instruction is always available but hidden. 403 */ 404 cpu_feature |= CPUID_CX8; 405 } 406 407 /* 408 * IDT WinChip C6/2/2A/2B/3 409 * 410 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 411 */ 412 static void 413 init_winchip(void) 414 { 415 u_int regs[4]; 416 uint64_t fcr; 417 418 fcr = rdmsr(0x0107); 419 420 /* 421 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 422 */ 423 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 424 fcr &= ~(1ULL << 11); 425 426 /* 427 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 428 */ 429 if (CPUID_TO_MODEL(cpu_id) >= 8) 430 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 431 432 wrmsr(0x0107, fcr); 433 do_cpuid(1, regs); 434 cpu_feature = regs[3]; 435 } 436 #endif 437 438 #ifdef I686_CPU 439 /* 440 * Cyrix 6x86MX (code-named M2) 441 * 442 * XXX - What should I do here? Please let me know. 443 */ 444 static void 445 init_6x86MX(void) 446 { 447 register_t saveintr; 448 u_char ccr3, ccr4; 449 450 saveintr = intr_disable(); 451 452 load_cr0(rcr0() | CR0_CD | CR0_NW); 453 wbinvd(); 454 455 /* Initialize CCR0. */ 456 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 457 458 /* Initialize CCR1. */ 459 #ifdef CPU_CYRIX_NO_LOCK 460 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 461 #else 462 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 463 #endif 464 465 /* Initialize CCR2. */ 466 #ifdef CPU_SUSP_HLT 467 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 468 #else 469 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 470 #endif 471 472 ccr3 = read_cyrix_reg(CCR3); 473 write_cyrix_reg(CCR3, CCR3_MAPEN0); 474 475 /* Initialize CCR4. */ 476 ccr4 = read_cyrix_reg(CCR4); 477 ccr4 &= ~CCR4_IOMASK; 478 #ifdef CPU_IORT 479 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 480 #else 481 write_cyrix_reg(CCR4, ccr4 | 7); 482 #endif 483 484 /* Initialize CCR5. */ 485 #ifdef CPU_WT_ALLOC 486 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 487 #endif 488 489 /* Restore CCR3. */ 490 write_cyrix_reg(CCR3, ccr3); 491 492 /* Unlock NW bit in CR0. */ 493 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 494 495 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 496 497 /* Lock NW bit in CR0. */ 498 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 499 500 intr_restore(saveintr); 501 } 502 503 static int ppro_apic_used = -1; 504 505 static void 506 init_ppro(void) 507 { 508 u_int64_t apicbase; 509 510 /* 511 * Local APIC should be disabled if it is not going to be used. 512 */ 513 if (ppro_apic_used != 1) { 514 apicbase = rdmsr(MSR_APICBASE); 515 apicbase &= ~APICBASE_ENABLED; 516 wrmsr(MSR_APICBASE, apicbase); 517 ppro_apic_used = 0; 518 } 519 } 520 521 /* 522 * If the local APIC is going to be used after being disabled above, 523 * re-enable it and don't disable it in the future. 524 */ 525 void 526 ppro_reenable_apic(void) 527 { 528 u_int64_t apicbase; 529 530 if (ppro_apic_used == 0) { 531 apicbase = rdmsr(MSR_APICBASE); 532 apicbase |= APICBASE_ENABLED; 533 wrmsr(MSR_APICBASE, apicbase); 534 ppro_apic_used = 1; 535 } 536 } 537 538 /* 539 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 540 * L2 cache). 541 */ 542 static void 543 init_mendocino(void) 544 { 545 #ifdef CPU_PPRO2CELERON 546 register_t saveintr; 547 u_int64_t bbl_cr_ctl3; 548 549 saveintr = intr_disable(); 550 551 load_cr0(rcr0() | CR0_CD | CR0_NW); 552 wbinvd(); 553 554 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 555 556 /* If the L2 cache is configured, do nothing. */ 557 if (!(bbl_cr_ctl3 & 1)) { 558 bbl_cr_ctl3 = 0x134052bLL; 559 560 /* Set L2 Cache Latency (Default: 5). */ 561 #ifdef CPU_CELERON_L2_LATENCY 562 #if CPU_L2_LATENCY > 15 563 #error invalid CPU_L2_LATENCY. 564 #endif 565 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 566 #else 567 bbl_cr_ctl3 |= 5 << 1; 568 #endif 569 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 570 } 571 572 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 573 intr_restore(saveintr); 574 #endif /* CPU_PPRO2CELERON */ 575 } 576 577 /* 578 * Initialize special VIA features 579 */ 580 static void 581 init_via(void) 582 { 583 u_int regs[4], val; 584 uint64_t fcr; 585 586 /* 587 * Explicitly enable CX8 and PGE on C3. 588 * 589 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 590 */ 591 if (CPUID_TO_MODEL(cpu_id) <= 9) 592 fcr = (1 << 1) | (1 << 7); 593 else 594 fcr = 0; 595 596 /* 597 * Check extended CPUID for PadLock features. 598 * 599 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 600 */ 601 do_cpuid(0xc0000000, regs); 602 if (regs[0] >= 0xc0000001) { 603 do_cpuid(0xc0000001, regs); 604 val = regs[3]; 605 } else 606 val = 0; 607 608 /* Enable RNG if present. */ 609 if ((val & VIA_CPUID_HAS_RNG) != 0) { 610 via_feature_rng = VIA_HAS_RNG; 611 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 612 } 613 614 /* Enable PadLock if present. */ 615 if ((val & VIA_CPUID_HAS_ACE) != 0) 616 via_feature_xcrypt |= VIA_HAS_AES; 617 if ((val & VIA_CPUID_HAS_ACE2) != 0) 618 via_feature_xcrypt |= VIA_HAS_AESCTR; 619 if ((val & VIA_CPUID_HAS_PHE) != 0) 620 via_feature_xcrypt |= VIA_HAS_SHA; 621 if ((val & VIA_CPUID_HAS_PMM) != 0) 622 via_feature_xcrypt |= VIA_HAS_MM; 623 if (via_feature_xcrypt != 0) 624 fcr |= 1 << 28; 625 626 wrmsr(0x1107, rdmsr(0x1107) | fcr); 627 } 628 629 #endif /* I686_CPU */ 630 631 #if defined(I586_CPU) || defined(I686_CPU) 632 static void 633 init_transmeta(void) 634 { 635 u_int regs[0]; 636 637 /* Expose all hidden features. */ 638 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 639 do_cpuid(1, regs); 640 cpu_feature = regs[3]; 641 } 642 #endif 643 644 extern int elf32_nxstack; 645 646 void 647 initializecpu(void) 648 { 649 650 switch (cpu) { 651 #ifdef I486_CPU 652 case CPU_BLUE: 653 init_bluelightning(); 654 break; 655 case CPU_486DLC: 656 init_486dlc(); 657 break; 658 case CPU_CY486DX: 659 init_cy486dx(); 660 break; 661 case CPU_M1SC: 662 init_5x86(); 663 break; 664 #ifdef CPU_I486_ON_386 665 case CPU_486: 666 init_i486_on_386(); 667 break; 668 #endif 669 case CPU_M1: 670 init_6x86(); 671 break; 672 #endif /* I486_CPU */ 673 #ifdef I586_CPU 674 case CPU_586: 675 switch (cpu_vendor_id) { 676 case CPU_VENDOR_AMD: 677 #ifdef CPU_WT_ALLOC 678 if (((cpu_id & 0x0f0) > 0) && 679 ((cpu_id & 0x0f0) < 0x60) && 680 ((cpu_id & 0x00f) > 3)) 681 enable_K5_wt_alloc(); 682 else if (((cpu_id & 0x0f0) > 0x80) || 683 (((cpu_id & 0x0f0) == 0x80) && 684 (cpu_id & 0x00f) > 0x07)) 685 enable_K6_2_wt_alloc(); 686 else if ((cpu_id & 0x0f0) > 0x50) 687 enable_K6_wt_alloc(); 688 #endif 689 if ((cpu_id & 0xf0) == 0xa0) 690 /* 691 * Make sure the TSC runs through 692 * suspension, otherwise we can't use 693 * it as timecounter 694 */ 695 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 696 break; 697 case CPU_VENDOR_CENTAUR: 698 init_winchip(); 699 break; 700 case CPU_VENDOR_TRANSMETA: 701 init_transmeta(); 702 break; 703 case CPU_VENDOR_RISE: 704 init_rise(); 705 break; 706 } 707 break; 708 #endif 709 #ifdef I686_CPU 710 case CPU_M2: 711 init_6x86MX(); 712 break; 713 case CPU_686: 714 switch (cpu_vendor_id) { 715 case CPU_VENDOR_INTEL: 716 switch (cpu_id & 0xff0) { 717 case 0x610: 718 init_ppro(); 719 break; 720 case 0x660: 721 init_mendocino(); 722 break; 723 } 724 break; 725 #ifdef CPU_ATHLON_SSE_HACK 726 case CPU_VENDOR_AMD: 727 /* 728 * Sometimes the BIOS doesn't enable SSE instructions. 729 * According to AMD document 20734, the mobile 730 * Duron, the (mobile) Athlon 4 and the Athlon MP 731 * support SSE. These correspond to cpu_id 0x66X 732 * or 0x67X. 733 */ 734 if ((cpu_feature & CPUID_XMM) == 0 && 735 ((cpu_id & ~0xf) == 0x660 || 736 (cpu_id & ~0xf) == 0x670 || 737 (cpu_id & ~0xf) == 0x680)) { 738 u_int regs[4]; 739 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 740 do_cpuid(1, regs); 741 cpu_feature = regs[3]; 742 } 743 break; 744 #endif 745 case CPU_VENDOR_CENTAUR: 746 init_via(); 747 break; 748 case CPU_VENDOR_TRANSMETA: 749 init_transmeta(); 750 break; 751 } 752 break; 753 #endif 754 default: 755 break; 756 } 757 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 758 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 759 cpu_fxsr = hw_instruction_sse = 1; 760 } 761 #if defined(PAE) || defined(PAE_TABLES) 762 if ((amd_feature & AMDID_NX) != 0) { 763 uint64_t msr; 764 765 msr = rdmsr(MSR_EFER) | EFER_NXE; 766 wrmsr(MSR_EFER, msr); 767 pg_nx = PG_NX; 768 elf32_nxstack = 1; 769 } 770 #endif 771 } 772 773 void 774 initializecpucache(void) 775 { 776 777 /* 778 * CPUID with %eax = 1, %ebx returns 779 * Bits 15-8: CLFLUSH line size 780 * (Value * 8 = cache line size in bytes) 781 */ 782 if ((cpu_feature & CPUID_CLFSH) != 0) 783 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 784 /* 785 * XXXKIB: (temporary) hack to work around traps generated 786 * when CLFLUSHing APIC register window under virtualization 787 * environments. These environments tend to disable the 788 * CPUID_SS feature even though the native CPU supports it. 789 */ 790 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 791 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 792 cpu_feature &= ~CPUID_CLFSH; 793 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 794 } 795 /* 796 * The kernel's use of CLFLUSH{,OPT} can be disabled manually 797 * by setting the hw.clflush_disable tunable. 798 */ 799 if (hw_clflush_disable == 1) { 800 cpu_feature &= ~CPUID_CLFSH; 801 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 802 } 803 804 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 805 /* 806 * OS should flush L1 cache by itself because no PC-98 supports 807 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 808 * when need_pre_dma_flush = 1, use invd instruction after DMA 809 * transfer when need_post_dma_flush = 1. If your CPU upgrade 810 * product supports hardware cache control, you can add the 811 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 812 * This option eliminates unneeded cache flush instruction(s). 813 */ 814 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 815 switch (cpu) { 816 #ifdef I486_CPU 817 case CPU_486DLC: 818 need_post_dma_flush = 1; 819 break; 820 case CPU_M1SC: 821 need_pre_dma_flush = 1; 822 break; 823 case CPU_CY486DX: 824 need_pre_dma_flush = 1; 825 #ifdef CPU_I486_ON_386 826 need_post_dma_flush = 1; 827 #endif 828 break; 829 #endif 830 default: 831 break; 832 } 833 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 834 switch (cpu_id & 0xFF0) { 835 case 0x470: /* Enhanced Am486DX2 WB */ 836 case 0x490: /* Enhanced Am486DX4 WB */ 837 case 0x4F0: /* Am5x86 WB */ 838 need_pre_dma_flush = 1; 839 break; 840 } 841 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 842 need_post_dma_flush = 1; 843 } else { 844 #ifdef CPU_I486_ON_386 845 need_pre_dma_flush = 1; 846 #endif 847 } 848 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 849 } 850 851 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 852 /* 853 * Enable write allocate feature of AMD processors. 854 * Following two functions require the Maxmem variable being set. 855 */ 856 static void 857 enable_K5_wt_alloc(void) 858 { 859 u_int64_t msr; 860 register_t saveintr; 861 862 /* 863 * Write allocate is supported only on models 1, 2, and 3, with 864 * a stepping of 4 or greater. 865 */ 866 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 867 saveintr = intr_disable(); 868 msr = rdmsr(0x83); /* HWCR */ 869 wrmsr(0x83, msr & !(0x10)); 870 871 /* 872 * We have to tell the chip where the top of memory is, 873 * since video cards could have frame bufferes there, 874 * memory-mapped I/O could be there, etc. 875 */ 876 if(Maxmem > 0) 877 msr = Maxmem / 16; 878 else 879 msr = 0; 880 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 881 #ifdef PC98 882 if (!(inb(0x43b) & 4)) { 883 wrmsr(0x86, 0x0ff00f0); 884 msr |= AMD_WT_ALLOC_PRE; 885 } 886 #else 887 /* 888 * There is no way to know wheter 15-16M hole exists or not. 889 * Therefore, we disable write allocate for this range. 890 */ 891 wrmsr(0x86, 0x0ff00f0); 892 msr |= AMD_WT_ALLOC_PRE; 893 #endif 894 wrmsr(0x85, msr); 895 896 msr=rdmsr(0x83); 897 wrmsr(0x83, msr|0x10); /* enable write allocate */ 898 intr_restore(saveintr); 899 } 900 } 901 902 static void 903 enable_K6_wt_alloc(void) 904 { 905 quad_t size; 906 u_int64_t whcr; 907 register_t saveintr; 908 909 saveintr = intr_disable(); 910 wbinvd(); 911 912 #ifdef CPU_DISABLE_CACHE 913 /* 914 * Certain K6-2 box becomes unstable when write allocation is 915 * enabled. 916 */ 917 /* 918 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 919 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 920 * All other bits in TR12 have no effect on the processer's operation. 921 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 922 * on the AMD-K6. 923 */ 924 wrmsr(0x0000000e, (u_int64_t)0x0008); 925 #endif 926 /* Don't assume that memory size is aligned with 4M. */ 927 if (Maxmem > 0) 928 size = ((Maxmem >> 8) + 3) >> 2; 929 else 930 size = 0; 931 932 /* Limit is 508M bytes. */ 933 if (size > 0x7f) 934 size = 0x7f; 935 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 936 937 #if defined(PC98) || defined(NO_MEMORY_HOLE) 938 if (whcr & (0x7fLL << 1)) { 939 #ifdef PC98 940 /* 941 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 942 * 15-16M range. 943 */ 944 if (!(inb(0x43b) & 4)) 945 whcr &= ~0x0001LL; 946 else 947 #endif 948 whcr |= 0x0001LL; 949 } 950 #else 951 /* 952 * There is no way to know wheter 15-16M hole exists or not. 953 * Therefore, we disable write allocate for this range. 954 */ 955 whcr &= ~0x0001LL; 956 #endif 957 wrmsr(0x0c0000082, whcr); 958 959 intr_restore(saveintr); 960 } 961 962 static void 963 enable_K6_2_wt_alloc(void) 964 { 965 quad_t size; 966 u_int64_t whcr; 967 register_t saveintr; 968 969 saveintr = intr_disable(); 970 wbinvd(); 971 972 #ifdef CPU_DISABLE_CACHE 973 /* 974 * Certain K6-2 box becomes unstable when write allocation is 975 * enabled. 976 */ 977 /* 978 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 979 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 980 * All other bits in TR12 have no effect on the processer's operation. 981 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 982 * on the AMD-K6. 983 */ 984 wrmsr(0x0000000e, (u_int64_t)0x0008); 985 #endif 986 /* Don't assume that memory size is aligned with 4M. */ 987 if (Maxmem > 0) 988 size = ((Maxmem >> 8) + 3) >> 2; 989 else 990 size = 0; 991 992 /* Limit is 4092M bytes. */ 993 if (size > 0x3fff) 994 size = 0x3ff; 995 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 996 997 #if defined(PC98) || defined(NO_MEMORY_HOLE) 998 if (whcr & (0x3ffLL << 22)) { 999 #ifdef PC98 1000 /* 1001 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 1002 * 15-16M range. 1003 */ 1004 if (!(inb(0x43b) & 4)) 1005 whcr &= ~(1LL << 16); 1006 else 1007 #endif 1008 whcr |= 1LL << 16; 1009 } 1010 #else 1011 /* 1012 * There is no way to know wheter 15-16M hole exists or not. 1013 * Therefore, we disable write allocate for this range. 1014 */ 1015 whcr &= ~(1LL << 16); 1016 #endif 1017 wrmsr(0x0c0000082, whcr); 1018 1019 intr_restore(saveintr); 1020 } 1021 #endif /* I585_CPU && CPU_WT_ALLOC */ 1022 1023 #include "opt_ddb.h" 1024 #ifdef DDB 1025 #include <ddb/ddb.h> 1026 1027 DB_SHOW_COMMAND(cyrixreg, cyrixreg) 1028 { 1029 register_t saveintr; 1030 u_int cr0; 1031 u_char ccr1, ccr2, ccr3; 1032 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 1033 1034 cr0 = rcr0(); 1035 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1036 saveintr = intr_disable(); 1037 1038 1039 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 1040 ccr0 = read_cyrix_reg(CCR0); 1041 } 1042 ccr1 = read_cyrix_reg(CCR1); 1043 ccr2 = read_cyrix_reg(CCR2); 1044 ccr3 = read_cyrix_reg(CCR3); 1045 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1046 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1047 ccr4 = read_cyrix_reg(CCR4); 1048 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 1049 ccr5 = read_cyrix_reg(CCR5); 1050 else 1051 pcr0 = read_cyrix_reg(PCR0); 1052 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 1053 } 1054 intr_restore(saveintr); 1055 1056 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 1057 printf("CCR0=%x, ", (u_int)ccr0); 1058 1059 printf("CCR1=%x, CCR2=%x, CCR3=%x", 1060 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 1061 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1062 printf(", CCR4=%x, ", (u_int)ccr4); 1063 if (cpu == CPU_M1SC) 1064 printf("PCR0=%x\n", pcr0); 1065 else 1066 printf("CCR5=%x\n", ccr5); 1067 } 1068 } 1069 printf("CR0=%x\n", cr0); 1070 } 1071 #endif /* DDB */
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