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sys/i386/i386/initcpu.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) KATO Takenori, 1997, 1998. 5 * 6 * All rights reserved. Unpublished rights reserved under the copyright 7 * laws of Japan. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer as 15 * the first lines of this file unmodified. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_cpu.h" 36 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/cputypes.h> 43 #include <machine/md_var.h> 44 #include <machine/psl.h> 45 #include <machine/specialreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #ifdef I486_CPU 51 static void init_5x86(void); 52 static void init_bluelightning(void); 53 static void init_486dlc(void); 54 static void init_cy486dx(void); 55 #ifdef CPU_I486_ON_386 56 static void init_i486_on_386(void); 57 #endif 58 static void init_6x86(void); 59 #endif /* I486_CPU */ 60 61 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 62 static void enable_K5_wt_alloc(void); 63 static void enable_K6_wt_alloc(void); 64 static void enable_K6_2_wt_alloc(void); 65 #endif 66 67 #ifdef I686_CPU 68 static void init_6x86MX(void); 69 static void init_ppro(void); 70 static void init_mendocino(void); 71 #endif 72 73 static int hw_instruction_sse; 74 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 75 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 76 /* 77 * -1: automatic (default) 78 * 0: keep enable CLFLUSH 79 * 1: force disable CLFLUSH 80 */ 81 static int hw_clflush_disable = -1; 82 83 u_int cyrix_did; /* Device ID of Cyrix CPU */ 84 85 #ifdef I486_CPU 86 /* 87 * IBM Blue Lightning 88 */ 89 static void 90 init_bluelightning(void) 91 { 92 register_t saveintr; 93 94 saveintr = intr_disable(); 95 96 load_cr0(rcr0() | CR0_CD | CR0_NW); 97 invd(); 98 99 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 100 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 101 #else 102 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 103 #endif 104 /* Enables 13MB and 0-640KB cache. */ 105 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 106 #ifdef CPU_BLUELIGHTNING_3X 107 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 108 #else 109 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 110 #endif 111 112 /* Enable caching in CR0. */ 113 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 114 invd(); 115 intr_restore(saveintr); 116 } 117 118 /* 119 * Cyrix 486SLC/DLC/SR/DR series 120 */ 121 static void 122 init_486dlc(void) 123 { 124 register_t saveintr; 125 u_char ccr0; 126 127 saveintr = intr_disable(); 128 invd(); 129 130 ccr0 = read_cyrix_reg(CCR0); 131 #ifndef CYRIX_CACHE_WORKS 132 ccr0 |= CCR0_NC1 | CCR0_BARB; 133 write_cyrix_reg(CCR0, ccr0); 134 invd(); 135 #else 136 ccr0 &= ~CCR0_NC0; 137 #ifndef CYRIX_CACHE_REALLY_WORKS 138 ccr0 |= CCR0_NC1 | CCR0_BARB; 139 #else 140 ccr0 |= CCR0_NC1; 141 #endif 142 #ifdef CPU_DIRECT_MAPPED_CACHE 143 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 144 #endif 145 write_cyrix_reg(CCR0, ccr0); 146 147 /* Clear non-cacheable region. */ 148 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 149 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 150 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 151 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 152 153 write_cyrix_reg(0, 0); /* dummy write */ 154 155 /* Enable caching in CR0. */ 156 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 157 invd(); 158 #endif /* !CYRIX_CACHE_WORKS */ 159 intr_restore(saveintr); 160 } 161 162 /* 163 * Cyrix 486S/DX series 164 */ 165 static void 166 init_cy486dx(void) 167 { 168 register_t saveintr; 169 u_char ccr2; 170 171 saveintr = intr_disable(); 172 invd(); 173 174 ccr2 = read_cyrix_reg(CCR2); 175 #ifdef CPU_SUSP_HLT 176 ccr2 |= CCR2_SUSP_HLT; 177 #endif 178 179 write_cyrix_reg(CCR2, ccr2); 180 intr_restore(saveintr); 181 } 182 183 /* 184 * Cyrix 5x86 185 */ 186 static void 187 init_5x86(void) 188 { 189 register_t saveintr; 190 u_char ccr2, ccr3, ccr4, pcr0; 191 192 saveintr = intr_disable(); 193 194 load_cr0(rcr0() | CR0_CD | CR0_NW); 195 wbinvd(); 196 197 (void)read_cyrix_reg(CCR3); /* dummy */ 198 199 /* Initialize CCR2. */ 200 ccr2 = read_cyrix_reg(CCR2); 201 ccr2 |= CCR2_WB; 202 #ifdef CPU_SUSP_HLT 203 ccr2 |= CCR2_SUSP_HLT; 204 #else 205 ccr2 &= ~CCR2_SUSP_HLT; 206 #endif 207 ccr2 |= CCR2_WT1; 208 write_cyrix_reg(CCR2, ccr2); 209 210 /* Initialize CCR4. */ 211 ccr3 = read_cyrix_reg(CCR3); 212 write_cyrix_reg(CCR3, CCR3_MAPEN0); 213 214 ccr4 = read_cyrix_reg(CCR4); 215 ccr4 |= CCR4_DTE; 216 ccr4 |= CCR4_MEM; 217 #ifdef CPU_FASTER_5X86_FPU 218 ccr4 |= CCR4_FASTFPE; 219 #else 220 ccr4 &= ~CCR4_FASTFPE; 221 #endif 222 ccr4 &= ~CCR4_IOMASK; 223 /******************************************************************** 224 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 225 * should be 0 for errata fix. 226 ********************************************************************/ 227 #ifdef CPU_IORT 228 ccr4 |= CPU_IORT & CCR4_IOMASK; 229 #endif 230 write_cyrix_reg(CCR4, ccr4); 231 232 /* Initialize PCR0. */ 233 /**************************************************************** 234 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 235 * BTB_EN might make your system unstable. 236 ****************************************************************/ 237 pcr0 = read_cyrix_reg(PCR0); 238 #ifdef CPU_RSTK_EN 239 pcr0 |= PCR0_RSTK; 240 #else 241 pcr0 &= ~PCR0_RSTK; 242 #endif 243 #ifdef CPU_BTB_EN 244 pcr0 |= PCR0_BTB; 245 #else 246 pcr0 &= ~PCR0_BTB; 247 #endif 248 #ifdef CPU_LOOP_EN 249 pcr0 |= PCR0_LOOP; 250 #else 251 pcr0 &= ~PCR0_LOOP; 252 #endif 253 254 /**************************************************************** 255 * WARNING: if you use a memory mapped I/O device, don't use 256 * DISABLE_5X86_LSSER option, which may reorder memory mapped 257 * I/O access. 258 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 259 ****************************************************************/ 260 #ifdef CPU_DISABLE_5X86_LSSER 261 pcr0 &= ~PCR0_LSSER; 262 #else 263 pcr0 |= PCR0_LSSER; 264 #endif 265 write_cyrix_reg(PCR0, pcr0); 266 267 /* Restore CCR3. */ 268 write_cyrix_reg(CCR3, ccr3); 269 270 (void)read_cyrix_reg(0x80); /* dummy */ 271 272 /* Unlock NW bit in CR0. */ 273 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 274 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 275 /* Lock NW bit in CR0. */ 276 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 277 278 intr_restore(saveintr); 279 } 280 281 #ifdef CPU_I486_ON_386 282 /* 283 * There are i486 based upgrade products for i386 machines. 284 * In this case, BIOS doesn't enable CPU cache. 285 */ 286 static void 287 init_i486_on_386(void) 288 { 289 register_t saveintr; 290 291 saveintr = intr_disable(); 292 293 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 294 295 intr_restore(saveintr); 296 } 297 #endif 298 299 /* 300 * Cyrix 6x86 301 * 302 * XXX - What should I do here? Please let me know. 303 */ 304 static void 305 init_6x86(void) 306 { 307 register_t saveintr; 308 u_char ccr3, ccr4; 309 310 saveintr = intr_disable(); 311 312 load_cr0(rcr0() | CR0_CD | CR0_NW); 313 wbinvd(); 314 315 /* Initialize CCR0. */ 316 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 317 318 /* Initialize CCR1. */ 319 #ifdef CPU_CYRIX_NO_LOCK 320 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 321 #else 322 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 323 #endif 324 325 /* Initialize CCR2. */ 326 #ifdef CPU_SUSP_HLT 327 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 328 #else 329 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 330 #endif 331 332 ccr3 = read_cyrix_reg(CCR3); 333 write_cyrix_reg(CCR3, CCR3_MAPEN0); 334 335 /* Initialize CCR4. */ 336 ccr4 = read_cyrix_reg(CCR4); 337 ccr4 |= CCR4_DTE; 338 ccr4 &= ~CCR4_IOMASK; 339 #ifdef CPU_IORT 340 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 341 #else 342 write_cyrix_reg(CCR4, ccr4 | 7); 343 #endif 344 345 /* Initialize CCR5. */ 346 #ifdef CPU_WT_ALLOC 347 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 348 #endif 349 350 /* Restore CCR3. */ 351 write_cyrix_reg(CCR3, ccr3); 352 353 /* Unlock NW bit in CR0. */ 354 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 355 356 /* 357 * Earlier revision of the 6x86 CPU could crash the system if 358 * L1 cache is in write-back mode. 359 */ 360 if ((cyrix_did & 0xff00) > 0x1600) 361 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 362 else { 363 /* Revision 2.6 and lower. */ 364 #ifdef CYRIX_CACHE_REALLY_WORKS 365 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 366 #else 367 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 368 #endif 369 } 370 371 /* Lock NW bit in CR0. */ 372 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 373 374 intr_restore(saveintr); 375 } 376 #endif /* I486_CPU */ 377 378 #ifdef I586_CPU 379 /* 380 * Rise mP6 381 */ 382 static void 383 init_rise(void) 384 { 385 386 /* 387 * The CMPXCHG8B instruction is always available but hidden. 388 */ 389 cpu_feature |= CPUID_CX8; 390 } 391 392 /* 393 * IDT WinChip C6/2/2A/2B/3 394 * 395 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 396 */ 397 static void 398 init_winchip(void) 399 { 400 u_int regs[4]; 401 uint64_t fcr; 402 403 fcr = rdmsr(0x0107); 404 405 /* 406 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 407 */ 408 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 409 fcr &= ~(1ULL << 11); 410 411 /* 412 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 413 */ 414 if (CPUID_TO_MODEL(cpu_id) >= 8) 415 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 416 417 wrmsr(0x0107, fcr); 418 do_cpuid(1, regs); 419 cpu_feature = regs[3]; 420 } 421 #endif 422 423 #ifdef I686_CPU 424 /* 425 * Cyrix 6x86MX (code-named M2) 426 * 427 * XXX - What should I do here? Please let me know. 428 */ 429 static void 430 init_6x86MX(void) 431 { 432 register_t saveintr; 433 u_char ccr3, ccr4; 434 435 saveintr = intr_disable(); 436 437 load_cr0(rcr0() | CR0_CD | CR0_NW); 438 wbinvd(); 439 440 /* Initialize CCR0. */ 441 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 442 443 /* Initialize CCR1. */ 444 #ifdef CPU_CYRIX_NO_LOCK 445 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 446 #else 447 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 448 #endif 449 450 /* Initialize CCR2. */ 451 #ifdef CPU_SUSP_HLT 452 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 453 #else 454 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 455 #endif 456 457 ccr3 = read_cyrix_reg(CCR3); 458 write_cyrix_reg(CCR3, CCR3_MAPEN0); 459 460 /* Initialize CCR4. */ 461 ccr4 = read_cyrix_reg(CCR4); 462 ccr4 &= ~CCR4_IOMASK; 463 #ifdef CPU_IORT 464 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 465 #else 466 write_cyrix_reg(CCR4, ccr4 | 7); 467 #endif 468 469 /* Initialize CCR5. */ 470 #ifdef CPU_WT_ALLOC 471 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 472 #endif 473 474 /* Restore CCR3. */ 475 write_cyrix_reg(CCR3, ccr3); 476 477 /* Unlock NW bit in CR0. */ 478 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 479 480 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 481 482 /* Lock NW bit in CR0. */ 483 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 484 485 intr_restore(saveintr); 486 } 487 488 static int ppro_apic_used = -1; 489 490 static void 491 init_ppro(void) 492 { 493 u_int64_t apicbase; 494 495 /* 496 * Local APIC should be disabled if it is not going to be used. 497 */ 498 if (ppro_apic_used != 1) { 499 apicbase = rdmsr(MSR_APICBASE); 500 apicbase &= ~APICBASE_ENABLED; 501 wrmsr(MSR_APICBASE, apicbase); 502 ppro_apic_used = 0; 503 } 504 } 505 506 /* 507 * If the local APIC is going to be used after being disabled above, 508 * re-enable it and don't disable it in the future. 509 */ 510 void 511 ppro_reenable_apic(void) 512 { 513 u_int64_t apicbase; 514 515 if (ppro_apic_used == 0) { 516 apicbase = rdmsr(MSR_APICBASE); 517 apicbase |= APICBASE_ENABLED; 518 wrmsr(MSR_APICBASE, apicbase); 519 ppro_apic_used = 1; 520 } 521 } 522 523 /* 524 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 525 * L2 cache). 526 */ 527 static void 528 init_mendocino(void) 529 { 530 #ifdef CPU_PPRO2CELERON 531 register_t saveintr; 532 u_int64_t bbl_cr_ctl3; 533 534 saveintr = intr_disable(); 535 536 load_cr0(rcr0() | CR0_CD | CR0_NW); 537 wbinvd(); 538 539 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 540 541 /* If the L2 cache is configured, do nothing. */ 542 if (!(bbl_cr_ctl3 & 1)) { 543 bbl_cr_ctl3 = 0x134052bLL; 544 545 /* Set L2 Cache Latency (Default: 5). */ 546 #ifdef CPU_CELERON_L2_LATENCY 547 #if CPU_L2_LATENCY > 15 548 #error invalid CPU_L2_LATENCY. 549 #endif 550 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 551 #else 552 bbl_cr_ctl3 |= 5 << 1; 553 #endif 554 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 555 } 556 557 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 558 intr_restore(saveintr); 559 #endif /* CPU_PPRO2CELERON */ 560 } 561 562 /* 563 * Initialize special VIA features 564 */ 565 static void 566 init_via(void) 567 { 568 u_int regs[4], val; 569 uint64_t fcr; 570 571 /* 572 * Explicitly enable CX8 and PGE on C3. 573 * 574 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 575 */ 576 if (CPUID_TO_MODEL(cpu_id) <= 9) 577 fcr = (1 << 1) | (1 << 7); 578 else 579 fcr = 0; 580 581 /* 582 * Check extended CPUID for PadLock features. 583 * 584 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 585 */ 586 do_cpuid(0xc0000000, regs); 587 if (regs[0] >= 0xc0000001) { 588 do_cpuid(0xc0000001, regs); 589 val = regs[3]; 590 } else 591 val = 0; 592 593 /* Enable RNG if present. */ 594 if ((val & VIA_CPUID_HAS_RNG) != 0) { 595 via_feature_rng = VIA_HAS_RNG; 596 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 597 } 598 599 /* Enable PadLock if present. */ 600 if ((val & VIA_CPUID_HAS_ACE) != 0) 601 via_feature_xcrypt |= VIA_HAS_AES; 602 if ((val & VIA_CPUID_HAS_ACE2) != 0) 603 via_feature_xcrypt |= VIA_HAS_AESCTR; 604 if ((val & VIA_CPUID_HAS_PHE) != 0) 605 via_feature_xcrypt |= VIA_HAS_SHA; 606 if ((val & VIA_CPUID_HAS_PMM) != 0) 607 via_feature_xcrypt |= VIA_HAS_MM; 608 if (via_feature_xcrypt != 0) 609 fcr |= 1 << 28; 610 611 wrmsr(0x1107, rdmsr(0x1107) | fcr); 612 } 613 614 #endif /* I686_CPU */ 615 616 #if defined(I586_CPU) || defined(I686_CPU) 617 static void 618 init_transmeta(void) 619 { 620 u_int regs[0]; 621 622 /* Expose all hidden features. */ 623 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 624 do_cpuid(1, regs); 625 cpu_feature = regs[3]; 626 } 627 #endif 628 629 /* 630 * The value for the TSC_AUX MSR and rdtscp/rdpid on the invoking CPU. 631 * 632 * Caller should prevent CPU migration. 633 */ 634 u_int 635 cpu_auxmsr(void) 636 { 637 KASSERT((read_eflags() & PSL_I) == 0, ("context switch possible")); 638 return (PCPU_GET(cpuid)); 639 } 640 641 extern int elf32_nxstack; 642 643 void 644 initializecpu(void) 645 { 646 uint64_t msr; 647 648 switch (cpu) { 649 #ifdef I486_CPU 650 case CPU_BLUE: 651 init_bluelightning(); 652 break; 653 case CPU_486DLC: 654 init_486dlc(); 655 break; 656 case CPU_CY486DX: 657 init_cy486dx(); 658 break; 659 case CPU_M1SC: 660 init_5x86(); 661 break; 662 #ifdef CPU_I486_ON_386 663 case CPU_486: 664 init_i486_on_386(); 665 break; 666 #endif 667 case CPU_M1: 668 init_6x86(); 669 break; 670 #endif /* I486_CPU */ 671 #ifdef I586_CPU 672 case CPU_586: 673 switch (cpu_vendor_id) { 674 case CPU_VENDOR_AMD: 675 #ifdef CPU_WT_ALLOC 676 if (((cpu_id & 0x0f0) > 0) && 677 ((cpu_id & 0x0f0) < 0x60) && 678 ((cpu_id & 0x00f) > 3)) 679 enable_K5_wt_alloc(); 680 else if (((cpu_id & 0x0f0) > 0x80) || 681 (((cpu_id & 0x0f0) == 0x80) && 682 (cpu_id & 0x00f) > 0x07)) 683 enable_K6_2_wt_alloc(); 684 else if ((cpu_id & 0x0f0) > 0x50) 685 enable_K6_wt_alloc(); 686 #endif 687 if ((cpu_id & 0xf0) == 0xa0) 688 /* 689 * Make sure the TSC runs through 690 * suspension, otherwise we can't use 691 * it as timecounter 692 */ 693 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 694 break; 695 case CPU_VENDOR_CENTAUR: 696 init_winchip(); 697 break; 698 case CPU_VENDOR_TRANSMETA: 699 init_transmeta(); 700 break; 701 case CPU_VENDOR_RISE: 702 init_rise(); 703 break; 704 } 705 break; 706 #endif 707 #ifdef I686_CPU 708 case CPU_M2: 709 init_6x86MX(); 710 break; 711 case CPU_686: 712 switch (cpu_vendor_id) { 713 case CPU_VENDOR_INTEL: 714 switch (cpu_id & 0xff0) { 715 case 0x610: 716 init_ppro(); 717 break; 718 case 0x660: 719 init_mendocino(); 720 break; 721 } 722 break; 723 case CPU_VENDOR_AMD: 724 #ifdef CPU_ATHLON_SSE_HACK 725 /* 726 * Sometimes the BIOS doesn't enable SSE instructions. 727 * According to AMD document 20734, the mobile 728 * Duron, the (mobile) Athlon 4 and the Athlon MP 729 * support SSE. These correspond to cpu_id 0x66X 730 * or 0x67X. 731 */ 732 if ((cpu_feature & CPUID_XMM) == 0 && 733 ((cpu_id & ~0xf) == 0x660 || 734 (cpu_id & ~0xf) == 0x670 || 735 (cpu_id & ~0xf) == 0x680)) { 736 u_int regs[4]; 737 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 738 do_cpuid(1, regs); 739 cpu_feature = regs[3]; 740 } 741 #endif 742 /* 743 * Detect C1E that breaks APIC. See comment in 744 * amd64/initcpu.c. 745 */ 746 if ((CPUID_TO_FAMILY(cpu_id) == 0xf || 747 CPUID_TO_FAMILY(cpu_id) == 0x10) && 748 (cpu_feature2 & CPUID2_HV) == 0) 749 cpu_amdc1e_bug = 1; 750 break; 751 case CPU_VENDOR_CENTAUR: 752 init_via(); 753 break; 754 case CPU_VENDOR_TRANSMETA: 755 init_transmeta(); 756 break; 757 } 758 break; 759 #endif 760 default: 761 break; 762 } 763 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 764 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 765 cpu_fxsr = hw_instruction_sse = 1; 766 } 767 if (elf32_nxstack) { 768 msr = rdmsr(MSR_EFER) | EFER_NXE; 769 wrmsr(MSR_EFER, msr); 770 } 771 if ((amd_feature & AMDID_RDTSCP) != 0 || 772 (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0) 773 wrmsr(MSR_TSC_AUX, cpu_auxmsr()); 774 } 775 776 void 777 initializecpucache(void) 778 { 779 780 /* 781 * CPUID with %eax = 1, %ebx returns 782 * Bits 15-8: CLFLUSH line size 783 * (Value * 8 = cache line size in bytes) 784 */ 785 if ((cpu_feature & CPUID_CLFSH) != 0) 786 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 787 /* 788 * XXXKIB: (temporary) hack to work around traps generated 789 * when CLFLUSHing APIC register window under virtualization 790 * environments. These environments tend to disable the 791 * CPUID_SS feature even though the native CPU supports it. 792 */ 793 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 794 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 795 cpu_feature &= ~CPUID_CLFSH; 796 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 797 } 798 /* 799 * The kernel's use of CLFLUSH{,OPT} can be disabled manually 800 * by setting the hw.clflush_disable tunable. 801 */ 802 if (hw_clflush_disable == 1) { 803 cpu_feature &= ~CPUID_CLFSH; 804 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 805 } 806 } 807 808 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 809 /* 810 * Enable write allocate feature of AMD processors. 811 * Following two functions require the Maxmem variable being set. 812 */ 813 static void 814 enable_K5_wt_alloc(void) 815 { 816 u_int64_t msr; 817 register_t saveintr; 818 819 /* 820 * Write allocate is supported only on models 1, 2, and 3, with 821 * a stepping of 4 or greater. 822 */ 823 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 824 saveintr = intr_disable(); 825 msr = rdmsr(0x83); /* HWCR */ 826 wrmsr(0x83, msr & !(0x10)); 827 828 /* 829 * We have to tell the chip where the top of memory is, 830 * since video cards could have frame bufferes there, 831 * memory-mapped I/O could be there, etc. 832 */ 833 if(Maxmem > 0) 834 msr = Maxmem / 16; 835 else 836 msr = 0; 837 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 838 839 /* 840 * There is no way to know whether 15-16M hole exists or not. 841 * Therefore, we disable write allocate for this range. 842 */ 843 wrmsr(0x86, 0x0ff00f0); 844 msr |= AMD_WT_ALLOC_PRE; 845 wrmsr(0x85, msr); 846 847 msr=rdmsr(0x83); 848 wrmsr(0x83, msr|0x10); /* enable write allocate */ 849 intr_restore(saveintr); 850 } 851 } 852 853 static void 854 enable_K6_wt_alloc(void) 855 { 856 quad_t size; 857 u_int64_t whcr; 858 register_t saveintr; 859 860 saveintr = intr_disable(); 861 wbinvd(); 862 863 #ifdef CPU_DISABLE_CACHE 864 /* 865 * Certain K6-2 box becomes unstable when write allocation is 866 * enabled. 867 */ 868 /* 869 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 870 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. 871 * All other bits in TR12 have no effect on the processer's operation. 872 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 873 * on the AMD-K6. 874 */ 875 wrmsr(0x0000000e, (u_int64_t)0x0008); 876 #endif 877 /* Don't assume that memory size is aligned with 4M. */ 878 if (Maxmem > 0) 879 size = ((Maxmem >> 8) + 3) >> 2; 880 else 881 size = 0; 882 883 /* Limit is 508M bytes. */ 884 if (size > 0x7f) 885 size = 0x7f; 886 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 887 888 #if defined(NO_MEMORY_HOLE) 889 if (whcr & (0x7fLL << 1)) 890 whcr |= 0x0001LL; 891 #else 892 /* 893 * There is no way to know whether 15-16M hole exists or not. 894 * Therefore, we disable write allocate for this range. 895 */ 896 whcr &= ~0x0001LL; 897 #endif 898 wrmsr(0x0c0000082, whcr); 899 900 intr_restore(saveintr); 901 } 902 903 static void 904 enable_K6_2_wt_alloc(void) 905 { 906 quad_t size; 907 u_int64_t whcr; 908 register_t saveintr; 909 910 saveintr = intr_disable(); 911 wbinvd(); 912 913 #ifdef CPU_DISABLE_CACHE 914 /* 915 * Certain K6-2 box becomes unstable when write allocation is 916 * enabled. 917 */ 918 /* 919 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 920 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. 921 * All other bits in TR12 have no effect on the processer's operation. 922 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 923 * on the AMD-K6. 924 */ 925 wrmsr(0x0000000e, (u_int64_t)0x0008); 926 #endif 927 /* Don't assume that memory size is aligned with 4M. */ 928 if (Maxmem > 0) 929 size = ((Maxmem >> 8) + 3) >> 2; 930 else 931 size = 0; 932 933 /* Limit is 4092M bytes. */ 934 if (size > 0x3fff) 935 size = 0x3ff; 936 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 937 938 #if defined(NO_MEMORY_HOLE) 939 if (whcr & (0x3ffLL << 22)) 940 whcr |= 1LL << 16; 941 #else 942 /* 943 * There is no way to know whether 15-16M hole exists or not. 944 * Therefore, we disable write allocate for this range. 945 */ 946 whcr &= ~(1LL << 16); 947 #endif 948 wrmsr(0x0c0000082, whcr); 949 950 intr_restore(saveintr); 951 } 952 #endif /* I585_CPU && CPU_WT_ALLOC */ 953 954 #include "opt_ddb.h" 955 #ifdef DDB 956 #include <ddb/ddb.h> 957 958 DB_SHOW_COMMAND(cyrixreg, cyrixreg) 959 { 960 register_t saveintr; 961 u_int cr0; 962 u_char ccr1, ccr2, ccr3; 963 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 964 965 cr0 = rcr0(); 966 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 967 saveintr = intr_disable(); 968 969 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 970 ccr0 = read_cyrix_reg(CCR0); 971 } 972 ccr1 = read_cyrix_reg(CCR1); 973 ccr2 = read_cyrix_reg(CCR2); 974 ccr3 = read_cyrix_reg(CCR3); 975 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 976 write_cyrix_reg(CCR3, CCR3_MAPEN0); 977 ccr4 = read_cyrix_reg(CCR4); 978 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 979 ccr5 = read_cyrix_reg(CCR5); 980 else 981 pcr0 = read_cyrix_reg(PCR0); 982 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 983 } 984 intr_restore(saveintr); 985 986 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 987 printf("CCR0=%x, ", (u_int)ccr0); 988 989 printf("CCR1=%x, CCR2=%x, CCR3=%x", 990 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 991 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 992 printf(", CCR4=%x, ", (u_int)ccr4); 993 if (cpu == CPU_M1SC) 994 printf("PCR0=%x\n", pcr0); 995 else 996 printf("CCR5=%x\n", ccr5); 997 } 998 } 999 printf("CR0=%x\n", cr0); 1000 } 1001 #endif /* DDB */
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