1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
43
44 #if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
45 #define CPU_ENABLE_SSE
46 #endif
47 #if defined(CPU_DISABLE_SSE)
48 #undef CPU_ENABLE_SSE
49 #endif
50
51 void initializecpu(void);
52 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
53 void enable_K5_wt_alloc(void);
54 void enable_K6_wt_alloc(void);
55 void enable_K6_2_wt_alloc(void);
56 #endif
57
58 #ifdef I486_CPU
59 static void init_5x86(void);
60 static void init_bluelightning(void);
61 static void init_486dlc(void);
62 static void init_cy486dx(void);
63 #ifdef CPU_I486_ON_386
64 static void init_i486_on_386(void);
65 #endif
66 static void init_6x86(void);
67 #endif /* I486_CPU */
68
69 #ifdef I686_CPU
70 static void init_6x86MX(void);
71 static void init_ppro(void);
72 static void init_mendocino(void);
73 #endif
74
75 static int hw_instruction_sse;
76 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
77 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
78
79 /* Must *NOT* be BSS or locore will bzero these after setting them */
80 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
81 u_int cpu_feature = 0; /* Feature flags */
82 u_int cpu_high = 0; /* Highest arg to CPUID */
83 u_int cpu_id = 0; /* Stepping ID */
84 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
85 char cpu_vendor[20] = ""; /* CPU Origin code */
86
87 #ifdef CPU_ENABLE_SSE
88 u_int cpu_fxsr; /* SSE enabled */
89 #endif
90
91 #ifdef I486_CPU
92 /*
93 * IBM Blue Lightning
94 */
95 static void
96 init_bluelightning(void)
97 {
98 u_long eflags;
99
100 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
101 need_post_dma_flush = 1;
102 #endif
103
104 eflags = read_eflags();
105 disable_intr();
106
107 load_cr0(rcr0() | CR0_CD | CR0_NW);
108 invd();
109
110 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
111 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
112 #else
113 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
114 #endif
115 /* Enables 13MB and 0-640KB cache. */
116 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
117 #ifdef CPU_BLUELIGHTNING_3X
118 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
119 #else
120 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
121 #endif
122
123 /* Enable caching in CR0. */
124 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
125 invd();
126 write_eflags(eflags);
127 }
128
129 /*
130 * Cyrix 486SLC/DLC/SR/DR series
131 */
132 static void
133 init_486dlc(void)
134 {
135 u_long eflags;
136 u_char ccr0;
137
138 eflags = read_eflags();
139 disable_intr();
140 invd();
141
142 ccr0 = read_cyrix_reg(CCR0);
143 #ifndef CYRIX_CACHE_WORKS
144 ccr0 |= CCR0_NC1 | CCR0_BARB;
145 write_cyrix_reg(CCR0, ccr0);
146 invd();
147 #else
148 ccr0 &= ~CCR0_NC0;
149 #ifndef CYRIX_CACHE_REALLY_WORKS
150 ccr0 |= CCR0_NC1 | CCR0_BARB;
151 #else
152 ccr0 |= CCR0_NC1;
153 #endif
154 #ifdef CPU_DIRECT_MAPPED_CACHE
155 ccr0 |= CCR0_CO; /* Direct mapped mode. */
156 #endif
157 write_cyrix_reg(CCR0, ccr0);
158
159 /* Clear non-cacheable region. */
160 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
161 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
162 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
163 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
164
165 write_cyrix_reg(0, 0); /* dummy write */
166
167 /* Enable caching in CR0. */
168 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
169 invd();
170 #endif /* !CYRIX_CACHE_WORKS */
171 write_eflags(eflags);
172 }
173
174
175 /*
176 * Cyrix 486S/DX series
177 */
178 static void
179 init_cy486dx(void)
180 {
181 u_long eflags;
182 u_char ccr2;
183
184 eflags = read_eflags();
185 disable_intr();
186 invd();
187
188 ccr2 = read_cyrix_reg(CCR2);
189 #ifdef CPU_SUSP_HLT
190 ccr2 |= CCR2_SUSP_HLT;
191 #endif
192
193 #ifdef PC98
194 /* Enables WB cache interface pin and Lock NW bit in CR0. */
195 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
196 /* Unlock NW bit in CR0. */
197 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
198 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
199 #endif
200
201 write_cyrix_reg(CCR2, ccr2);
202 write_eflags(eflags);
203 }
204
205
206 /*
207 * Cyrix 5x86
208 */
209 static void
210 init_5x86(void)
211 {
212 u_long eflags;
213 u_char ccr2, ccr3, ccr4, pcr0;
214
215 eflags = read_eflags();
216 disable_intr();
217
218 load_cr0(rcr0() | CR0_CD | CR0_NW);
219 wbinvd();
220
221 (void)read_cyrix_reg(CCR3); /* dummy */
222
223 /* Initialize CCR2. */
224 ccr2 = read_cyrix_reg(CCR2);
225 ccr2 |= CCR2_WB;
226 #ifdef CPU_SUSP_HLT
227 ccr2 |= CCR2_SUSP_HLT;
228 #else
229 ccr2 &= ~CCR2_SUSP_HLT;
230 #endif
231 ccr2 |= CCR2_WT1;
232 write_cyrix_reg(CCR2, ccr2);
233
234 /* Initialize CCR4. */
235 ccr3 = read_cyrix_reg(CCR3);
236 write_cyrix_reg(CCR3, CCR3_MAPEN0);
237
238 ccr4 = read_cyrix_reg(CCR4);
239 ccr4 |= CCR4_DTE;
240 ccr4 |= CCR4_MEM;
241 #ifdef CPU_FASTER_5X86_FPU
242 ccr4 |= CCR4_FASTFPE;
243 #else
244 ccr4 &= ~CCR4_FASTFPE;
245 #endif
246 ccr4 &= ~CCR4_IOMASK;
247 /********************************************************************
248 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
249 * should be 0 for errata fix.
250 ********************************************************************/
251 #ifdef CPU_IORT
252 ccr4 |= CPU_IORT & CCR4_IOMASK;
253 #endif
254 write_cyrix_reg(CCR4, ccr4);
255
256 /* Initialize PCR0. */
257 /****************************************************************
258 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
259 * BTB_EN might make your system unstable.
260 ****************************************************************/
261 pcr0 = read_cyrix_reg(PCR0);
262 #ifdef CPU_RSTK_EN
263 pcr0 |= PCR0_RSTK;
264 #else
265 pcr0 &= ~PCR0_RSTK;
266 #endif
267 #ifdef CPU_BTB_EN
268 pcr0 |= PCR0_BTB;
269 #else
270 pcr0 &= ~PCR0_BTB;
271 #endif
272 #ifdef CPU_LOOP_EN
273 pcr0 |= PCR0_LOOP;
274 #else
275 pcr0 &= ~PCR0_LOOP;
276 #endif
277
278 /****************************************************************
279 * WARNING: if you use a memory mapped I/O device, don't use
280 * DISABLE_5X86_LSSER option, which may reorder memory mapped
281 * I/O access.
282 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
283 ****************************************************************/
284 #ifdef CPU_DISABLE_5X86_LSSER
285 pcr0 &= ~PCR0_LSSER;
286 #else
287 pcr0 |= PCR0_LSSER;
288 #endif
289 write_cyrix_reg(PCR0, pcr0);
290
291 /* Restore CCR3. */
292 write_cyrix_reg(CCR3, ccr3);
293
294 (void)read_cyrix_reg(0x80); /* dummy */
295
296 /* Unlock NW bit in CR0. */
297 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
298 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
299 /* Lock NW bit in CR0. */
300 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
301
302 write_eflags(eflags);
303 }
304
305 #ifdef CPU_I486_ON_386
306 /*
307 * There are i486 based upgrade products for i386 machines.
308 * In this case, BIOS doesn't enables CPU cache.
309 */
310 static void
311 init_i486_on_386(void)
312 {
313 u_long eflags;
314
315 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
316 need_post_dma_flush = 1;
317 #endif
318
319 eflags = read_eflags();
320 disable_intr();
321
322 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
323
324 write_eflags(eflags);
325 }
326 #endif
327
328 /*
329 * Cyrix 6x86
330 *
331 * XXX - What should I do here? Please let me know.
332 */
333 static void
334 init_6x86(void)
335 {
336 u_long eflags;
337 u_char ccr3, ccr4;
338
339 eflags = read_eflags();
340 disable_intr();
341
342 load_cr0(rcr0() | CR0_CD | CR0_NW);
343 wbinvd();
344
345 /* Initialize CCR0. */
346 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
347
348 /* Initialize CCR1. */
349 #ifdef CPU_CYRIX_NO_LOCK
350 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
351 #else
352 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
353 #endif
354
355 /* Initialize CCR2. */
356 #ifdef CPU_SUSP_HLT
357 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
358 #else
359 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
360 #endif
361
362 ccr3 = read_cyrix_reg(CCR3);
363 write_cyrix_reg(CCR3, CCR3_MAPEN0);
364
365 /* Initialize CCR4. */
366 ccr4 = read_cyrix_reg(CCR4);
367 ccr4 |= CCR4_DTE;
368 ccr4 &= ~CCR4_IOMASK;
369 #ifdef CPU_IORT
370 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
371 #else
372 write_cyrix_reg(CCR4, ccr4 | 7);
373 #endif
374
375 /* Initialize CCR5. */
376 #ifdef CPU_WT_ALLOC
377 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
378 #endif
379
380 /* Restore CCR3. */
381 write_cyrix_reg(CCR3, ccr3);
382
383 /* Unlock NW bit in CR0. */
384 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
385
386 /*
387 * Earlier revision of the 6x86 CPU could crash the system if
388 * L1 cache is in write-back mode.
389 */
390 if ((cyrix_did & 0xff00) > 0x1600)
391 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
392 else {
393 /* Revision 2.6 and lower. */
394 #ifdef CYRIX_CACHE_REALLY_WORKS
395 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
396 #else
397 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
398 #endif
399 }
400
401 /* Lock NW bit in CR0. */
402 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
403
404 write_eflags(eflags);
405 }
406 #endif /* I486_CPU */
407
408 #ifdef I686_CPU
409 /*
410 * Cyrix 6x86MX (code-named M2)
411 *
412 * XXX - What should I do here? Please let me know.
413 */
414 static void
415 init_6x86MX(void)
416 {
417 u_long eflags;
418 u_char ccr3, ccr4;
419
420 eflags = read_eflags();
421 disable_intr();
422
423 load_cr0(rcr0() | CR0_CD | CR0_NW);
424 wbinvd();
425
426 /* Initialize CCR0. */
427 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
428
429 /* Initialize CCR1. */
430 #ifdef CPU_CYRIX_NO_LOCK
431 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
432 #else
433 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
434 #endif
435
436 /* Initialize CCR2. */
437 #ifdef CPU_SUSP_HLT
438 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
439 #else
440 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
441 #endif
442
443 ccr3 = read_cyrix_reg(CCR3);
444 write_cyrix_reg(CCR3, CCR3_MAPEN0);
445
446 /* Initialize CCR4. */
447 ccr4 = read_cyrix_reg(CCR4);
448 ccr4 &= ~CCR4_IOMASK;
449 #ifdef CPU_IORT
450 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
451 #else
452 write_cyrix_reg(CCR4, ccr4 | 7);
453 #endif
454
455 /* Initialize CCR5. */
456 #ifdef CPU_WT_ALLOC
457 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
458 #endif
459
460 /* Restore CCR3. */
461 write_cyrix_reg(CCR3, ccr3);
462
463 /* Unlock NW bit in CR0. */
464 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
465
466 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
467
468 /* Lock NW bit in CR0. */
469 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
470
471 write_eflags(eflags);
472 }
473
474 static void
475 init_ppro(void)
476 {
477 u_int64_t apicbase;
478
479 /*
480 * Local APIC should be disabled if it is not going to be used.
481 */
482 apicbase = rdmsr(MSR_APICBASE);
483 apicbase &= ~APICBASE_ENABLED;
484 wrmsr(MSR_APICBASE, apicbase);
485 }
486
487 /*
488 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
489 * L2 cache).
490 */
491 static void
492 init_mendocino(void)
493 {
494 #ifdef CPU_PPRO2CELERON
495 u_long eflags;
496 u_int64_t bbl_cr_ctl3;
497
498 eflags = read_eflags();
499 disable_intr();
500
501 load_cr0(rcr0() | CR0_CD | CR0_NW);
502 wbinvd();
503
504 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
505
506 /* If the L2 cache is configured, do nothing. */
507 if (!(bbl_cr_ctl3 & 1)) {
508 bbl_cr_ctl3 = 0x134052bLL;
509
510 /* Set L2 Cache Latency (Default: 5). */
511 #ifdef CPU_CELERON_L2_LATENCY
512 #if CPU_L2_LATENCY > 15
513 #error invalid CPU_L2_LATENCY.
514 #endif
515 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
516 #else
517 bbl_cr_ctl3 |= 5 << 1;
518 #endif
519 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
520 }
521
522 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
523 write_eflags(eflags);
524 #endif /* CPU_PPRO2CELERON */
525 }
526
527 #endif /* I686_CPU */
528
529 /*
530 * Initialize CR4 (Control register 4) to enable SSE instructions.
531 */
532 void
533 enable_sse(void)
534 {
535 #if defined(CPU_ENABLE_SSE)
536 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
537 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
538 cpu_fxsr = hw_instruction_sse = 1;
539 }
540 #endif
541 }
542
543 void
544 initializecpu(void)
545 {
546
547 switch (cpu) {
548 #ifdef I486_CPU
549 case CPU_BLUE:
550 init_bluelightning();
551 break;
552 case CPU_486DLC:
553 init_486dlc();
554 break;
555 case CPU_CY486DX:
556 init_cy486dx();
557 break;
558 case CPU_M1SC:
559 init_5x86();
560 break;
561 #ifdef CPU_I486_ON_386
562 case CPU_486:
563 init_i486_on_386();
564 break;
565 #endif
566 case CPU_M1:
567 init_6x86();
568 break;
569 #endif /* I486_CPU */
570 #ifdef I686_CPU
571 case CPU_M2:
572 init_6x86MX();
573 break;
574 case CPU_686:
575 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
576 switch (cpu_id & 0xff0) {
577 case 0x610:
578 init_ppro();
579 break;
580 case 0x660:
581 init_mendocino();
582 break;
583 }
584 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
585 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
586 /*
587 * Sometimes the BIOS doesn't enable SSE instructions.
588 * According to AMD document 20734, the mobile
589 * Duron, the (mobile) Athlon 4 and the Athlon MP
590 * support SSE. These correspond to cpu_id 0x66X
591 * or 0x67X.
592 */
593 if ((cpu_feature & CPUID_XMM) == 0 &&
594 ((cpu_id & ~0xf) == 0x660 ||
595 (cpu_id & ~0xf) == 0x670 ||
596 (cpu_id & ~0xf) == 0x680)) {
597 u_int regs[4];
598 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
599 do_cpuid(1, regs);
600 cpu_feature = regs[3];
601 }
602 #endif
603 }
604 break;
605 #endif
606 default:
607 break;
608 }
609 enable_sse();
610
611 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
612 /*
613 * OS should flush L1 cache by itself because no PC-98 supports
614 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
615 * when need_pre_dma_flush = 1, use invd instruction after DMA
616 * transfer when need_post_dma_flush = 1. If your CPU upgrade
617 * product supports hardware cache control, you can add the
618 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
619 * This option eliminates unneeded cache flush instruction(s).
620 */
621 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
622 switch (cpu) {
623 #ifdef I486_CPU
624 case CPU_486DLC:
625 need_post_dma_flush = 1;
626 break;
627 case CPU_M1SC:
628 need_pre_dma_flush = 1;
629 break;
630 case CPU_CY486DX:
631 need_pre_dma_flush = 1;
632 #ifdef CPU_I486_ON_386
633 need_post_dma_flush = 1;
634 #endif
635 break;
636 #endif
637 default:
638 break;
639 }
640 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
641 switch (cpu_id & 0xFF0) {
642 case 0x470: /* Enhanced Am486DX2 WB */
643 case 0x490: /* Enhanced Am486DX4 WB */
644 case 0x4F0: /* Am5x86 WB */
645 need_pre_dma_flush = 1;
646 break;
647 }
648 } else if (strcmp(cpu_vendor, "IBM") == 0) {
649 need_post_dma_flush = 1;
650 } else {
651 #ifdef CPU_I486_ON_386
652 need_pre_dma_flush = 1;
653 #endif
654 }
655 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
656 }
657
658 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
659 /*
660 * Enable write allocate feature of AMD processors.
661 * Following two functions require the Maxmem variable being set.
662 */
663 void
664 enable_K5_wt_alloc(void)
665 {
666 u_int64_t msr;
667 register_t savecrit;
668
669 /*
670 * Write allocate is supported only on models 1, 2, and 3, with
671 * a stepping of 4 or greater.
672 */
673 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
674 savecrit = intr_disable();
675 msr = rdmsr(0x83); /* HWCR */
676 wrmsr(0x83, msr & !(0x10));
677
678 /*
679 * We have to tell the chip where the top of memory is,
680 * since video cards could have frame bufferes there,
681 * memory-mapped I/O could be there, etc.
682 */
683 if(Maxmem > 0)
684 msr = Maxmem / 16;
685 else
686 msr = 0;
687 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
688 #ifdef PC98
689 if (!(inb(0x43b) & 4)) {
690 wrmsr(0x86, 0x0ff00f0);
691 msr |= AMD_WT_ALLOC_PRE;
692 }
693 #else
694 /*
695 * There is no way to know wheter 15-16M hole exists or not.
696 * Therefore, we disable write allocate for this range.
697 */
698 wrmsr(0x86, 0x0ff00f0);
699 msr |= AMD_WT_ALLOC_PRE;
700 #endif
701 wrmsr(0x85, msr);
702
703 msr=rdmsr(0x83);
704 wrmsr(0x83, msr|0x10); /* enable write allocate */
705 intr_restore(savecrit);
706 }
707 }
708
709 void
710 enable_K6_wt_alloc(void)
711 {
712 quad_t size;
713 u_int64_t whcr;
714 u_long eflags;
715
716 eflags = read_eflags();
717 disable_intr();
718 wbinvd();
719
720 #ifdef CPU_DISABLE_CACHE
721 /*
722 * Certain K6-2 box becomes unstable when write allocation is
723 * enabled.
724 */
725 /*
726 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
727 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
728 * All other bits in TR12 have no effect on the processer's operation.
729 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
730 * on the AMD-K6.
731 */
732 wrmsr(0x0000000e, (u_int64_t)0x0008);
733 #endif
734 /* Don't assume that memory size is aligned with 4M. */
735 if (Maxmem > 0)
736 size = ((Maxmem >> 8) + 3) >> 2;
737 else
738 size = 0;
739
740 /* Limit is 508M bytes. */
741 if (size > 0x7f)
742 size = 0x7f;
743 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
744
745 #if defined(PC98) || defined(NO_MEMORY_HOLE)
746 if (whcr & (0x7fLL << 1)) {
747 #ifdef PC98
748 /*
749 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
750 * 15-16M range.
751 */
752 if (!(inb(0x43b) & 4))
753 whcr &= ~0x0001LL;
754 else
755 #endif
756 whcr |= 0x0001LL;
757 }
758 #else
759 /*
760 * There is no way to know wheter 15-16M hole exists or not.
761 * Therefore, we disable write allocate for this range.
762 */
763 whcr &= ~0x0001LL;
764 #endif
765 wrmsr(0x0c0000082, whcr);
766
767 write_eflags(eflags);
768 }
769
770 void
771 enable_K6_2_wt_alloc(void)
772 {
773 quad_t size;
774 u_int64_t whcr;
775 u_long eflags;
776
777 eflags = read_eflags();
778 disable_intr();
779 wbinvd();
780
781 #ifdef CPU_DISABLE_CACHE
782 /*
783 * Certain K6-2 box becomes unstable when write allocation is
784 * enabled.
785 */
786 /*
787 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
788 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
789 * All other bits in TR12 have no effect on the processer's operation.
790 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
791 * on the AMD-K6.
792 */
793 wrmsr(0x0000000e, (u_int64_t)0x0008);
794 #endif
795 /* Don't assume that memory size is aligned with 4M. */
796 if (Maxmem > 0)
797 size = ((Maxmem >> 8) + 3) >> 2;
798 else
799 size = 0;
800
801 /* Limit is 4092M bytes. */
802 if (size > 0x3fff)
803 size = 0x3ff;
804 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
805
806 #if defined(PC98) || defined(NO_MEMORY_HOLE)
807 if (whcr & (0x3ffLL << 22)) {
808 #ifdef PC98
809 /*
810 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
811 * 15-16M range.
812 */
813 if (!(inb(0x43b) & 4))
814 whcr &= ~(1LL << 16);
815 else
816 #endif
817 whcr |= 1LL << 16;
818 }
819 #else
820 /*
821 * There is no way to know wheter 15-16M hole exists or not.
822 * Therefore, we disable write allocate for this range.
823 */
824 whcr &= ~(1LL << 16);
825 #endif
826 wrmsr(0x0c0000082, whcr);
827
828 write_eflags(eflags);
829 }
830 #endif /* I585_CPU && CPU_WT_ALLOC */
831
832 #include "opt_ddb.h"
833 #ifdef DDB
834 #include <ddb/ddb.h>
835
836 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
837 {
838 u_long eflags;
839 u_int cr0;
840 u_char ccr1, ccr2, ccr3;
841 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
842
843 cr0 = rcr0();
844 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
845 eflags = read_eflags();
846 disable_intr();
847
848
849 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
850 ccr0 = read_cyrix_reg(CCR0);
851 }
852 ccr1 = read_cyrix_reg(CCR1);
853 ccr2 = read_cyrix_reg(CCR2);
854 ccr3 = read_cyrix_reg(CCR3);
855 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
856 write_cyrix_reg(CCR3, CCR3_MAPEN0);
857 ccr4 = read_cyrix_reg(CCR4);
858 if ((cpu == CPU_M1) || (cpu == CPU_M2))
859 ccr5 = read_cyrix_reg(CCR5);
860 else
861 pcr0 = read_cyrix_reg(PCR0);
862 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
863 }
864 write_eflags(eflags);
865
866 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
867 printf("CCR0=%x, ", (u_int)ccr0);
868
869 printf("CCR1=%x, CCR2=%x, CCR3=%x",
870 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
871 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
872 printf(", CCR4=%x, ", (u_int)ccr4);
873 if (cpu == CPU_M1SC)
874 printf("PCR0=%x\n", pcr0);
875 else
876 printf("CCR5=%x\n", ccr5);
877 }
878 }
879 printf("CR0=%x\n", cr0);
880 }
881 #endif /* DDB */
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