1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/6.0/sys/i386/i386/initcpu.c 147741 2005-07-02 20:06:44Z delphij $");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
43
44 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
45 #define CPU_ENABLE_SSE
46 #endif
47
48 void initializecpu(void);
49 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
50 void enable_K5_wt_alloc(void);
51 void enable_K6_wt_alloc(void);
52 void enable_K6_2_wt_alloc(void);
53 #endif
54
55 #ifdef I486_CPU
56 static void init_5x86(void);
57 static void init_bluelightning(void);
58 static void init_486dlc(void);
59 static void init_cy486dx(void);
60 #ifdef CPU_I486_ON_386
61 static void init_i486_on_386(void);
62 #endif
63 static void init_6x86(void);
64 #endif /* I486_CPU */
65
66 #ifdef I686_CPU
67 static void init_6x86MX(void);
68 static void init_ppro(void);
69 static void init_mendocino(void);
70 #endif
71
72 static int hw_instruction_sse;
73 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
74 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
75
76 /* Must *NOT* be BSS or locore will bzero these after setting them */
77 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
78 u_int cpu_feature = 0; /* Feature flags */
79 u_int cpu_feature2 = 0; /* Feature flags */
80 u_int amd_feature = 0; /* Feature flags */
81 u_int cpu_high = 0; /* Highest arg to CPUID */
82 u_int cpu_id = 0; /* Stepping ID */
83 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
84 char cpu_vendor[20] = ""; /* CPU Origin code */
85
86 #ifdef CPU_ENABLE_SSE
87 u_int cpu_fxsr; /* SSE enabled */
88 #endif
89
90 #ifdef I486_CPU
91 /*
92 * IBM Blue Lightning
93 */
94 static void
95 init_bluelightning(void)
96 {
97 u_long eflags;
98
99 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
100 need_post_dma_flush = 1;
101 #endif
102
103 eflags = read_eflags();
104 disable_intr();
105
106 load_cr0(rcr0() | CR0_CD | CR0_NW);
107 invd();
108
109 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
110 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
111 #else
112 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
113 #endif
114 /* Enables 13MB and 0-640KB cache. */
115 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
116 #ifdef CPU_BLUELIGHTNING_3X
117 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
118 #else
119 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
120 #endif
121
122 /* Enable caching in CR0. */
123 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
124 invd();
125 write_eflags(eflags);
126 }
127
128 /*
129 * Cyrix 486SLC/DLC/SR/DR series
130 */
131 static void
132 init_486dlc(void)
133 {
134 u_long eflags;
135 u_char ccr0;
136
137 eflags = read_eflags();
138 disable_intr();
139 invd();
140
141 ccr0 = read_cyrix_reg(CCR0);
142 #ifndef CYRIX_CACHE_WORKS
143 ccr0 |= CCR0_NC1 | CCR0_BARB;
144 write_cyrix_reg(CCR0, ccr0);
145 invd();
146 #else
147 ccr0 &= ~CCR0_NC0;
148 #ifndef CYRIX_CACHE_REALLY_WORKS
149 ccr0 |= CCR0_NC1 | CCR0_BARB;
150 #else
151 ccr0 |= CCR0_NC1;
152 #endif
153 #ifdef CPU_DIRECT_MAPPED_CACHE
154 ccr0 |= CCR0_CO; /* Direct mapped mode. */
155 #endif
156 write_cyrix_reg(CCR0, ccr0);
157
158 /* Clear non-cacheable region. */
159 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
160 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
161 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
162 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
163
164 write_cyrix_reg(0, 0); /* dummy write */
165
166 /* Enable caching in CR0. */
167 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
168 invd();
169 #endif /* !CYRIX_CACHE_WORKS */
170 write_eflags(eflags);
171 }
172
173
174 /*
175 * Cyrix 486S/DX series
176 */
177 static void
178 init_cy486dx(void)
179 {
180 u_long eflags;
181 u_char ccr2;
182
183 eflags = read_eflags();
184 disable_intr();
185 invd();
186
187 ccr2 = read_cyrix_reg(CCR2);
188 #ifdef CPU_SUSP_HLT
189 ccr2 |= CCR2_SUSP_HLT;
190 #endif
191
192 #ifdef PC98
193 /* Enables WB cache interface pin and Lock NW bit in CR0. */
194 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
195 /* Unlock NW bit in CR0. */
196 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
197 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
198 #endif
199
200 write_cyrix_reg(CCR2, ccr2);
201 write_eflags(eflags);
202 }
203
204
205 /*
206 * Cyrix 5x86
207 */
208 static void
209 init_5x86(void)
210 {
211 u_long eflags;
212 u_char ccr2, ccr3, ccr4, pcr0;
213
214 eflags = read_eflags();
215 disable_intr();
216
217 load_cr0(rcr0() | CR0_CD | CR0_NW);
218 wbinvd();
219
220 (void)read_cyrix_reg(CCR3); /* dummy */
221
222 /* Initialize CCR2. */
223 ccr2 = read_cyrix_reg(CCR2);
224 ccr2 |= CCR2_WB;
225 #ifdef CPU_SUSP_HLT
226 ccr2 |= CCR2_SUSP_HLT;
227 #else
228 ccr2 &= ~CCR2_SUSP_HLT;
229 #endif
230 ccr2 |= CCR2_WT1;
231 write_cyrix_reg(CCR2, ccr2);
232
233 /* Initialize CCR4. */
234 ccr3 = read_cyrix_reg(CCR3);
235 write_cyrix_reg(CCR3, CCR3_MAPEN0);
236
237 ccr4 = read_cyrix_reg(CCR4);
238 ccr4 |= CCR4_DTE;
239 ccr4 |= CCR4_MEM;
240 #ifdef CPU_FASTER_5X86_FPU
241 ccr4 |= CCR4_FASTFPE;
242 #else
243 ccr4 &= ~CCR4_FASTFPE;
244 #endif
245 ccr4 &= ~CCR4_IOMASK;
246 /********************************************************************
247 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
248 * should be 0 for errata fix.
249 ********************************************************************/
250 #ifdef CPU_IORT
251 ccr4 |= CPU_IORT & CCR4_IOMASK;
252 #endif
253 write_cyrix_reg(CCR4, ccr4);
254
255 /* Initialize PCR0. */
256 /****************************************************************
257 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
258 * BTB_EN might make your system unstable.
259 ****************************************************************/
260 pcr0 = read_cyrix_reg(PCR0);
261 #ifdef CPU_RSTK_EN
262 pcr0 |= PCR0_RSTK;
263 #else
264 pcr0 &= ~PCR0_RSTK;
265 #endif
266 #ifdef CPU_BTB_EN
267 pcr0 |= PCR0_BTB;
268 #else
269 pcr0 &= ~PCR0_BTB;
270 #endif
271 #ifdef CPU_LOOP_EN
272 pcr0 |= PCR0_LOOP;
273 #else
274 pcr0 &= ~PCR0_LOOP;
275 #endif
276
277 /****************************************************************
278 * WARNING: if you use a memory mapped I/O device, don't use
279 * DISABLE_5X86_LSSER option, which may reorder memory mapped
280 * I/O access.
281 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
282 ****************************************************************/
283 #ifdef CPU_DISABLE_5X86_LSSER
284 pcr0 &= ~PCR0_LSSER;
285 #else
286 pcr0 |= PCR0_LSSER;
287 #endif
288 write_cyrix_reg(PCR0, pcr0);
289
290 /* Restore CCR3. */
291 write_cyrix_reg(CCR3, ccr3);
292
293 (void)read_cyrix_reg(0x80); /* dummy */
294
295 /* Unlock NW bit in CR0. */
296 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
297 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
298 /* Lock NW bit in CR0. */
299 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
300
301 write_eflags(eflags);
302 }
303
304 #ifdef CPU_I486_ON_386
305 /*
306 * There are i486 based upgrade products for i386 machines.
307 * In this case, BIOS doesn't enables CPU cache.
308 */
309 static void
310 init_i486_on_386(void)
311 {
312 u_long eflags;
313
314 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
315 need_post_dma_flush = 1;
316 #endif
317
318 eflags = read_eflags();
319 disable_intr();
320
321 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
322
323 write_eflags(eflags);
324 }
325 #endif
326
327 /*
328 * Cyrix 6x86
329 *
330 * XXX - What should I do here? Please let me know.
331 */
332 static void
333 init_6x86(void)
334 {
335 u_long eflags;
336 u_char ccr3, ccr4;
337
338 eflags = read_eflags();
339 disable_intr();
340
341 load_cr0(rcr0() | CR0_CD | CR0_NW);
342 wbinvd();
343
344 /* Initialize CCR0. */
345 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
346
347 /* Initialize CCR1. */
348 #ifdef CPU_CYRIX_NO_LOCK
349 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
350 #else
351 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
352 #endif
353
354 /* Initialize CCR2. */
355 #ifdef CPU_SUSP_HLT
356 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
357 #else
358 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
359 #endif
360
361 ccr3 = read_cyrix_reg(CCR3);
362 write_cyrix_reg(CCR3, CCR3_MAPEN0);
363
364 /* Initialize CCR4. */
365 ccr4 = read_cyrix_reg(CCR4);
366 ccr4 |= CCR4_DTE;
367 ccr4 &= ~CCR4_IOMASK;
368 #ifdef CPU_IORT
369 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
370 #else
371 write_cyrix_reg(CCR4, ccr4 | 7);
372 #endif
373
374 /* Initialize CCR5. */
375 #ifdef CPU_WT_ALLOC
376 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
377 #endif
378
379 /* Restore CCR3. */
380 write_cyrix_reg(CCR3, ccr3);
381
382 /* Unlock NW bit in CR0. */
383 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
384
385 /*
386 * Earlier revision of the 6x86 CPU could crash the system if
387 * L1 cache is in write-back mode.
388 */
389 if ((cyrix_did & 0xff00) > 0x1600)
390 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
391 else {
392 /* Revision 2.6 and lower. */
393 #ifdef CYRIX_CACHE_REALLY_WORKS
394 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
395 #else
396 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
397 #endif
398 }
399
400 /* Lock NW bit in CR0. */
401 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
402
403 write_eflags(eflags);
404 }
405 #endif /* I486_CPU */
406
407 #ifdef I686_CPU
408 /*
409 * Cyrix 6x86MX (code-named M2)
410 *
411 * XXX - What should I do here? Please let me know.
412 */
413 static void
414 init_6x86MX(void)
415 {
416 u_long eflags;
417 u_char ccr3, ccr4;
418
419 eflags = read_eflags();
420 disable_intr();
421
422 load_cr0(rcr0() | CR0_CD | CR0_NW);
423 wbinvd();
424
425 /* Initialize CCR0. */
426 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
427
428 /* Initialize CCR1. */
429 #ifdef CPU_CYRIX_NO_LOCK
430 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
431 #else
432 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
433 #endif
434
435 /* Initialize CCR2. */
436 #ifdef CPU_SUSP_HLT
437 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
438 #else
439 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
440 #endif
441
442 ccr3 = read_cyrix_reg(CCR3);
443 write_cyrix_reg(CCR3, CCR3_MAPEN0);
444
445 /* Initialize CCR4. */
446 ccr4 = read_cyrix_reg(CCR4);
447 ccr4 &= ~CCR4_IOMASK;
448 #ifdef CPU_IORT
449 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
450 #else
451 write_cyrix_reg(CCR4, ccr4 | 7);
452 #endif
453
454 /* Initialize CCR5. */
455 #ifdef CPU_WT_ALLOC
456 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
457 #endif
458
459 /* Restore CCR3. */
460 write_cyrix_reg(CCR3, ccr3);
461
462 /* Unlock NW bit in CR0. */
463 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
464
465 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
466
467 /* Lock NW bit in CR0. */
468 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
469
470 write_eflags(eflags);
471 }
472
473 static void
474 init_ppro(void)
475 {
476 u_int64_t apicbase;
477
478 /*
479 * Local APIC should be disabled if it is not going to be used.
480 */
481 apicbase = rdmsr(MSR_APICBASE);
482 apicbase &= ~APICBASE_ENABLED;
483 wrmsr(MSR_APICBASE, apicbase);
484 }
485
486 /*
487 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
488 * L2 cache).
489 */
490 static void
491 init_mendocino(void)
492 {
493 #ifdef CPU_PPRO2CELERON
494 u_long eflags;
495 u_int64_t bbl_cr_ctl3;
496
497 eflags = read_eflags();
498 disable_intr();
499
500 load_cr0(rcr0() | CR0_CD | CR0_NW);
501 wbinvd();
502
503 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
504
505 /* If the L2 cache is configured, do nothing. */
506 if (!(bbl_cr_ctl3 & 1)) {
507 bbl_cr_ctl3 = 0x134052bLL;
508
509 /* Set L2 Cache Latency (Default: 5). */
510 #ifdef CPU_CELERON_L2_LATENCY
511 #if CPU_L2_LATENCY > 15
512 #error invalid CPU_L2_LATENCY.
513 #endif
514 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
515 #else
516 bbl_cr_ctl3 |= 5 << 1;
517 #endif
518 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
519 }
520
521 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
522 write_eflags(eflags);
523 #endif /* CPU_PPRO2CELERON */
524 }
525
526 #endif /* I686_CPU */
527
528 /*
529 * Initialize CR4 (Control register 4) to enable SSE instructions.
530 */
531 void
532 enable_sse(void)
533 {
534 #if defined(CPU_ENABLE_SSE)
535 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
536 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
537 cpu_fxsr = hw_instruction_sse = 1;
538 }
539 #endif
540 }
541
542 void
543 initializecpu(void)
544 {
545
546 switch (cpu) {
547 #ifdef I486_CPU
548 case CPU_BLUE:
549 init_bluelightning();
550 break;
551 case CPU_486DLC:
552 init_486dlc();
553 break;
554 case CPU_CY486DX:
555 init_cy486dx();
556 break;
557 case CPU_M1SC:
558 init_5x86();
559 break;
560 #ifdef CPU_I486_ON_386
561 case CPU_486:
562 init_i486_on_386();
563 break;
564 #endif
565 case CPU_M1:
566 init_6x86();
567 break;
568 #endif /* I486_CPU */
569 #ifdef I686_CPU
570 case CPU_M2:
571 init_6x86MX();
572 break;
573 case CPU_686:
574 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
575 switch (cpu_id & 0xff0) {
576 case 0x610:
577 init_ppro();
578 break;
579 case 0x660:
580 init_mendocino();
581 break;
582 }
583 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
584 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
585 /*
586 * Sometimes the BIOS doesn't enable SSE instructions.
587 * According to AMD document 20734, the mobile
588 * Duron, the (mobile) Athlon 4 and the Athlon MP
589 * support SSE. These correspond to cpu_id 0x66X
590 * or 0x67X.
591 */
592 if ((cpu_feature & CPUID_XMM) == 0 &&
593 ((cpu_id & ~0xf) == 0x660 ||
594 (cpu_id & ~0xf) == 0x670 ||
595 (cpu_id & ~0xf) == 0x680)) {
596 u_int regs[4];
597 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
598 do_cpuid(1, regs);
599 cpu_feature = regs[3];
600 }
601 #endif
602 }
603 break;
604 #endif
605 default:
606 break;
607 }
608 enable_sse();
609
610 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
611 /*
612 * OS should flush L1 cache by itself because no PC-98 supports
613 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
614 * when need_pre_dma_flush = 1, use invd instruction after DMA
615 * transfer when need_post_dma_flush = 1. If your CPU upgrade
616 * product supports hardware cache control, you can add the
617 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
618 * This option eliminates unneeded cache flush instruction(s).
619 */
620 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
621 switch (cpu) {
622 #ifdef I486_CPU
623 case CPU_486DLC:
624 need_post_dma_flush = 1;
625 break;
626 case CPU_M1SC:
627 need_pre_dma_flush = 1;
628 break;
629 case CPU_CY486DX:
630 need_pre_dma_flush = 1;
631 #ifdef CPU_I486_ON_386
632 need_post_dma_flush = 1;
633 #endif
634 break;
635 #endif
636 default:
637 break;
638 }
639 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
640 switch (cpu_id & 0xFF0) {
641 case 0x470: /* Enhanced Am486DX2 WB */
642 case 0x490: /* Enhanced Am486DX4 WB */
643 case 0x4F0: /* Am5x86 WB */
644 need_pre_dma_flush = 1;
645 break;
646 }
647 } else if (strcmp(cpu_vendor, "IBM") == 0) {
648 need_post_dma_flush = 1;
649 } else {
650 #ifdef CPU_I486_ON_386
651 need_pre_dma_flush = 1;
652 #endif
653 }
654 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
655 }
656
657 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
658 /*
659 * Enable write allocate feature of AMD processors.
660 * Following two functions require the Maxmem variable being set.
661 */
662 void
663 enable_K5_wt_alloc(void)
664 {
665 u_int64_t msr;
666 register_t savecrit;
667
668 /*
669 * Write allocate is supported only on models 1, 2, and 3, with
670 * a stepping of 4 or greater.
671 */
672 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
673 savecrit = intr_disable();
674 msr = rdmsr(0x83); /* HWCR */
675 wrmsr(0x83, msr & !(0x10));
676
677 /*
678 * We have to tell the chip where the top of memory is,
679 * since video cards could have frame bufferes there,
680 * memory-mapped I/O could be there, etc.
681 */
682 if(Maxmem > 0)
683 msr = Maxmem / 16;
684 else
685 msr = 0;
686 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
687 #ifdef PC98
688 if (!(inb(0x43b) & 4)) {
689 wrmsr(0x86, 0x0ff00f0);
690 msr |= AMD_WT_ALLOC_PRE;
691 }
692 #else
693 /*
694 * There is no way to know wheter 15-16M hole exists or not.
695 * Therefore, we disable write allocate for this range.
696 */
697 wrmsr(0x86, 0x0ff00f0);
698 msr |= AMD_WT_ALLOC_PRE;
699 #endif
700 wrmsr(0x85, msr);
701
702 msr=rdmsr(0x83);
703 wrmsr(0x83, msr|0x10); /* enable write allocate */
704 intr_restore(savecrit);
705 }
706 }
707
708 void
709 enable_K6_wt_alloc(void)
710 {
711 quad_t size;
712 u_int64_t whcr;
713 u_long eflags;
714
715 eflags = read_eflags();
716 disable_intr();
717 wbinvd();
718
719 #ifdef CPU_DISABLE_CACHE
720 /*
721 * Certain K6-2 box becomes unstable when write allocation is
722 * enabled.
723 */
724 /*
725 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
726 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
727 * All other bits in TR12 have no effect on the processer's operation.
728 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
729 * on the AMD-K6.
730 */
731 wrmsr(0x0000000e, (u_int64_t)0x0008);
732 #endif
733 /* Don't assume that memory size is aligned with 4M. */
734 if (Maxmem > 0)
735 size = ((Maxmem >> 8) + 3) >> 2;
736 else
737 size = 0;
738
739 /* Limit is 508M bytes. */
740 if (size > 0x7f)
741 size = 0x7f;
742 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
743
744 #if defined(PC98) || defined(NO_MEMORY_HOLE)
745 if (whcr & (0x7fLL << 1)) {
746 #ifdef PC98
747 /*
748 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
749 * 15-16M range.
750 */
751 if (!(inb(0x43b) & 4))
752 whcr &= ~0x0001LL;
753 else
754 #endif
755 whcr |= 0x0001LL;
756 }
757 #else
758 /*
759 * There is no way to know wheter 15-16M hole exists or not.
760 * Therefore, we disable write allocate for this range.
761 */
762 whcr &= ~0x0001LL;
763 #endif
764 wrmsr(0x0c0000082, whcr);
765
766 write_eflags(eflags);
767 }
768
769 void
770 enable_K6_2_wt_alloc(void)
771 {
772 quad_t size;
773 u_int64_t whcr;
774 u_long eflags;
775
776 eflags = read_eflags();
777 disable_intr();
778 wbinvd();
779
780 #ifdef CPU_DISABLE_CACHE
781 /*
782 * Certain K6-2 box becomes unstable when write allocation is
783 * enabled.
784 */
785 /*
786 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
787 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
788 * All other bits in TR12 have no effect on the processer's operation.
789 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
790 * on the AMD-K6.
791 */
792 wrmsr(0x0000000e, (u_int64_t)0x0008);
793 #endif
794 /* Don't assume that memory size is aligned with 4M. */
795 if (Maxmem > 0)
796 size = ((Maxmem >> 8) + 3) >> 2;
797 else
798 size = 0;
799
800 /* Limit is 4092M bytes. */
801 if (size > 0x3fff)
802 size = 0x3ff;
803 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
804
805 #if defined(PC98) || defined(NO_MEMORY_HOLE)
806 if (whcr & (0x3ffLL << 22)) {
807 #ifdef PC98
808 /*
809 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
810 * 15-16M range.
811 */
812 if (!(inb(0x43b) & 4))
813 whcr &= ~(1LL << 16);
814 else
815 #endif
816 whcr |= 1LL << 16;
817 }
818 #else
819 /*
820 * There is no way to know wheter 15-16M hole exists or not.
821 * Therefore, we disable write allocate for this range.
822 */
823 whcr &= ~(1LL << 16);
824 #endif
825 wrmsr(0x0c0000082, whcr);
826
827 write_eflags(eflags);
828 }
829 #endif /* I585_CPU && CPU_WT_ALLOC */
830
831 #include "opt_ddb.h"
832 #ifdef DDB
833 #include <ddb/ddb.h>
834
835 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
836 {
837 u_long eflags;
838 u_int cr0;
839 u_char ccr1, ccr2, ccr3;
840 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
841
842 cr0 = rcr0();
843 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
844 eflags = read_eflags();
845 disable_intr();
846
847
848 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
849 ccr0 = read_cyrix_reg(CCR0);
850 }
851 ccr1 = read_cyrix_reg(CCR1);
852 ccr2 = read_cyrix_reg(CCR2);
853 ccr3 = read_cyrix_reg(CCR3);
854 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
855 write_cyrix_reg(CCR3, CCR3_MAPEN0);
856 ccr4 = read_cyrix_reg(CCR4);
857 if ((cpu == CPU_M1) || (cpu == CPU_M2))
858 ccr5 = read_cyrix_reg(CCR5);
859 else
860 pcr0 = read_cyrix_reg(PCR0);
861 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
862 }
863 write_eflags(eflags);
864
865 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
866 printf("CCR0=%x, ", (u_int)ccr0);
867
868 printf("CCR1=%x, CCR2=%x, CCR3=%x",
869 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
870 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
871 printf(", CCR4=%x, ", (u_int)ccr4);
872 if (cpu == CPU_M1SC)
873 printf("PCR0=%x\n", pcr0);
874 else
875 printf("CCR5=%x\n", ccr5);
876 }
877 }
878 printf("CR0=%x\n", cr0);
879 }
880 #endif /* DDB */
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