The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/initcpu.c

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    1 /*-
    2  * Copyright (c) KATO Takenori, 1997, 1998.
    3  * 
    4  * All rights reserved.  Unpublished rights reserved under the copyright
    5  * laws of Japan.
    6  * 
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer as
   13  *    the first lines of this file unmodified.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD$");
   32 
   33 #include "opt_cpu.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/kernel.h>
   37 #include <sys/systm.h>
   38 #include <sys/sysctl.h>
   39 
   40 #include <machine/cputypes.h>
   41 #include <machine/md_var.h>
   42 #include <machine/specialreg.h>
   43 
   44 #include <vm/vm.h>
   45 #include <vm/pmap.h>
   46 
   47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
   48 #define CPU_ENABLE_SSE
   49 #endif
   50 
   51 void initializecpu(void);
   52 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   53 void    enable_K5_wt_alloc(void);
   54 void    enable_K6_wt_alloc(void);
   55 void    enable_K6_2_wt_alloc(void);
   56 #endif
   57 
   58 #ifdef I486_CPU
   59 static void init_5x86(void);
   60 static void init_bluelightning(void);
   61 static void init_486dlc(void);
   62 static void init_cy486dx(void);
   63 #ifdef CPU_I486_ON_386
   64 static void init_i486_on_386(void);
   65 #endif
   66 static void init_6x86(void);
   67 #endif /* I486_CPU */
   68 
   69 #ifdef I686_CPU
   70 static void     init_6x86MX(void);
   71 static void     init_ppro(void);
   72 static void     init_mendocino(void);
   73 #endif
   74 
   75 static int      hw_instruction_sse;
   76 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
   77     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
   78 
   79 /* Must *NOT* be BSS or locore will bzero these after setting them */
   80 int     cpu = 0;                /* Are we 386, 386sx, 486, etc? */
   81 u_int   cpu_feature = 0;        /* Feature flags */
   82 u_int   cpu_feature2 = 0;       /* Feature flags */
   83 u_int   amd_feature = 0;        /* AMD feature flags */
   84 u_int   amd_feature2 = 0;       /* AMD feature flags */
   85 u_int   via_feature_rng = 0;    /* VIA RNG features */
   86 u_int   via_feature_xcrypt = 0; /* VIA ACE features */
   87 u_int   cpu_high = 0;           /* Highest arg to CPUID */
   88 u_int   cpu_id = 0;             /* Stepping ID */
   89 u_int   cpu_procinfo = 0;       /* HyperThreading Info / Brand Index / CLFUSH */
   90 u_int   cpu_procinfo2 = 0;      /* Multicore info */
   91 char    cpu_vendor[20] = "";    /* CPU Origin code */
   92 
   93 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
   94         &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
   95 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
   96         &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
   97 
   98 #ifdef CPU_ENABLE_SSE
   99 u_int   cpu_fxsr;               /* SSE enabled */
  100 u_int   cpu_mxcsr_mask;         /* valid bits in mxcsr */
  101 #endif
  102 
  103 #ifdef I486_CPU
  104 /*
  105  * IBM Blue Lightning
  106  */
  107 static void
  108 init_bluelightning(void)
  109 {
  110         u_long  eflags;
  111 
  112 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  113         need_post_dma_flush = 1;
  114 #endif
  115 
  116         eflags = read_eflags();
  117         disable_intr();
  118 
  119         load_cr0(rcr0() | CR0_CD | CR0_NW);
  120         invd();
  121 
  122 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
  123         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
  124 #else
  125         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
  126 #endif
  127         /* Enables 13MB and 0-640KB cache. */
  128         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
  129 #ifdef CPU_BLUELIGHTNING_3X
  130         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
  131 #else
  132         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
  133 #endif
  134 
  135         /* Enable caching in CR0. */
  136         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  137         invd();
  138         write_eflags(eflags);
  139 }
  140 
  141 /*
  142  * Cyrix 486SLC/DLC/SR/DR series
  143  */
  144 static void
  145 init_486dlc(void)
  146 {
  147         u_long  eflags;
  148         u_char  ccr0;
  149 
  150         eflags = read_eflags();
  151         disable_intr();
  152         invd();
  153 
  154         ccr0 = read_cyrix_reg(CCR0);
  155 #ifndef CYRIX_CACHE_WORKS
  156         ccr0 |= CCR0_NC1 | CCR0_BARB;
  157         write_cyrix_reg(CCR0, ccr0);
  158         invd();
  159 #else
  160         ccr0 &= ~CCR0_NC0;
  161 #ifndef CYRIX_CACHE_REALLY_WORKS
  162         ccr0 |= CCR0_NC1 | CCR0_BARB;
  163 #else
  164         ccr0 |= CCR0_NC1;
  165 #endif
  166 #ifdef CPU_DIRECT_MAPPED_CACHE
  167         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
  168 #endif
  169         write_cyrix_reg(CCR0, ccr0);
  170 
  171         /* Clear non-cacheable region. */
  172         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
  173         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
  174         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
  175         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
  176 
  177         write_cyrix_reg(0, 0);  /* dummy write */
  178 
  179         /* Enable caching in CR0. */
  180         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  181         invd();
  182 #endif /* !CYRIX_CACHE_WORKS */
  183         write_eflags(eflags);
  184 }
  185 
  186 
  187 /*
  188  * Cyrix 486S/DX series
  189  */
  190 static void
  191 init_cy486dx(void)
  192 {
  193         u_long  eflags;
  194         u_char  ccr2;
  195 
  196         eflags = read_eflags();
  197         disable_intr();
  198         invd();
  199 
  200         ccr2 = read_cyrix_reg(CCR2);
  201 #ifdef CPU_SUSP_HLT
  202         ccr2 |= CCR2_SUSP_HLT;
  203 #endif
  204 
  205 #ifdef PC98
  206         /* Enables WB cache interface pin and Lock NW bit in CR0. */
  207         ccr2 |= CCR2_WB | CCR2_LOCK_NW;
  208         /* Unlock NW bit in CR0. */
  209         write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
  210         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
  211 #endif
  212 
  213         write_cyrix_reg(CCR2, ccr2);
  214         write_eflags(eflags);
  215 }
  216 
  217 
  218 /*
  219  * Cyrix 5x86
  220  */
  221 static void
  222 init_5x86(void)
  223 {
  224         u_long  eflags;
  225         u_char  ccr2, ccr3, ccr4, pcr0;
  226 
  227         eflags = read_eflags();
  228         disable_intr();
  229 
  230         load_cr0(rcr0() | CR0_CD | CR0_NW);
  231         wbinvd();
  232 
  233         (void)read_cyrix_reg(CCR3);             /* dummy */
  234 
  235         /* Initialize CCR2. */
  236         ccr2 = read_cyrix_reg(CCR2);
  237         ccr2 |= CCR2_WB;
  238 #ifdef CPU_SUSP_HLT
  239         ccr2 |= CCR2_SUSP_HLT;
  240 #else
  241         ccr2 &= ~CCR2_SUSP_HLT;
  242 #endif
  243         ccr2 |= CCR2_WT1;
  244         write_cyrix_reg(CCR2, ccr2);
  245 
  246         /* Initialize CCR4. */
  247         ccr3 = read_cyrix_reg(CCR3);
  248         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  249 
  250         ccr4 = read_cyrix_reg(CCR4);
  251         ccr4 |= CCR4_DTE;
  252         ccr4 |= CCR4_MEM;
  253 #ifdef CPU_FASTER_5X86_FPU
  254         ccr4 |= CCR4_FASTFPE;
  255 #else
  256         ccr4 &= ~CCR4_FASTFPE;
  257 #endif
  258         ccr4 &= ~CCR4_IOMASK;
  259         /********************************************************************
  260          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
  261          * should be 0 for errata fix.
  262          ********************************************************************/
  263 #ifdef CPU_IORT
  264         ccr4 |= CPU_IORT & CCR4_IOMASK;
  265 #endif
  266         write_cyrix_reg(CCR4, ccr4);
  267 
  268         /* Initialize PCR0. */
  269         /****************************************************************
  270          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
  271          * BTB_EN might make your system unstable.
  272          ****************************************************************/
  273         pcr0 = read_cyrix_reg(PCR0);
  274 #ifdef CPU_RSTK_EN
  275         pcr0 |= PCR0_RSTK;
  276 #else
  277         pcr0 &= ~PCR0_RSTK;
  278 #endif
  279 #ifdef CPU_BTB_EN
  280         pcr0 |= PCR0_BTB;
  281 #else
  282         pcr0 &= ~PCR0_BTB;
  283 #endif
  284 #ifdef CPU_LOOP_EN
  285         pcr0 |= PCR0_LOOP;
  286 #else
  287         pcr0 &= ~PCR0_LOOP;
  288 #endif
  289 
  290         /****************************************************************
  291          * WARNING: if you use a memory mapped I/O device, don't use
  292          * DISABLE_5X86_LSSER option, which may reorder memory mapped
  293          * I/O access.
  294          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
  295          ****************************************************************/
  296 #ifdef CPU_DISABLE_5X86_LSSER
  297         pcr0 &= ~PCR0_LSSER;
  298 #else
  299         pcr0 |= PCR0_LSSER;
  300 #endif
  301         write_cyrix_reg(PCR0, pcr0);
  302 
  303         /* Restore CCR3. */
  304         write_cyrix_reg(CCR3, ccr3);
  305 
  306         (void)read_cyrix_reg(0x80);             /* dummy */
  307 
  308         /* Unlock NW bit in CR0. */
  309         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  310         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
  311         /* Lock NW bit in CR0. */
  312         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  313 
  314         write_eflags(eflags);
  315 }
  316 
  317 #ifdef CPU_I486_ON_386
  318 /*
  319  * There are i486 based upgrade products for i386 machines.
  320  * In this case, BIOS doesn't enables CPU cache.
  321  */
  322 static void
  323 init_i486_on_386(void)
  324 {
  325         u_long  eflags;
  326 
  327 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  328         need_post_dma_flush = 1;
  329 #endif
  330 
  331         eflags = read_eflags();
  332         disable_intr();
  333 
  334         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
  335 
  336         write_eflags(eflags);
  337 }
  338 #endif
  339 
  340 /*
  341  * Cyrix 6x86
  342  *
  343  * XXX - What should I do here?  Please let me know.
  344  */
  345 static void
  346 init_6x86(void)
  347 {
  348         u_long  eflags;
  349         u_char  ccr3, ccr4;
  350 
  351         eflags = read_eflags();
  352         disable_intr();
  353 
  354         load_cr0(rcr0() | CR0_CD | CR0_NW);
  355         wbinvd();
  356 
  357         /* Initialize CCR0. */
  358         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  359 
  360         /* Initialize CCR1. */
  361 #ifdef CPU_CYRIX_NO_LOCK
  362         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  363 #else
  364         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  365 #endif
  366 
  367         /* Initialize CCR2. */
  368 #ifdef CPU_SUSP_HLT
  369         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  370 #else
  371         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  372 #endif
  373 
  374         ccr3 = read_cyrix_reg(CCR3);
  375         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  376 
  377         /* Initialize CCR4. */
  378         ccr4 = read_cyrix_reg(CCR4);
  379         ccr4 |= CCR4_DTE;
  380         ccr4 &= ~CCR4_IOMASK;
  381 #ifdef CPU_IORT
  382         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  383 #else
  384         write_cyrix_reg(CCR4, ccr4 | 7);
  385 #endif
  386 
  387         /* Initialize CCR5. */
  388 #ifdef CPU_WT_ALLOC
  389         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  390 #endif
  391 
  392         /* Restore CCR3. */
  393         write_cyrix_reg(CCR3, ccr3);
  394 
  395         /* Unlock NW bit in CR0. */
  396         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  397 
  398         /*
  399          * Earlier revision of the 6x86 CPU could crash the system if
  400          * L1 cache is in write-back mode.
  401          */
  402         if ((cyrix_did & 0xff00) > 0x1600)
  403                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  404         else {
  405                 /* Revision 2.6 and lower. */
  406 #ifdef CYRIX_CACHE_REALLY_WORKS
  407                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  408 #else
  409                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
  410 #endif
  411         }
  412 
  413         /* Lock NW bit in CR0. */
  414         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  415 
  416         write_eflags(eflags);
  417 }
  418 #endif /* I486_CPU */
  419 
  420 #ifdef I686_CPU
  421 /*
  422  * Cyrix 6x86MX (code-named M2)
  423  *
  424  * XXX - What should I do here?  Please let me know.
  425  */
  426 static void
  427 init_6x86MX(void)
  428 {
  429         u_long  eflags;
  430         u_char  ccr3, ccr4;
  431 
  432         eflags = read_eflags();
  433         disable_intr();
  434 
  435         load_cr0(rcr0() | CR0_CD | CR0_NW);
  436         wbinvd();
  437 
  438         /* Initialize CCR0. */
  439         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  440 
  441         /* Initialize CCR1. */
  442 #ifdef CPU_CYRIX_NO_LOCK
  443         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  444 #else
  445         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  446 #endif
  447 
  448         /* Initialize CCR2. */
  449 #ifdef CPU_SUSP_HLT
  450         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  451 #else
  452         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  453 #endif
  454 
  455         ccr3 = read_cyrix_reg(CCR3);
  456         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  457 
  458         /* Initialize CCR4. */
  459         ccr4 = read_cyrix_reg(CCR4);
  460         ccr4 &= ~CCR4_IOMASK;
  461 #ifdef CPU_IORT
  462         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  463 #else
  464         write_cyrix_reg(CCR4, ccr4 | 7);
  465 #endif
  466 
  467         /* Initialize CCR5. */
  468 #ifdef CPU_WT_ALLOC
  469         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  470 #endif
  471 
  472         /* Restore CCR3. */
  473         write_cyrix_reg(CCR3, ccr3);
  474 
  475         /* Unlock NW bit in CR0. */
  476         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  477 
  478         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  479 
  480         /* Lock NW bit in CR0. */
  481         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  482 
  483         write_eflags(eflags);
  484 }
  485 
  486 static void
  487 init_ppro(void)
  488 {
  489         u_int64_t       apicbase;
  490 
  491         /*
  492          * Local APIC should be disabled if it is not going to be used.
  493          */
  494         apicbase = rdmsr(MSR_APICBASE);
  495         apicbase &= ~APICBASE_ENABLED;
  496         wrmsr(MSR_APICBASE, apicbase);
  497 }
  498 
  499 /*
  500  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
  501  * L2 cache).
  502  */
  503 static void
  504 init_mendocino(void)
  505 {
  506 #ifdef CPU_PPRO2CELERON
  507         u_long  eflags;
  508         u_int64_t       bbl_cr_ctl3;
  509 
  510         eflags = read_eflags();
  511         disable_intr();
  512 
  513         load_cr0(rcr0() | CR0_CD | CR0_NW);
  514         wbinvd();
  515 
  516         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
  517 
  518         /* If the L2 cache is configured, do nothing. */
  519         if (!(bbl_cr_ctl3 & 1)) {
  520                 bbl_cr_ctl3 = 0x134052bLL;
  521 
  522                 /* Set L2 Cache Latency (Default: 5). */
  523 #ifdef  CPU_CELERON_L2_LATENCY
  524 #if CPU_L2_LATENCY > 15
  525 #error invalid CPU_L2_LATENCY.
  526 #endif
  527                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
  528 #else
  529                 bbl_cr_ctl3 |= 5 << 1;
  530 #endif
  531                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
  532         }
  533 
  534         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
  535         write_eflags(eflags);
  536 #endif /* CPU_PPRO2CELERON */
  537 }
  538 
  539 /*
  540  * Initialize special VIA C3/C7 features
  541  */
  542 static void
  543 init_via(void)
  544 {
  545         u_int regs[4], val;
  546         u_int64_t msreg;
  547 
  548         do_cpuid(0xc0000000, regs);
  549         val = regs[0];
  550         if (val >= 0xc0000001) {
  551                 do_cpuid(0xc0000001, regs);
  552                 val = regs[3];
  553         } else
  554                 val = 0;
  555 
  556         /* Enable RNG if present and disabled */
  557         if (val & VIA_CPUID_HAS_RNG) {
  558                 if (!(val & VIA_CPUID_DO_RNG)) {
  559                         msreg = rdmsr(0x110B);
  560                         msreg |= 0x40;
  561                         wrmsr(0x110B, msreg);
  562                 }
  563                 via_feature_rng = VIA_HAS_RNG;
  564         }
  565         /* Enable AES engine if present and disabled */
  566         if (val & VIA_CPUID_HAS_ACE) {
  567                 if (!(val & VIA_CPUID_DO_ACE)) {
  568                         msreg = rdmsr(0x1107);
  569                         msreg |= (0x01 << 28);
  570                         wrmsr(0x1107, msreg);
  571                 }
  572                 via_feature_xcrypt |= VIA_HAS_AES;
  573         }
  574         /* Enable ACE2 engine if present and disabled */
  575         if (val & VIA_CPUID_HAS_ACE2) {
  576                 if (!(val & VIA_CPUID_DO_ACE2)) {
  577                         msreg = rdmsr(0x1107);
  578                         msreg |= (0x01 << 28);
  579                         wrmsr(0x1107, msreg);
  580                 }
  581                 via_feature_xcrypt |= VIA_HAS_AESCTR;
  582         }
  583         /* Enable SHA engine if present and disabled */
  584         if (val & VIA_CPUID_HAS_PHE) {
  585                 if (!(val & VIA_CPUID_DO_PHE)) {
  586                         msreg = rdmsr(0x1107);
  587                         msreg |= (0x01 << 28/**/);
  588                         wrmsr(0x1107, msreg);
  589                 }
  590                 via_feature_xcrypt |= VIA_HAS_SHA;
  591         }
  592         /* Enable MM engine if present and disabled */
  593         if (val & VIA_CPUID_HAS_PMM) {
  594                 if (!(val & VIA_CPUID_DO_PMM)) {
  595                         msreg = rdmsr(0x1107);
  596                         msreg |= (0x01 << 28/**/);
  597                         wrmsr(0x1107, msreg);
  598                 }
  599                 via_feature_xcrypt |= VIA_HAS_MM;
  600         }
  601 }
  602 
  603 #endif /* I686_CPU */
  604 
  605 /*
  606  * Initialize CR4 (Control register 4) to enable SSE instructions.
  607  */
  608 void
  609 enable_sse(void)
  610 {
  611 #if defined(CPU_ENABLE_SSE)
  612         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  613                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
  614                 cpu_fxsr = hw_instruction_sse = 1;
  615         }
  616 #endif
  617 }
  618 
  619 void
  620 initializecpu(void)
  621 {
  622 
  623         switch (cpu) {
  624 #ifdef I486_CPU
  625         case CPU_BLUE:
  626                 init_bluelightning();
  627                 break;
  628         case CPU_486DLC:
  629                 init_486dlc();
  630                 break;
  631         case CPU_CY486DX:
  632                 init_cy486dx();
  633                 break;
  634         case CPU_M1SC:
  635                 init_5x86();
  636                 break;
  637 #ifdef CPU_I486_ON_386
  638         case CPU_486:
  639                 init_i486_on_386();
  640                 break;
  641 #endif
  642         case CPU_M1:
  643                 init_6x86();
  644                 break;
  645 #endif /* I486_CPU */
  646 #ifdef I686_CPU
  647         case CPU_M2:
  648                 init_6x86MX();
  649                 break;
  650         case CPU_686:
  651                 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  652                         switch (cpu_id & 0xff0) {
  653                         case 0x610:
  654                                 init_ppro();
  655                                 break;
  656                         case 0x660:
  657                                 init_mendocino();
  658                                 break;
  659                         }
  660                 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  661 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
  662                         /*
  663                          * Sometimes the BIOS doesn't enable SSE instructions.
  664                          * According to AMD document 20734, the mobile
  665                          * Duron, the (mobile) Athlon 4 and the Athlon MP
  666                          * support SSE. These correspond to cpu_id 0x66X
  667                          * or 0x67X.
  668                          */
  669                         if ((cpu_feature & CPUID_XMM) == 0 &&
  670                             ((cpu_id & ~0xf) == 0x660 ||
  671                              (cpu_id & ~0xf) == 0x670 ||
  672                              (cpu_id & ~0xf) == 0x680)) {
  673                                 u_int regs[4];
  674                                 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
  675                                 do_cpuid(1, regs);
  676                                 cpu_feature = regs[3];
  677                         }
  678 #endif
  679                 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
  680                         switch (cpu_id & 0xff0) {
  681                         case 0x690:
  682                                 if ((cpu_id & 0xf) < 3)
  683                                         break;
  684                                 /* fall through. */
  685                         case 0x6a0:
  686                                 init_via();
  687                                 break;
  688                         default:
  689                                 break;
  690                         }
  691                 }
  692 #ifdef PAE
  693                 if ((amd_feature & AMDID_NX) != 0) {
  694                         uint64_t msr;
  695 
  696                         msr = rdmsr(MSR_EFER) | EFER_NXE;
  697                         wrmsr(MSR_EFER, msr);
  698                         pg_nx = PG_NX;
  699                 }
  700 #endif
  701                 break;
  702 #endif
  703         default:
  704                 break;
  705         }
  706         enable_sse();
  707 
  708 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  709         /*
  710          * OS should flush L1 cache by itself because no PC-98 supports
  711          * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
  712          * when need_pre_dma_flush = 1, use invd instruction after DMA
  713          * transfer when need_post_dma_flush = 1.  If your CPU upgrade
  714          * product supports hardware cache control, you can add the
  715          * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
  716          * This option eliminates unneeded cache flush instruction(s).
  717          */
  718         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  719                 switch (cpu) {
  720 #ifdef I486_CPU
  721                 case CPU_486DLC:
  722                         need_post_dma_flush = 1;
  723                         break;
  724                 case CPU_M1SC:
  725                         need_pre_dma_flush = 1;
  726                         break;
  727                 case CPU_CY486DX:
  728                         need_pre_dma_flush = 1;
  729 #ifdef CPU_I486_ON_386
  730                         need_post_dma_flush = 1;
  731 #endif
  732                         break;
  733 #endif
  734                 default:
  735                         break;
  736                 }
  737         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  738                 switch (cpu_id & 0xFF0) {
  739                 case 0x470:             /* Enhanced Am486DX2 WB */
  740                 case 0x490:             /* Enhanced Am486DX4 WB */
  741                 case 0x4F0:             /* Am5x86 WB */
  742                         need_pre_dma_flush = 1;
  743                         break;
  744                 }
  745         } else if (strcmp(cpu_vendor, "IBM") == 0) {
  746                 need_post_dma_flush = 1;
  747         } else {
  748 #ifdef CPU_I486_ON_386
  749                 need_pre_dma_flush = 1;
  750 #endif
  751         }
  752 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
  753 }
  754 
  755 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  756 /*
  757  * Enable write allocate feature of AMD processors.
  758  * Following two functions require the Maxmem variable being set.
  759  */
  760 void
  761 enable_K5_wt_alloc(void)
  762 {
  763         u_int64_t       msr;
  764         register_t      savecrit;
  765 
  766         /*
  767          * Write allocate is supported only on models 1, 2, and 3, with
  768          * a stepping of 4 or greater.
  769          */
  770         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
  771                 savecrit = intr_disable();
  772                 msr = rdmsr(0x83);              /* HWCR */
  773                 wrmsr(0x83, msr & !(0x10));
  774 
  775                 /*
  776                  * We have to tell the chip where the top of memory is,
  777                  * since video cards could have frame bufferes there,
  778                  * memory-mapped I/O could be there, etc.
  779                  */
  780                 if(Maxmem > 0)
  781                   msr = Maxmem / 16;
  782                 else
  783                   msr = 0;
  784                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
  785 #ifdef PC98
  786                 if (!(inb(0x43b) & 4)) {
  787                         wrmsr(0x86, 0x0ff00f0);
  788                         msr |= AMD_WT_ALLOC_PRE;
  789                 }
  790 #else
  791                 /*
  792                  * There is no way to know wheter 15-16M hole exists or not. 
  793                  * Therefore, we disable write allocate for this range.
  794                  */
  795                         wrmsr(0x86, 0x0ff00f0);
  796                         msr |= AMD_WT_ALLOC_PRE;
  797 #endif
  798                 wrmsr(0x85, msr);
  799 
  800                 msr=rdmsr(0x83);
  801                 wrmsr(0x83, msr|0x10); /* enable write allocate */
  802                 intr_restore(savecrit);
  803         }
  804 }
  805 
  806 void
  807 enable_K6_wt_alloc(void)
  808 {
  809         quad_t  size;
  810         u_int64_t       whcr;
  811         u_long  eflags;
  812 
  813         eflags = read_eflags();
  814         disable_intr();
  815         wbinvd();
  816 
  817 #ifdef CPU_DISABLE_CACHE
  818         /*
  819          * Certain K6-2 box becomes unstable when write allocation is
  820          * enabled.
  821          */
  822         /*
  823          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  824          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  825          * All other bits in TR12 have no effect on the processer's operation.
  826          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  827          * on the AMD-K6.
  828          */
  829         wrmsr(0x0000000e, (u_int64_t)0x0008);
  830 #endif
  831         /* Don't assume that memory size is aligned with 4M. */
  832         if (Maxmem > 0)
  833           size = ((Maxmem >> 8) + 3) >> 2;
  834         else
  835           size = 0;
  836 
  837         /* Limit is 508M bytes. */
  838         if (size > 0x7f)
  839                 size = 0x7f;
  840         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
  841 
  842 #if defined(PC98) || defined(NO_MEMORY_HOLE)
  843         if (whcr & (0x7fLL << 1)) {
  844 #ifdef PC98
  845                 /*
  846                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  847                  * 15-16M range.
  848                  */
  849                 if (!(inb(0x43b) & 4))
  850                         whcr &= ~0x0001LL;
  851                 else
  852 #endif
  853                         whcr |=  0x0001LL;
  854         }
  855 #else
  856         /*
  857          * There is no way to know wheter 15-16M hole exists or not. 
  858          * Therefore, we disable write allocate for this range.
  859          */
  860         whcr &= ~0x0001LL;
  861 #endif
  862         wrmsr(0x0c0000082, whcr);
  863 
  864         write_eflags(eflags);
  865 }
  866 
  867 void
  868 enable_K6_2_wt_alloc(void)
  869 {
  870         quad_t  size;
  871         u_int64_t       whcr;
  872         u_long  eflags;
  873 
  874         eflags = read_eflags();
  875         disable_intr();
  876         wbinvd();
  877 
  878 #ifdef CPU_DISABLE_CACHE
  879         /*
  880          * Certain K6-2 box becomes unstable when write allocation is
  881          * enabled.
  882          */
  883         /*
  884          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  885          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  886          * All other bits in TR12 have no effect on the processer's operation.
  887          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  888          * on the AMD-K6.
  889          */
  890         wrmsr(0x0000000e, (u_int64_t)0x0008);
  891 #endif
  892         /* Don't assume that memory size is aligned with 4M. */
  893         if (Maxmem > 0)
  894           size = ((Maxmem >> 8) + 3) >> 2;
  895         else
  896           size = 0;
  897 
  898         /* Limit is 4092M bytes. */
  899         if (size > 0x3fff)
  900                 size = 0x3ff;
  901         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
  902 
  903 #if defined(PC98) || defined(NO_MEMORY_HOLE)
  904         if (whcr & (0x3ffLL << 22)) {
  905 #ifdef PC98
  906                 /*
  907                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  908                  * 15-16M range.
  909                  */
  910                 if (!(inb(0x43b) & 4))
  911                         whcr &= ~(1LL << 16);
  912                 else
  913 #endif
  914                         whcr |=  1LL << 16;
  915         }
  916 #else
  917         /*
  918          * There is no way to know wheter 15-16M hole exists or not. 
  919          * Therefore, we disable write allocate for this range.
  920          */
  921         whcr &= ~(1LL << 16);
  922 #endif
  923         wrmsr(0x0c0000082, whcr);
  924 
  925         write_eflags(eflags);
  926 }
  927 #endif /* I585_CPU && CPU_WT_ALLOC */
  928 
  929 #include "opt_ddb.h"
  930 #ifdef DDB
  931 #include <ddb/ddb.h>
  932 
  933 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
  934 {
  935         u_long  eflags;
  936         u_int   cr0;
  937         u_char  ccr1, ccr2, ccr3;
  938         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
  939 
  940         cr0 = rcr0();
  941         if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
  942                 eflags = read_eflags();
  943                 disable_intr();
  944 
  945 
  946                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
  947                         ccr0 = read_cyrix_reg(CCR0);
  948                 }
  949                 ccr1 = read_cyrix_reg(CCR1);
  950                 ccr2 = read_cyrix_reg(CCR2);
  951                 ccr3 = read_cyrix_reg(CCR3);
  952                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
  953                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  954                         ccr4 = read_cyrix_reg(CCR4);
  955                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
  956                                 ccr5 = read_cyrix_reg(CCR5);
  957                         else
  958                                 pcr0 = read_cyrix_reg(PCR0);
  959                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
  960                 }
  961                 write_eflags(eflags);
  962 
  963                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
  964                         printf("CCR0=%x, ", (u_int)ccr0);
  965 
  966                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
  967                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
  968                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
  969                         printf(", CCR4=%x, ", (u_int)ccr4);
  970                         if (cpu == CPU_M1SC)
  971                                 printf("PCR0=%x\n", pcr0);
  972                         else
  973                                 printf("CCR5=%x\n", ccr5);
  974                 }
  975         }
  976         printf("CR0=%x\n", cr0);
  977 }
  978 #endif /* DDB */

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