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sys/i386/i386/initcpu.c
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1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 48 #define CPU_ENABLE_SSE 49 #endif 50 51 void initializecpu(void); 52 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 53 void enable_K5_wt_alloc(void); 54 void enable_K6_wt_alloc(void); 55 void enable_K6_2_wt_alloc(void); 56 #endif 57 58 #ifdef I486_CPU 59 static void init_5x86(void); 60 static void init_bluelightning(void); 61 static void init_486dlc(void); 62 static void init_cy486dx(void); 63 #ifdef CPU_I486_ON_386 64 static void init_i486_on_386(void); 65 #endif 66 static void init_6x86(void); 67 #endif /* I486_CPU */ 68 69 #ifdef I686_CPU 70 static void init_6x86MX(void); 71 static void init_ppro(void); 72 static void init_mendocino(void); 73 #endif 74 75 static int hw_instruction_sse; 76 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 77 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 78 79 /* Must *NOT* be BSS or locore will bzero these after setting them */ 80 int cpu = 0; /* Are we 386, 386sx, 486, etc? */ 81 u_int cpu_feature = 0; /* Feature flags */ 82 u_int cpu_feature2 = 0; /* Feature flags */ 83 u_int amd_feature = 0; /* AMD feature flags */ 84 u_int amd_feature2 = 0; /* AMD feature flags */ 85 u_int amd_pminfo = 0; /* AMD advanced power management info */ 86 u_int via_feature_rng = 0; /* VIA RNG features */ 87 u_int via_feature_xcrypt = 0; /* VIA ACE features */ 88 u_int cpu_high = 0; /* Highest arg to CPUID */ 89 u_int cpu_id = 0; /* Stepping ID */ 90 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */ 91 u_int cpu_procinfo2 = 0; /* Multicore info */ 92 char cpu_vendor[20] = ""; /* CPU Origin code */ 93 94 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 95 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 96 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 97 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 98 99 #ifdef CPU_ENABLE_SSE 100 u_int cpu_fxsr; /* SSE enabled */ 101 u_int cpu_mxcsr_mask; /* valid bits in mxcsr */ 102 #endif 103 104 #ifdef I486_CPU 105 /* 106 * IBM Blue Lightning 107 */ 108 static void 109 init_bluelightning(void) 110 { 111 u_long eflags; 112 113 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 114 need_post_dma_flush = 1; 115 #endif 116 117 eflags = read_eflags(); 118 disable_intr(); 119 120 load_cr0(rcr0() | CR0_CD | CR0_NW); 121 invd(); 122 123 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 124 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 125 #else 126 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 127 #endif 128 /* Enables 13MB and 0-640KB cache. */ 129 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 130 #ifdef CPU_BLUELIGHTNING_3X 131 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 132 #else 133 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 134 #endif 135 136 /* Enable caching in CR0. */ 137 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 138 invd(); 139 write_eflags(eflags); 140 } 141 142 /* 143 * Cyrix 486SLC/DLC/SR/DR series 144 */ 145 static void 146 init_486dlc(void) 147 { 148 u_long eflags; 149 u_char ccr0; 150 151 eflags = read_eflags(); 152 disable_intr(); 153 invd(); 154 155 ccr0 = read_cyrix_reg(CCR0); 156 #ifndef CYRIX_CACHE_WORKS 157 ccr0 |= CCR0_NC1 | CCR0_BARB; 158 write_cyrix_reg(CCR0, ccr0); 159 invd(); 160 #else 161 ccr0 &= ~CCR0_NC0; 162 #ifndef CYRIX_CACHE_REALLY_WORKS 163 ccr0 |= CCR0_NC1 | CCR0_BARB; 164 #else 165 ccr0 |= CCR0_NC1; 166 #endif 167 #ifdef CPU_DIRECT_MAPPED_CACHE 168 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 169 #endif 170 write_cyrix_reg(CCR0, ccr0); 171 172 /* Clear non-cacheable region. */ 173 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 174 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 175 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 176 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 177 178 write_cyrix_reg(0, 0); /* dummy write */ 179 180 /* Enable caching in CR0. */ 181 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 182 invd(); 183 #endif /* !CYRIX_CACHE_WORKS */ 184 write_eflags(eflags); 185 } 186 187 188 /* 189 * Cyrix 486S/DX series 190 */ 191 static void 192 init_cy486dx(void) 193 { 194 u_long eflags; 195 u_char ccr2; 196 197 eflags = read_eflags(); 198 disable_intr(); 199 invd(); 200 201 ccr2 = read_cyrix_reg(CCR2); 202 #ifdef CPU_SUSP_HLT 203 ccr2 |= CCR2_SUSP_HLT; 204 #endif 205 206 #ifdef PC98 207 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 208 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 209 /* Unlock NW bit in CR0. */ 210 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 211 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 212 #endif 213 214 write_cyrix_reg(CCR2, ccr2); 215 write_eflags(eflags); 216 } 217 218 219 /* 220 * Cyrix 5x86 221 */ 222 static void 223 init_5x86(void) 224 { 225 u_long eflags; 226 u_char ccr2, ccr3, ccr4, pcr0; 227 228 eflags = read_eflags(); 229 disable_intr(); 230 231 load_cr0(rcr0() | CR0_CD | CR0_NW); 232 wbinvd(); 233 234 (void)read_cyrix_reg(CCR3); /* dummy */ 235 236 /* Initialize CCR2. */ 237 ccr2 = read_cyrix_reg(CCR2); 238 ccr2 |= CCR2_WB; 239 #ifdef CPU_SUSP_HLT 240 ccr2 |= CCR2_SUSP_HLT; 241 #else 242 ccr2 &= ~CCR2_SUSP_HLT; 243 #endif 244 ccr2 |= CCR2_WT1; 245 write_cyrix_reg(CCR2, ccr2); 246 247 /* Initialize CCR4. */ 248 ccr3 = read_cyrix_reg(CCR3); 249 write_cyrix_reg(CCR3, CCR3_MAPEN0); 250 251 ccr4 = read_cyrix_reg(CCR4); 252 ccr4 |= CCR4_DTE; 253 ccr4 |= CCR4_MEM; 254 #ifdef CPU_FASTER_5X86_FPU 255 ccr4 |= CCR4_FASTFPE; 256 #else 257 ccr4 &= ~CCR4_FASTFPE; 258 #endif 259 ccr4 &= ~CCR4_IOMASK; 260 /******************************************************************** 261 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 262 * should be 0 for errata fix. 263 ********************************************************************/ 264 #ifdef CPU_IORT 265 ccr4 |= CPU_IORT & CCR4_IOMASK; 266 #endif 267 write_cyrix_reg(CCR4, ccr4); 268 269 /* Initialize PCR0. */ 270 /**************************************************************** 271 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 272 * BTB_EN might make your system unstable. 273 ****************************************************************/ 274 pcr0 = read_cyrix_reg(PCR0); 275 #ifdef CPU_RSTK_EN 276 pcr0 |= PCR0_RSTK; 277 #else 278 pcr0 &= ~PCR0_RSTK; 279 #endif 280 #ifdef CPU_BTB_EN 281 pcr0 |= PCR0_BTB; 282 #else 283 pcr0 &= ~PCR0_BTB; 284 #endif 285 #ifdef CPU_LOOP_EN 286 pcr0 |= PCR0_LOOP; 287 #else 288 pcr0 &= ~PCR0_LOOP; 289 #endif 290 291 /**************************************************************** 292 * WARNING: if you use a memory mapped I/O device, don't use 293 * DISABLE_5X86_LSSER option, which may reorder memory mapped 294 * I/O access. 295 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 296 ****************************************************************/ 297 #ifdef CPU_DISABLE_5X86_LSSER 298 pcr0 &= ~PCR0_LSSER; 299 #else 300 pcr0 |= PCR0_LSSER; 301 #endif 302 write_cyrix_reg(PCR0, pcr0); 303 304 /* Restore CCR3. */ 305 write_cyrix_reg(CCR3, ccr3); 306 307 (void)read_cyrix_reg(0x80); /* dummy */ 308 309 /* Unlock NW bit in CR0. */ 310 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 311 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 312 /* Lock NW bit in CR0. */ 313 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 314 315 write_eflags(eflags); 316 } 317 318 #ifdef CPU_I486_ON_386 319 /* 320 * There are i486 based upgrade products for i386 machines. 321 * In this case, BIOS doesn't enables CPU cache. 322 */ 323 static void 324 init_i486_on_386(void) 325 { 326 u_long eflags; 327 328 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 329 need_post_dma_flush = 1; 330 #endif 331 332 eflags = read_eflags(); 333 disable_intr(); 334 335 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 336 337 write_eflags(eflags); 338 } 339 #endif 340 341 /* 342 * Cyrix 6x86 343 * 344 * XXX - What should I do here? Please let me know. 345 */ 346 static void 347 init_6x86(void) 348 { 349 u_long eflags; 350 u_char ccr3, ccr4; 351 352 eflags = read_eflags(); 353 disable_intr(); 354 355 load_cr0(rcr0() | CR0_CD | CR0_NW); 356 wbinvd(); 357 358 /* Initialize CCR0. */ 359 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 360 361 /* Initialize CCR1. */ 362 #ifdef CPU_CYRIX_NO_LOCK 363 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 364 #else 365 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 366 #endif 367 368 /* Initialize CCR2. */ 369 #ifdef CPU_SUSP_HLT 370 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 371 #else 372 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 373 #endif 374 375 ccr3 = read_cyrix_reg(CCR3); 376 write_cyrix_reg(CCR3, CCR3_MAPEN0); 377 378 /* Initialize CCR4. */ 379 ccr4 = read_cyrix_reg(CCR4); 380 ccr4 |= CCR4_DTE; 381 ccr4 &= ~CCR4_IOMASK; 382 #ifdef CPU_IORT 383 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 384 #else 385 write_cyrix_reg(CCR4, ccr4 | 7); 386 #endif 387 388 /* Initialize CCR5. */ 389 #ifdef CPU_WT_ALLOC 390 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 391 #endif 392 393 /* Restore CCR3. */ 394 write_cyrix_reg(CCR3, ccr3); 395 396 /* Unlock NW bit in CR0. */ 397 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 398 399 /* 400 * Earlier revision of the 6x86 CPU could crash the system if 401 * L1 cache is in write-back mode. 402 */ 403 if ((cyrix_did & 0xff00) > 0x1600) 404 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 405 else { 406 /* Revision 2.6 and lower. */ 407 #ifdef CYRIX_CACHE_REALLY_WORKS 408 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 409 #else 410 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 411 #endif 412 } 413 414 /* Lock NW bit in CR0. */ 415 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 416 417 write_eflags(eflags); 418 } 419 #endif /* I486_CPU */ 420 421 #ifdef I686_CPU 422 /* 423 * Cyrix 6x86MX (code-named M2) 424 * 425 * XXX - What should I do here? Please let me know. 426 */ 427 static void 428 init_6x86MX(void) 429 { 430 u_long eflags; 431 u_char ccr3, ccr4; 432 433 eflags = read_eflags(); 434 disable_intr(); 435 436 load_cr0(rcr0() | CR0_CD | CR0_NW); 437 wbinvd(); 438 439 /* Initialize CCR0. */ 440 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 441 442 /* Initialize CCR1. */ 443 #ifdef CPU_CYRIX_NO_LOCK 444 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 445 #else 446 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 447 #endif 448 449 /* Initialize CCR2. */ 450 #ifdef CPU_SUSP_HLT 451 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 452 #else 453 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 454 #endif 455 456 ccr3 = read_cyrix_reg(CCR3); 457 write_cyrix_reg(CCR3, CCR3_MAPEN0); 458 459 /* Initialize CCR4. */ 460 ccr4 = read_cyrix_reg(CCR4); 461 ccr4 &= ~CCR4_IOMASK; 462 #ifdef CPU_IORT 463 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 464 #else 465 write_cyrix_reg(CCR4, ccr4 | 7); 466 #endif 467 468 /* Initialize CCR5. */ 469 #ifdef CPU_WT_ALLOC 470 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 471 #endif 472 473 /* Restore CCR3. */ 474 write_cyrix_reg(CCR3, ccr3); 475 476 /* Unlock NW bit in CR0. */ 477 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 478 479 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 480 481 /* Lock NW bit in CR0. */ 482 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 483 484 write_eflags(eflags); 485 } 486 487 static void 488 init_ppro(void) 489 { 490 u_int64_t apicbase; 491 492 /* 493 * Local APIC should be disabled if it is not going to be used. 494 */ 495 apicbase = rdmsr(MSR_APICBASE); 496 apicbase &= ~APICBASE_ENABLED; 497 wrmsr(MSR_APICBASE, apicbase); 498 } 499 500 /* 501 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 502 * L2 cache). 503 */ 504 static void 505 init_mendocino(void) 506 { 507 #ifdef CPU_PPRO2CELERON 508 u_long eflags; 509 u_int64_t bbl_cr_ctl3; 510 511 eflags = read_eflags(); 512 disable_intr(); 513 514 load_cr0(rcr0() | CR0_CD | CR0_NW); 515 wbinvd(); 516 517 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 518 519 /* If the L2 cache is configured, do nothing. */ 520 if (!(bbl_cr_ctl3 & 1)) { 521 bbl_cr_ctl3 = 0x134052bLL; 522 523 /* Set L2 Cache Latency (Default: 5). */ 524 #ifdef CPU_CELERON_L2_LATENCY 525 #if CPU_L2_LATENCY > 15 526 #error invalid CPU_L2_LATENCY. 527 #endif 528 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 529 #else 530 bbl_cr_ctl3 |= 5 << 1; 531 #endif 532 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 533 } 534 535 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 536 write_eflags(eflags); 537 #endif /* CPU_PPRO2CELERON */ 538 } 539 540 /* 541 * Initialize special VIA C3/C7 features 542 */ 543 static void 544 init_via(void) 545 { 546 u_int regs[4], val; 547 u_int64_t msreg; 548 549 do_cpuid(0xc0000000, regs); 550 val = regs[0]; 551 if (val >= 0xc0000001) { 552 do_cpuid(0xc0000001, regs); 553 val = regs[3]; 554 } else 555 val = 0; 556 557 /* Enable RNG if present and disabled */ 558 if (val & VIA_CPUID_HAS_RNG) { 559 if (!(val & VIA_CPUID_DO_RNG)) { 560 msreg = rdmsr(0x110B); 561 msreg |= 0x40; 562 wrmsr(0x110B, msreg); 563 } 564 via_feature_rng = VIA_HAS_RNG; 565 } 566 /* Enable AES engine if present and disabled */ 567 if (val & VIA_CPUID_HAS_ACE) { 568 if (!(val & VIA_CPUID_DO_ACE)) { 569 msreg = rdmsr(0x1107); 570 msreg |= (0x01 << 28); 571 wrmsr(0x1107, msreg); 572 } 573 via_feature_xcrypt |= VIA_HAS_AES; 574 } 575 /* Enable ACE2 engine if present and disabled */ 576 if (val & VIA_CPUID_HAS_ACE2) { 577 if (!(val & VIA_CPUID_DO_ACE2)) { 578 msreg = rdmsr(0x1107); 579 msreg |= (0x01 << 28); 580 wrmsr(0x1107, msreg); 581 } 582 via_feature_xcrypt |= VIA_HAS_AESCTR; 583 } 584 /* Enable SHA engine if present and disabled */ 585 if (val & VIA_CPUID_HAS_PHE) { 586 if (!(val & VIA_CPUID_DO_PHE)) { 587 msreg = rdmsr(0x1107); 588 msreg |= (0x01 << 28/**/); 589 wrmsr(0x1107, msreg); 590 } 591 via_feature_xcrypt |= VIA_HAS_SHA; 592 } 593 /* Enable MM engine if present and disabled */ 594 if (val & VIA_CPUID_HAS_PMM) { 595 if (!(val & VIA_CPUID_DO_PMM)) { 596 msreg = rdmsr(0x1107); 597 msreg |= (0x01 << 28/**/); 598 wrmsr(0x1107, msreg); 599 } 600 via_feature_xcrypt |= VIA_HAS_MM; 601 } 602 } 603 604 #endif /* I686_CPU */ 605 606 /* 607 * Initialize CR4 (Control register 4) to enable SSE instructions. 608 */ 609 void 610 enable_sse(void) 611 { 612 #if defined(CPU_ENABLE_SSE) 613 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 614 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 615 cpu_fxsr = hw_instruction_sse = 1; 616 } 617 #endif 618 } 619 620 void 621 initializecpu(void) 622 { 623 624 switch (cpu) { 625 #ifdef I486_CPU 626 case CPU_BLUE: 627 init_bluelightning(); 628 break; 629 case CPU_486DLC: 630 init_486dlc(); 631 break; 632 case CPU_CY486DX: 633 init_cy486dx(); 634 break; 635 case CPU_M1SC: 636 init_5x86(); 637 break; 638 #ifdef CPU_I486_ON_386 639 case CPU_486: 640 init_i486_on_386(); 641 break; 642 #endif 643 case CPU_M1: 644 init_6x86(); 645 break; 646 #endif /* I486_CPU */ 647 #ifdef I686_CPU 648 case CPU_M2: 649 init_6x86MX(); 650 break; 651 case CPU_686: 652 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 653 switch (cpu_id & 0xff0) { 654 case 0x610: 655 init_ppro(); 656 break; 657 case 0x660: 658 init_mendocino(); 659 break; 660 } 661 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 662 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) 663 /* 664 * Sometimes the BIOS doesn't enable SSE instructions. 665 * According to AMD document 20734, the mobile 666 * Duron, the (mobile) Athlon 4 and the Athlon MP 667 * support SSE. These correspond to cpu_id 0x66X 668 * or 0x67X. 669 */ 670 if ((cpu_feature & CPUID_XMM) == 0 && 671 ((cpu_id & ~0xf) == 0x660 || 672 (cpu_id & ~0xf) == 0x670 || 673 (cpu_id & ~0xf) == 0x680)) { 674 u_int regs[4]; 675 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); 676 do_cpuid(1, regs); 677 cpu_feature = regs[3]; 678 } 679 #endif 680 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { 681 switch (cpu_id & 0xff0) { 682 case 0x690: 683 if ((cpu_id & 0xf) < 3) 684 break; 685 /* fall through. */ 686 case 0x6a0: 687 case 0x6d0: 688 init_via(); 689 break; 690 default: 691 break; 692 } 693 } 694 #ifdef PAE 695 if ((amd_feature & AMDID_NX) != 0) { 696 uint64_t msr; 697 698 msr = rdmsr(MSR_EFER) | EFER_NXE; 699 wrmsr(MSR_EFER, msr); 700 pg_nx = PG_NX; 701 } 702 #endif 703 break; 704 #endif 705 default: 706 break; 707 } 708 enable_sse(); 709 710 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 711 /* 712 * OS should flush L1 cache by itself because no PC-98 supports 713 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 714 * when need_pre_dma_flush = 1, use invd instruction after DMA 715 * transfer when need_post_dma_flush = 1. If your CPU upgrade 716 * product supports hardware cache control, you can add the 717 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 718 * This option eliminates unneeded cache flush instruction(s). 719 */ 720 if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 721 switch (cpu) { 722 #ifdef I486_CPU 723 case CPU_486DLC: 724 need_post_dma_flush = 1; 725 break; 726 case CPU_M1SC: 727 need_pre_dma_flush = 1; 728 break; 729 case CPU_CY486DX: 730 need_pre_dma_flush = 1; 731 #ifdef CPU_I486_ON_386 732 need_post_dma_flush = 1; 733 #endif 734 break; 735 #endif 736 default: 737 break; 738 } 739 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 740 switch (cpu_id & 0xFF0) { 741 case 0x470: /* Enhanced Am486DX2 WB */ 742 case 0x490: /* Enhanced Am486DX4 WB */ 743 case 0x4F0: /* Am5x86 WB */ 744 need_pre_dma_flush = 1; 745 break; 746 } 747 } else if (strcmp(cpu_vendor, "IBM") == 0) { 748 need_post_dma_flush = 1; 749 } else { 750 #ifdef CPU_I486_ON_386 751 need_pre_dma_flush = 1; 752 #endif 753 } 754 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 755 } 756 757 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 758 /* 759 * Enable write allocate feature of AMD processors. 760 * Following two functions require the Maxmem variable being set. 761 */ 762 void 763 enable_K5_wt_alloc(void) 764 { 765 u_int64_t msr; 766 register_t savecrit; 767 768 /* 769 * Write allocate is supported only on models 1, 2, and 3, with 770 * a stepping of 4 or greater. 771 */ 772 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 773 savecrit = intr_disable(); 774 msr = rdmsr(0x83); /* HWCR */ 775 wrmsr(0x83, msr & !(0x10)); 776 777 /* 778 * We have to tell the chip where the top of memory is, 779 * since video cards could have frame bufferes there, 780 * memory-mapped I/O could be there, etc. 781 */ 782 if(Maxmem > 0) 783 msr = Maxmem / 16; 784 else 785 msr = 0; 786 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 787 #ifdef PC98 788 if (!(inb(0x43b) & 4)) { 789 wrmsr(0x86, 0x0ff00f0); 790 msr |= AMD_WT_ALLOC_PRE; 791 } 792 #else 793 /* 794 * There is no way to know wheter 15-16M hole exists or not. 795 * Therefore, we disable write allocate for this range. 796 */ 797 wrmsr(0x86, 0x0ff00f0); 798 msr |= AMD_WT_ALLOC_PRE; 799 #endif 800 wrmsr(0x85, msr); 801 802 msr=rdmsr(0x83); 803 wrmsr(0x83, msr|0x10); /* enable write allocate */ 804 intr_restore(savecrit); 805 } 806 } 807 808 void 809 enable_K6_wt_alloc(void) 810 { 811 quad_t size; 812 u_int64_t whcr; 813 u_long eflags; 814 815 eflags = read_eflags(); 816 disable_intr(); 817 wbinvd(); 818 819 #ifdef CPU_DISABLE_CACHE 820 /* 821 * Certain K6-2 box becomes unstable when write allocation is 822 * enabled. 823 */ 824 /* 825 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 826 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 827 * All other bits in TR12 have no effect on the processer's operation. 828 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 829 * on the AMD-K6. 830 */ 831 wrmsr(0x0000000e, (u_int64_t)0x0008); 832 #endif 833 /* Don't assume that memory size is aligned with 4M. */ 834 if (Maxmem > 0) 835 size = ((Maxmem >> 8) + 3) >> 2; 836 else 837 size = 0; 838 839 /* Limit is 508M bytes. */ 840 if (size > 0x7f) 841 size = 0x7f; 842 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 843 844 #if defined(PC98) || defined(NO_MEMORY_HOLE) 845 if (whcr & (0x7fLL << 1)) { 846 #ifdef PC98 847 /* 848 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 849 * 15-16M range. 850 */ 851 if (!(inb(0x43b) & 4)) 852 whcr &= ~0x0001LL; 853 else 854 #endif 855 whcr |= 0x0001LL; 856 } 857 #else 858 /* 859 * There is no way to know wheter 15-16M hole exists or not. 860 * Therefore, we disable write allocate for this range. 861 */ 862 whcr &= ~0x0001LL; 863 #endif 864 wrmsr(0x0c0000082, whcr); 865 866 write_eflags(eflags); 867 } 868 869 void 870 enable_K6_2_wt_alloc(void) 871 { 872 quad_t size; 873 u_int64_t whcr; 874 u_long eflags; 875 876 eflags = read_eflags(); 877 disable_intr(); 878 wbinvd(); 879 880 #ifdef CPU_DISABLE_CACHE 881 /* 882 * Certain K6-2 box becomes unstable when write allocation is 883 * enabled. 884 */ 885 /* 886 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 887 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 888 * All other bits in TR12 have no effect on the processer's operation. 889 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 890 * on the AMD-K6. 891 */ 892 wrmsr(0x0000000e, (u_int64_t)0x0008); 893 #endif 894 /* Don't assume that memory size is aligned with 4M. */ 895 if (Maxmem > 0) 896 size = ((Maxmem >> 8) + 3) >> 2; 897 else 898 size = 0; 899 900 /* Limit is 4092M bytes. */ 901 if (size > 0x3fff) 902 size = 0x3ff; 903 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 904 905 #if defined(PC98) || defined(NO_MEMORY_HOLE) 906 if (whcr & (0x3ffLL << 22)) { 907 #ifdef PC98 908 /* 909 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 910 * 15-16M range. 911 */ 912 if (!(inb(0x43b) & 4)) 913 whcr &= ~(1LL << 16); 914 else 915 #endif 916 whcr |= 1LL << 16; 917 } 918 #else 919 /* 920 * There is no way to know wheter 15-16M hole exists or not. 921 * Therefore, we disable write allocate for this range. 922 */ 923 whcr &= ~(1LL << 16); 924 #endif 925 wrmsr(0x0c0000082, whcr); 926 927 write_eflags(eflags); 928 } 929 #endif /* I585_CPU && CPU_WT_ALLOC */ 930 931 #include "opt_ddb.h" 932 #ifdef DDB 933 #include <ddb/ddb.h> 934 935 DB_SHOW_COMMAND(cyrixreg, cyrixreg) 936 { 937 u_long eflags; 938 u_int cr0; 939 u_char ccr1, ccr2, ccr3; 940 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 941 942 cr0 = rcr0(); 943 if (strcmp(cpu_vendor,"CyrixInstead") == 0) { 944 eflags = read_eflags(); 945 disable_intr(); 946 947 948 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 949 ccr0 = read_cyrix_reg(CCR0); 950 } 951 ccr1 = read_cyrix_reg(CCR1); 952 ccr2 = read_cyrix_reg(CCR2); 953 ccr3 = read_cyrix_reg(CCR3); 954 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 955 write_cyrix_reg(CCR3, CCR3_MAPEN0); 956 ccr4 = read_cyrix_reg(CCR4); 957 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 958 ccr5 = read_cyrix_reg(CCR5); 959 else 960 pcr0 = read_cyrix_reg(PCR0); 961 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 962 } 963 write_eflags(eflags); 964 965 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 966 printf("CCR0=%x, ", (u_int)ccr0); 967 968 printf("CCR1=%x, CCR2=%x, CCR3=%x", 969 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 970 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 971 printf(", CCR4=%x, ", (u_int)ccr4); 972 if (cpu == CPU_M1SC) 973 printf("PCR0=%x\n", pcr0); 974 else 975 printf("CCR5=%x\n", ccr5); 976 } 977 } 978 printf("CR0=%x\n", cr0); 979 } 980 #endif /* DDB */
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