The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/initcpu.c

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    1 /*-
    2  * Copyright (c) KATO Takenori, 1997, 1998.
    3  * 
    4  * All rights reserved.  Unpublished rights reserved under the copyright
    5  * laws of Japan.
    6  * 
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer as
   13  *    the first lines of this file unmodified.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/7.4/sys/i386/i386/initcpu.c 211892 2010-08-27 18:55:48Z jhb $");
   32 
   33 #include "opt_cpu.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/kernel.h>
   37 #include <sys/systm.h>
   38 #include <sys/sysctl.h>
   39 
   40 #include <machine/cputypes.h>
   41 #include <machine/md_var.h>
   42 #include <machine/specialreg.h>
   43 
   44 #include <vm/vm.h>
   45 #include <vm/pmap.h>
   46 
   47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
   48 #define CPU_ENABLE_SSE
   49 #endif
   50 
   51 void initializecpu(void);
   52 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   53 void    enable_K5_wt_alloc(void);
   54 void    enable_K6_wt_alloc(void);
   55 void    enable_K6_2_wt_alloc(void);
   56 #endif
   57 
   58 #ifdef I486_CPU
   59 static void init_5x86(void);
   60 static void init_bluelightning(void);
   61 static void init_486dlc(void);
   62 static void init_cy486dx(void);
   63 #ifdef CPU_I486_ON_386
   64 static void init_i486_on_386(void);
   65 #endif
   66 static void init_6x86(void);
   67 #endif /* I486_CPU */
   68 
   69 #ifdef I686_CPU
   70 static void     init_6x86MX(void);
   71 static void     init_ppro(void);
   72 static void     init_mendocino(void);
   73 #endif
   74 
   75 static int      hw_instruction_sse;
   76 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
   77     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
   78 /*
   79  * -1: automatic (default)
   80  *  0: keep enable CLFLUSH
   81  *  1: force disable CLFLUSH
   82  */
   83 static int      hw_clflush_disable = -1;
   84 
   85 /* Must *NOT* be BSS or locore will bzero these after setting them */
   86 int     cpu = 0;                /* Are we 386, 386sx, 486, etc? */
   87 u_int   cpu_feature = 0;        /* Feature flags */
   88 u_int   cpu_feature2 = 0;       /* Feature flags */
   89 u_int   amd_feature = 0;        /* AMD feature flags */
   90 u_int   amd_feature2 = 0;       /* AMD feature flags */
   91 u_int   amd_pminfo = 0;         /* AMD advanced power management info */
   92 u_int   via_feature_rng = 0;    /* VIA RNG features */
   93 u_int   via_feature_xcrypt = 0; /* VIA ACE features */
   94 u_int   cpu_high = 0;           /* Highest arg to CPUID */
   95 u_int   cpu_id = 0;             /* Stepping ID */
   96 u_int   cpu_procinfo = 0;       /* HyperThreading Info / Brand Index / CLFUSH */
   97 u_int   cpu_procinfo2 = 0;      /* Multicore info */
   98 char    cpu_vendor[20] = "";    /* CPU Origin code */
   99 u_int   cpu_vendor_id = 0;      /* CPU vendor ID */
  100 u_int   cpu_clflush_line_size = 32;
  101 
  102 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
  103         &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
  104 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
  105         &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
  106 
  107 #ifdef CPU_ENABLE_SSE
  108 u_int   cpu_fxsr;               /* SSE enabled */
  109 u_int   cpu_mxcsr_mask;         /* valid bits in mxcsr */
  110 #endif
  111 
  112 #ifdef I486_CPU
  113 /*
  114  * IBM Blue Lightning
  115  */
  116 static void
  117 init_bluelightning(void)
  118 {
  119         u_long  eflags;
  120 
  121 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  122         need_post_dma_flush = 1;
  123 #endif
  124 
  125         eflags = read_eflags();
  126         disable_intr();
  127 
  128         load_cr0(rcr0() | CR0_CD | CR0_NW);
  129         invd();
  130 
  131 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
  132         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
  133 #else
  134         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
  135 #endif
  136         /* Enables 13MB and 0-640KB cache. */
  137         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
  138 #ifdef CPU_BLUELIGHTNING_3X
  139         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
  140 #else
  141         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
  142 #endif
  143 
  144         /* Enable caching in CR0. */
  145         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  146         invd();
  147         write_eflags(eflags);
  148 }
  149 
  150 /*
  151  * Cyrix 486SLC/DLC/SR/DR series
  152  */
  153 static void
  154 init_486dlc(void)
  155 {
  156         u_long  eflags;
  157         u_char  ccr0;
  158 
  159         eflags = read_eflags();
  160         disable_intr();
  161         invd();
  162 
  163         ccr0 = read_cyrix_reg(CCR0);
  164 #ifndef CYRIX_CACHE_WORKS
  165         ccr0 |= CCR0_NC1 | CCR0_BARB;
  166         write_cyrix_reg(CCR0, ccr0);
  167         invd();
  168 #else
  169         ccr0 &= ~CCR0_NC0;
  170 #ifndef CYRIX_CACHE_REALLY_WORKS
  171         ccr0 |= CCR0_NC1 | CCR0_BARB;
  172 #else
  173         ccr0 |= CCR0_NC1;
  174 #endif
  175 #ifdef CPU_DIRECT_MAPPED_CACHE
  176         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
  177 #endif
  178         write_cyrix_reg(CCR0, ccr0);
  179 
  180         /* Clear non-cacheable region. */
  181         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
  182         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
  183         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
  184         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
  185 
  186         write_cyrix_reg(0, 0);  /* dummy write */
  187 
  188         /* Enable caching in CR0. */
  189         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  190         invd();
  191 #endif /* !CYRIX_CACHE_WORKS */
  192         write_eflags(eflags);
  193 }
  194 
  195 
  196 /*
  197  * Cyrix 486S/DX series
  198  */
  199 static void
  200 init_cy486dx(void)
  201 {
  202         u_long  eflags;
  203         u_char  ccr2;
  204 
  205         eflags = read_eflags();
  206         disable_intr();
  207         invd();
  208 
  209         ccr2 = read_cyrix_reg(CCR2);
  210 #ifdef CPU_SUSP_HLT
  211         ccr2 |= CCR2_SUSP_HLT;
  212 #endif
  213 
  214 #ifdef PC98
  215         /* Enables WB cache interface pin and Lock NW bit in CR0. */
  216         ccr2 |= CCR2_WB | CCR2_LOCK_NW;
  217         /* Unlock NW bit in CR0. */
  218         write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
  219         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
  220 #endif
  221 
  222         write_cyrix_reg(CCR2, ccr2);
  223         write_eflags(eflags);
  224 }
  225 
  226 
  227 /*
  228  * Cyrix 5x86
  229  */
  230 static void
  231 init_5x86(void)
  232 {
  233         u_long  eflags;
  234         u_char  ccr2, ccr3, ccr4, pcr0;
  235 
  236         eflags = read_eflags();
  237         disable_intr();
  238 
  239         load_cr0(rcr0() | CR0_CD | CR0_NW);
  240         wbinvd();
  241 
  242         (void)read_cyrix_reg(CCR3);             /* dummy */
  243 
  244         /* Initialize CCR2. */
  245         ccr2 = read_cyrix_reg(CCR2);
  246         ccr2 |= CCR2_WB;
  247 #ifdef CPU_SUSP_HLT
  248         ccr2 |= CCR2_SUSP_HLT;
  249 #else
  250         ccr2 &= ~CCR2_SUSP_HLT;
  251 #endif
  252         ccr2 |= CCR2_WT1;
  253         write_cyrix_reg(CCR2, ccr2);
  254 
  255         /* Initialize CCR4. */
  256         ccr3 = read_cyrix_reg(CCR3);
  257         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  258 
  259         ccr4 = read_cyrix_reg(CCR4);
  260         ccr4 |= CCR4_DTE;
  261         ccr4 |= CCR4_MEM;
  262 #ifdef CPU_FASTER_5X86_FPU
  263         ccr4 |= CCR4_FASTFPE;
  264 #else
  265         ccr4 &= ~CCR4_FASTFPE;
  266 #endif
  267         ccr4 &= ~CCR4_IOMASK;
  268         /********************************************************************
  269          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
  270          * should be 0 for errata fix.
  271          ********************************************************************/
  272 #ifdef CPU_IORT
  273         ccr4 |= CPU_IORT & CCR4_IOMASK;
  274 #endif
  275         write_cyrix_reg(CCR4, ccr4);
  276 
  277         /* Initialize PCR0. */
  278         /****************************************************************
  279          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
  280          * BTB_EN might make your system unstable.
  281          ****************************************************************/
  282         pcr0 = read_cyrix_reg(PCR0);
  283 #ifdef CPU_RSTK_EN
  284         pcr0 |= PCR0_RSTK;
  285 #else
  286         pcr0 &= ~PCR0_RSTK;
  287 #endif
  288 #ifdef CPU_BTB_EN
  289         pcr0 |= PCR0_BTB;
  290 #else
  291         pcr0 &= ~PCR0_BTB;
  292 #endif
  293 #ifdef CPU_LOOP_EN
  294         pcr0 |= PCR0_LOOP;
  295 #else
  296         pcr0 &= ~PCR0_LOOP;
  297 #endif
  298 
  299         /****************************************************************
  300          * WARNING: if you use a memory mapped I/O device, don't use
  301          * DISABLE_5X86_LSSER option, which may reorder memory mapped
  302          * I/O access.
  303          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
  304          ****************************************************************/
  305 #ifdef CPU_DISABLE_5X86_LSSER
  306         pcr0 &= ~PCR0_LSSER;
  307 #else
  308         pcr0 |= PCR0_LSSER;
  309 #endif
  310         write_cyrix_reg(PCR0, pcr0);
  311 
  312         /* Restore CCR3. */
  313         write_cyrix_reg(CCR3, ccr3);
  314 
  315         (void)read_cyrix_reg(0x80);             /* dummy */
  316 
  317         /* Unlock NW bit in CR0. */
  318         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  319         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
  320         /* Lock NW bit in CR0. */
  321         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  322 
  323         write_eflags(eflags);
  324 }
  325 
  326 #ifdef CPU_I486_ON_386
  327 /*
  328  * There are i486 based upgrade products for i386 machines.
  329  * In this case, BIOS doesn't enables CPU cache.
  330  */
  331 static void
  332 init_i486_on_386(void)
  333 {
  334         u_long  eflags;
  335 
  336 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  337         need_post_dma_flush = 1;
  338 #endif
  339 
  340         eflags = read_eflags();
  341         disable_intr();
  342 
  343         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
  344 
  345         write_eflags(eflags);
  346 }
  347 #endif
  348 
  349 /*
  350  * Cyrix 6x86
  351  *
  352  * XXX - What should I do here?  Please let me know.
  353  */
  354 static void
  355 init_6x86(void)
  356 {
  357         u_long  eflags;
  358         u_char  ccr3, ccr4;
  359 
  360         eflags = read_eflags();
  361         disable_intr();
  362 
  363         load_cr0(rcr0() | CR0_CD | CR0_NW);
  364         wbinvd();
  365 
  366         /* Initialize CCR0. */
  367         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  368 
  369         /* Initialize CCR1. */
  370 #ifdef CPU_CYRIX_NO_LOCK
  371         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  372 #else
  373         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  374 #endif
  375 
  376         /* Initialize CCR2. */
  377 #ifdef CPU_SUSP_HLT
  378         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  379 #else
  380         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  381 #endif
  382 
  383         ccr3 = read_cyrix_reg(CCR3);
  384         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  385 
  386         /* Initialize CCR4. */
  387         ccr4 = read_cyrix_reg(CCR4);
  388         ccr4 |= CCR4_DTE;
  389         ccr4 &= ~CCR4_IOMASK;
  390 #ifdef CPU_IORT
  391         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  392 #else
  393         write_cyrix_reg(CCR4, ccr4 | 7);
  394 #endif
  395 
  396         /* Initialize CCR5. */
  397 #ifdef CPU_WT_ALLOC
  398         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  399 #endif
  400 
  401         /* Restore CCR3. */
  402         write_cyrix_reg(CCR3, ccr3);
  403 
  404         /* Unlock NW bit in CR0. */
  405         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  406 
  407         /*
  408          * Earlier revision of the 6x86 CPU could crash the system if
  409          * L1 cache is in write-back mode.
  410          */
  411         if ((cyrix_did & 0xff00) > 0x1600)
  412                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  413         else {
  414                 /* Revision 2.6 and lower. */
  415 #ifdef CYRIX_CACHE_REALLY_WORKS
  416                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  417 #else
  418                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
  419 #endif
  420         }
  421 
  422         /* Lock NW bit in CR0. */
  423         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  424 
  425         write_eflags(eflags);
  426 }
  427 #endif /* I486_CPU */
  428 
  429 #ifdef I686_CPU
  430 /*
  431  * Cyrix 6x86MX (code-named M2)
  432  *
  433  * XXX - What should I do here?  Please let me know.
  434  */
  435 static void
  436 init_6x86MX(void)
  437 {
  438         u_long  eflags;
  439         u_char  ccr3, ccr4;
  440 
  441         eflags = read_eflags();
  442         disable_intr();
  443 
  444         load_cr0(rcr0() | CR0_CD | CR0_NW);
  445         wbinvd();
  446 
  447         /* Initialize CCR0. */
  448         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  449 
  450         /* Initialize CCR1. */
  451 #ifdef CPU_CYRIX_NO_LOCK
  452         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  453 #else
  454         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  455 #endif
  456 
  457         /* Initialize CCR2. */
  458 #ifdef CPU_SUSP_HLT
  459         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  460 #else
  461         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  462 #endif
  463 
  464         ccr3 = read_cyrix_reg(CCR3);
  465         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  466 
  467         /* Initialize CCR4. */
  468         ccr4 = read_cyrix_reg(CCR4);
  469         ccr4 &= ~CCR4_IOMASK;
  470 #ifdef CPU_IORT
  471         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  472 #else
  473         write_cyrix_reg(CCR4, ccr4 | 7);
  474 #endif
  475 
  476         /* Initialize CCR5. */
  477 #ifdef CPU_WT_ALLOC
  478         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  479 #endif
  480 
  481         /* Restore CCR3. */
  482         write_cyrix_reg(CCR3, ccr3);
  483 
  484         /* Unlock NW bit in CR0. */
  485         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  486 
  487         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
  488 
  489         /* Lock NW bit in CR0. */
  490         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  491 
  492         write_eflags(eflags);
  493 }
  494 
  495 static void
  496 init_ppro(void)
  497 {
  498         u_int64_t       apicbase;
  499 
  500         /*
  501          * Local APIC should be disabled if it is not going to be used.
  502          */
  503         apicbase = rdmsr(MSR_APICBASE);
  504         apicbase &= ~APICBASE_ENABLED;
  505         wrmsr(MSR_APICBASE, apicbase);
  506 }
  507 
  508 /*
  509  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
  510  * L2 cache).
  511  */
  512 static void
  513 init_mendocino(void)
  514 {
  515 #ifdef CPU_PPRO2CELERON
  516         u_long  eflags;
  517         u_int64_t       bbl_cr_ctl3;
  518 
  519         eflags = read_eflags();
  520         disable_intr();
  521 
  522         load_cr0(rcr0() | CR0_CD | CR0_NW);
  523         wbinvd();
  524 
  525         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
  526 
  527         /* If the L2 cache is configured, do nothing. */
  528         if (!(bbl_cr_ctl3 & 1)) {
  529                 bbl_cr_ctl3 = 0x134052bLL;
  530 
  531                 /* Set L2 Cache Latency (Default: 5). */
  532 #ifdef  CPU_CELERON_L2_LATENCY
  533 #if CPU_L2_LATENCY > 15
  534 #error invalid CPU_L2_LATENCY.
  535 #endif
  536                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
  537 #else
  538                 bbl_cr_ctl3 |= 5 << 1;
  539 #endif
  540                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
  541         }
  542 
  543         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
  544         write_eflags(eflags);
  545 #endif /* CPU_PPRO2CELERON */
  546 }
  547 
  548 /*
  549  * Initialize special VIA C3/C7 features
  550  */
  551 static void
  552 init_via(void)
  553 {
  554         u_int regs[4], val;
  555         u_int64_t msreg;
  556 
  557         do_cpuid(0xc0000000, regs);
  558         val = regs[0];
  559         if (val >= 0xc0000001) {
  560                 do_cpuid(0xc0000001, regs);
  561                 val = regs[3];
  562         } else
  563                 val = 0;
  564 
  565         /* Enable RNG if present and disabled */
  566         if (val & VIA_CPUID_HAS_RNG) {
  567                 if (!(val & VIA_CPUID_DO_RNG)) {
  568                         msreg = rdmsr(0x110B);
  569                         msreg |= 0x40;
  570                         wrmsr(0x110B, msreg);
  571                 }
  572                 via_feature_rng = VIA_HAS_RNG;
  573         }
  574         /* Enable AES engine if present and disabled */
  575         if (val & VIA_CPUID_HAS_ACE) {
  576                 if (!(val & VIA_CPUID_DO_ACE)) {
  577                         msreg = rdmsr(0x1107);
  578                         msreg |= (0x01 << 28);
  579                         wrmsr(0x1107, msreg);
  580                 }
  581                 via_feature_xcrypt |= VIA_HAS_AES;
  582         }
  583         /* Enable ACE2 engine if present and disabled */
  584         if (val & VIA_CPUID_HAS_ACE2) {
  585                 if (!(val & VIA_CPUID_DO_ACE2)) {
  586                         msreg = rdmsr(0x1107);
  587                         msreg |= (0x01 << 28);
  588                         wrmsr(0x1107, msreg);
  589                 }
  590                 via_feature_xcrypt |= VIA_HAS_AESCTR;
  591         }
  592         /* Enable SHA engine if present and disabled */
  593         if (val & VIA_CPUID_HAS_PHE) {
  594                 if (!(val & VIA_CPUID_DO_PHE)) {
  595                         msreg = rdmsr(0x1107);
  596                         msreg |= (0x01 << 28/**/);
  597                         wrmsr(0x1107, msreg);
  598                 }
  599                 via_feature_xcrypt |= VIA_HAS_SHA;
  600         }
  601         /* Enable MM engine if present and disabled */
  602         if (val & VIA_CPUID_HAS_PMM) {
  603                 if (!(val & VIA_CPUID_DO_PMM)) {
  604                         msreg = rdmsr(0x1107);
  605                         msreg |= (0x01 << 28/**/);
  606                         wrmsr(0x1107, msreg);
  607                 }
  608                 via_feature_xcrypt |= VIA_HAS_MM;
  609         }
  610 }
  611 
  612 #endif /* I686_CPU */
  613 
  614 /*
  615  * Initialize CR4 (Control register 4) to enable SSE instructions.
  616  */
  617 void
  618 enable_sse(void)
  619 {
  620 #if defined(CPU_ENABLE_SSE)
  621         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  622                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
  623                 cpu_fxsr = hw_instruction_sse = 1;
  624         }
  625 #endif
  626 }
  627 
  628 void
  629 initializecpu(void)
  630 {
  631 
  632         switch (cpu) {
  633 #ifdef I486_CPU
  634         case CPU_BLUE:
  635                 init_bluelightning();
  636                 break;
  637         case CPU_486DLC:
  638                 init_486dlc();
  639                 break;
  640         case CPU_CY486DX:
  641                 init_cy486dx();
  642                 break;
  643         case CPU_M1SC:
  644                 init_5x86();
  645                 break;
  646 #ifdef CPU_I486_ON_386
  647         case CPU_486:
  648                 init_i486_on_386();
  649                 break;
  650 #endif
  651         case CPU_M1:
  652                 init_6x86();
  653                 break;
  654 #endif /* I486_CPU */
  655 #ifdef I686_CPU
  656         case CPU_M2:
  657                 init_6x86MX();
  658                 break;
  659         case CPU_686:
  660                 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  661                         switch (cpu_id & 0xff0) {
  662                         case 0x610:
  663                                 init_ppro();
  664                                 break;
  665                         case 0x660:
  666                                 init_mendocino();
  667                                 break;
  668                         }
  669                 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
  670 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
  671                         /*
  672                          * Sometimes the BIOS doesn't enable SSE instructions.
  673                          * According to AMD document 20734, the mobile
  674                          * Duron, the (mobile) Athlon 4 and the Athlon MP
  675                          * support SSE. These correspond to cpu_id 0x66X
  676                          * or 0x67X.
  677                          */
  678                         if ((cpu_feature & CPUID_XMM) == 0 &&
  679                             ((cpu_id & ~0xf) == 0x660 ||
  680                              (cpu_id & ~0xf) == 0x670 ||
  681                              (cpu_id & ~0xf) == 0x680)) {
  682                                 u_int regs[4];
  683                                 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
  684                                 do_cpuid(1, regs);
  685                                 cpu_feature = regs[3];
  686                         }
  687 #endif
  688                 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
  689                         switch (cpu_id & 0xff0) {
  690                         case 0x690:
  691                                 if ((cpu_id & 0xf) < 3)
  692                                         break;
  693                                 /* fall through. */
  694                         case 0x6a0:
  695                         case 0x6d0:
  696                         case 0x6f0:
  697                                 init_via();
  698                                 break;
  699                         default:
  700                                 break;
  701                         }
  702                 }
  703 #ifdef PAE
  704                 if ((amd_feature & AMDID_NX) != 0) {
  705                         uint64_t msr;
  706 
  707                         msr = rdmsr(MSR_EFER) | EFER_NXE;
  708                         wrmsr(MSR_EFER, msr);
  709                         pg_nx = PG_NX;
  710                 }
  711 #endif
  712                 break;
  713 #endif
  714         default:
  715                 break;
  716         }
  717         enable_sse();
  718 
  719         /*
  720          * CPUID with %eax = 1, %ebx returns
  721          * Bits 15-8: CLFLUSH line size
  722          *      (Value * 8 = cache line size in bytes)
  723          */
  724         if ((cpu_feature & CPUID_CLFSH) != 0)
  725                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
  726         /*
  727          * XXXKIB: (temporary) hack to work around traps generated
  728          * when CLFLUSHing APIC register window under virtualization
  729          * environments.  These environments tend to disable the
  730          * CPUID_SS feature even though the native CPU supports it.
  731          */
  732         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
  733         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
  734                 cpu_feature &= ~CPUID_CLFSH;
  735         /*
  736          * Allow to disable CLFLUSH feature manually by
  737          * hw.clflush_disable tunable.
  738          */
  739         if (hw_clflush_disable == 1)
  740                 cpu_feature &= ~CPUID_CLFSH;
  741 
  742 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  743         /*
  744          * OS should flush L1 cache by itself because no PC-98 supports
  745          * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
  746          * when need_pre_dma_flush = 1, use invd instruction after DMA
  747          * transfer when need_post_dma_flush = 1.  If your CPU upgrade
  748          * product supports hardware cache control, you can add the
  749          * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
  750          * This option eliminates unneeded cache flush instruction(s).
  751          */
  752         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
  753                 switch (cpu) {
  754 #ifdef I486_CPU
  755                 case CPU_486DLC:
  756                         need_post_dma_flush = 1;
  757                         break;
  758                 case CPU_M1SC:
  759                         need_pre_dma_flush = 1;
  760                         break;
  761                 case CPU_CY486DX:
  762                         need_pre_dma_flush = 1;
  763 #ifdef CPU_I486_ON_386
  764                         need_post_dma_flush = 1;
  765 #endif
  766                         break;
  767 #endif
  768                 default:
  769                         break;
  770                 }
  771         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
  772                 switch (cpu_id & 0xFF0) {
  773                 case 0x470:             /* Enhanced Am486DX2 WB */
  774                 case 0x490:             /* Enhanced Am486DX4 WB */
  775                 case 0x4F0:             /* Am5x86 WB */
  776                         need_pre_dma_flush = 1;
  777                         break;
  778                 }
  779         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
  780                 need_post_dma_flush = 1;
  781         } else {
  782 #ifdef CPU_I486_ON_386
  783                 need_pre_dma_flush = 1;
  784 #endif
  785         }
  786 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
  787 }
  788 
  789 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  790 /*
  791  * Enable write allocate feature of AMD processors.
  792  * Following two functions require the Maxmem variable being set.
  793  */
  794 void
  795 enable_K5_wt_alloc(void)
  796 {
  797         u_int64_t       msr;
  798         register_t      savecrit;
  799 
  800         /*
  801          * Write allocate is supported only on models 1, 2, and 3, with
  802          * a stepping of 4 or greater.
  803          */
  804         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
  805                 savecrit = intr_disable();
  806                 msr = rdmsr(0x83);              /* HWCR */
  807                 wrmsr(0x83, msr & !(0x10));
  808 
  809                 /*
  810                  * We have to tell the chip where the top of memory is,
  811                  * since video cards could have frame bufferes there,
  812                  * memory-mapped I/O could be there, etc.
  813                  */
  814                 if(Maxmem > 0)
  815                   msr = Maxmem / 16;
  816                 else
  817                   msr = 0;
  818                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
  819 #ifdef PC98
  820                 if (!(inb(0x43b) & 4)) {
  821                         wrmsr(0x86, 0x0ff00f0);
  822                         msr |= AMD_WT_ALLOC_PRE;
  823                 }
  824 #else
  825                 /*
  826                  * There is no way to know wheter 15-16M hole exists or not. 
  827                  * Therefore, we disable write allocate for this range.
  828                  */
  829                         wrmsr(0x86, 0x0ff00f0);
  830                         msr |= AMD_WT_ALLOC_PRE;
  831 #endif
  832                 wrmsr(0x85, msr);
  833 
  834                 msr=rdmsr(0x83);
  835                 wrmsr(0x83, msr|0x10); /* enable write allocate */
  836                 intr_restore(savecrit);
  837         }
  838 }
  839 
  840 void
  841 enable_K6_wt_alloc(void)
  842 {
  843         quad_t  size;
  844         u_int64_t       whcr;
  845         u_long  eflags;
  846 
  847         eflags = read_eflags();
  848         disable_intr();
  849         wbinvd();
  850 
  851 #ifdef CPU_DISABLE_CACHE
  852         /*
  853          * Certain K6-2 box becomes unstable when write allocation is
  854          * enabled.
  855          */
  856         /*
  857          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  858          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  859          * All other bits in TR12 have no effect on the processer's operation.
  860          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  861          * on the AMD-K6.
  862          */
  863         wrmsr(0x0000000e, (u_int64_t)0x0008);
  864 #endif
  865         /* Don't assume that memory size is aligned with 4M. */
  866         if (Maxmem > 0)
  867           size = ((Maxmem >> 8) + 3) >> 2;
  868         else
  869           size = 0;
  870 
  871         /* Limit is 508M bytes. */
  872         if (size > 0x7f)
  873                 size = 0x7f;
  874         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
  875 
  876 #if defined(PC98) || defined(NO_MEMORY_HOLE)
  877         if (whcr & (0x7fLL << 1)) {
  878 #ifdef PC98
  879                 /*
  880                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  881                  * 15-16M range.
  882                  */
  883                 if (!(inb(0x43b) & 4))
  884                         whcr &= ~0x0001LL;
  885                 else
  886 #endif
  887                         whcr |=  0x0001LL;
  888         }
  889 #else
  890         /*
  891          * There is no way to know wheter 15-16M hole exists or not. 
  892          * Therefore, we disable write allocate for this range.
  893          */
  894         whcr &= ~0x0001LL;
  895 #endif
  896         wrmsr(0x0c0000082, whcr);
  897 
  898         write_eflags(eflags);
  899 }
  900 
  901 void
  902 enable_K6_2_wt_alloc(void)
  903 {
  904         quad_t  size;
  905         u_int64_t       whcr;
  906         u_long  eflags;
  907 
  908         eflags = read_eflags();
  909         disable_intr();
  910         wbinvd();
  911 
  912 #ifdef CPU_DISABLE_CACHE
  913         /*
  914          * Certain K6-2 box becomes unstable when write allocation is
  915          * enabled.
  916          */
  917         /*
  918          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  919          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  920          * All other bits in TR12 have no effect on the processer's operation.
  921          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  922          * on the AMD-K6.
  923          */
  924         wrmsr(0x0000000e, (u_int64_t)0x0008);
  925 #endif
  926         /* Don't assume that memory size is aligned with 4M. */
  927         if (Maxmem > 0)
  928           size = ((Maxmem >> 8) + 3) >> 2;
  929         else
  930           size = 0;
  931 
  932         /* Limit is 4092M bytes. */
  933         if (size > 0x3fff)
  934                 size = 0x3ff;
  935         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
  936 
  937 #if defined(PC98) || defined(NO_MEMORY_HOLE)
  938         if (whcr & (0x3ffLL << 22)) {
  939 #ifdef PC98
  940                 /*
  941                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  942                  * 15-16M range.
  943                  */
  944                 if (!(inb(0x43b) & 4))
  945                         whcr &= ~(1LL << 16);
  946                 else
  947 #endif
  948                         whcr |=  1LL << 16;
  949         }
  950 #else
  951         /*
  952          * There is no way to know wheter 15-16M hole exists or not. 
  953          * Therefore, we disable write allocate for this range.
  954          */
  955         whcr &= ~(1LL << 16);
  956 #endif
  957         wrmsr(0x0c0000082, whcr);
  958 
  959         write_eflags(eflags);
  960 }
  961 #endif /* I585_CPU && CPU_WT_ALLOC */
  962 
  963 #include "opt_ddb.h"
  964 #ifdef DDB
  965 #include <ddb/ddb.h>
  966 
  967 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
  968 {
  969         u_long  eflags;
  970         u_int   cr0;
  971         u_char  ccr1, ccr2, ccr3;
  972         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
  973 
  974         cr0 = rcr0();
  975         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
  976                 eflags = read_eflags();
  977                 disable_intr();
  978 
  979 
  980                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
  981                         ccr0 = read_cyrix_reg(CCR0);
  982                 }
  983                 ccr1 = read_cyrix_reg(CCR1);
  984                 ccr2 = read_cyrix_reg(CCR2);
  985                 ccr3 = read_cyrix_reg(CCR3);
  986                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
  987                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
  988                         ccr4 = read_cyrix_reg(CCR4);
  989                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
  990                                 ccr5 = read_cyrix_reg(CCR5);
  991                         else
  992                                 pcr0 = read_cyrix_reg(PCR0);
  993                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
  994                 }
  995                 write_eflags(eflags);
  996 
  997                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
  998                         printf("CCR0=%x, ", (u_int)ccr0);
  999 
 1000                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
 1001                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
 1002                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 1003                         printf(", CCR4=%x, ", (u_int)ccr4);
 1004                         if (cpu == CPU_M1SC)
 1005                                 printf("PCR0=%x\n", pcr0);
 1006                         else
 1007                                 printf("CCR5=%x\n", ccr5);
 1008                 }
 1009         }
 1010         printf("CR0=%x\n", cr0);
 1011 }
 1012 #endif /* DDB */

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