1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46
47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
48 #define CPU_ENABLE_SSE
49 #endif
50
51 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
52 void enable_K5_wt_alloc(void);
53 void enable_K6_wt_alloc(void);
54 void enable_K6_2_wt_alloc(void);
55 #endif
56
57 #ifdef I486_CPU
58 static void init_5x86(void);
59 static void init_bluelightning(void);
60 static void init_486dlc(void);
61 static void init_cy486dx(void);
62 #ifdef CPU_I486_ON_386
63 static void init_i486_on_386(void);
64 #endif
65 static void init_6x86(void);
66 #endif /* I486_CPU */
67
68 #ifdef I686_CPU
69 static void init_6x86MX(void);
70 static void init_ppro(void);
71 static void init_mendocino(void);
72 #endif
73
74 static int hw_instruction_sse;
75 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
77 /*
78 * -1: automatic (default)
79 * 0: keep enable CLFLUSH
80 * 1: force disable CLFLUSH
81 */
82 static int hw_clflush_disable = -1;
83
84 /* Must *NOT* be BSS or locore will bzero these after setting them */
85 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
86 u_int cpu_feature = 0; /* Feature flags */
87 u_int cpu_feature2 = 0; /* Feature flags */
88 u_int amd_feature = 0; /* AMD feature flags */
89 u_int amd_feature2 = 0; /* AMD feature flags */
90 u_int amd_pminfo = 0; /* AMD advanced power management info */
91 u_int via_feature_rng = 0; /* VIA RNG features */
92 u_int via_feature_xcrypt = 0; /* VIA ACE features */
93 u_int cpu_high = 0; /* Highest arg to CPUID */
94 u_int cpu_id = 0; /* Stepping ID */
95 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
96 u_int cpu_procinfo2 = 0; /* Multicore info */
97 char cpu_vendor[20] = ""; /* CPU Origin code */
98 u_int cpu_vendor_id = 0; /* CPU vendor ID */
99 u_int cpu_clflush_line_size = 32;
100
101 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
102 &via_feature_rng, 0, "VIA RNG feature available in CPU");
103 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
104 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
105
106 #ifdef CPU_ENABLE_SSE
107 u_int cpu_fxsr; /* SSE enabled */
108 u_int cpu_mxcsr_mask; /* valid bits in mxcsr */
109 #endif
110
111 #ifdef I486_CPU
112 /*
113 * IBM Blue Lightning
114 */
115 static void
116 init_bluelightning(void)
117 {
118 register_t saveintr;
119
120 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
121 need_post_dma_flush = 1;
122 #endif
123
124 saveintr = intr_disable();
125
126 load_cr0(rcr0() | CR0_CD | CR0_NW);
127 invd();
128
129 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
130 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
131 #else
132 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
133 #endif
134 /* Enables 13MB and 0-640KB cache. */
135 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
136 #ifdef CPU_BLUELIGHTNING_3X
137 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
138 #else
139 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
140 #endif
141
142 /* Enable caching in CR0. */
143 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
144 invd();
145 intr_restore(saveintr);
146 }
147
148 /*
149 * Cyrix 486SLC/DLC/SR/DR series
150 */
151 static void
152 init_486dlc(void)
153 {
154 register_t saveintr;
155 u_char ccr0;
156
157 saveintr = intr_disable();
158 invd();
159
160 ccr0 = read_cyrix_reg(CCR0);
161 #ifndef CYRIX_CACHE_WORKS
162 ccr0 |= CCR0_NC1 | CCR0_BARB;
163 write_cyrix_reg(CCR0, ccr0);
164 invd();
165 #else
166 ccr0 &= ~CCR0_NC0;
167 #ifndef CYRIX_CACHE_REALLY_WORKS
168 ccr0 |= CCR0_NC1 | CCR0_BARB;
169 #else
170 ccr0 |= CCR0_NC1;
171 #endif
172 #ifdef CPU_DIRECT_MAPPED_CACHE
173 ccr0 |= CCR0_CO; /* Direct mapped mode. */
174 #endif
175 write_cyrix_reg(CCR0, ccr0);
176
177 /* Clear non-cacheable region. */
178 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
179 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
180 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
181 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
182
183 write_cyrix_reg(0, 0); /* dummy write */
184
185 /* Enable caching in CR0. */
186 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
187 invd();
188 #endif /* !CYRIX_CACHE_WORKS */
189 intr_restore(saveintr);
190 }
191
192
193 /*
194 * Cyrix 486S/DX series
195 */
196 static void
197 init_cy486dx(void)
198 {
199 register_t saveintr;
200 u_char ccr2;
201
202 saveintr = intr_disable();
203 invd();
204
205 ccr2 = read_cyrix_reg(CCR2);
206 #ifdef CPU_SUSP_HLT
207 ccr2 |= CCR2_SUSP_HLT;
208 #endif
209
210 #ifdef PC98
211 /* Enables WB cache interface pin and Lock NW bit in CR0. */
212 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
213 /* Unlock NW bit in CR0. */
214 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
215 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
216 #endif
217
218 write_cyrix_reg(CCR2, ccr2);
219 intr_restore(saveintr);
220 }
221
222
223 /*
224 * Cyrix 5x86
225 */
226 static void
227 init_5x86(void)
228 {
229 register_t saveintr;
230 u_char ccr2, ccr3, ccr4, pcr0;
231
232 saveintr = intr_disable();
233
234 load_cr0(rcr0() | CR0_CD | CR0_NW);
235 wbinvd();
236
237 (void)read_cyrix_reg(CCR3); /* dummy */
238
239 /* Initialize CCR2. */
240 ccr2 = read_cyrix_reg(CCR2);
241 ccr2 |= CCR2_WB;
242 #ifdef CPU_SUSP_HLT
243 ccr2 |= CCR2_SUSP_HLT;
244 #else
245 ccr2 &= ~CCR2_SUSP_HLT;
246 #endif
247 ccr2 |= CCR2_WT1;
248 write_cyrix_reg(CCR2, ccr2);
249
250 /* Initialize CCR4. */
251 ccr3 = read_cyrix_reg(CCR3);
252 write_cyrix_reg(CCR3, CCR3_MAPEN0);
253
254 ccr4 = read_cyrix_reg(CCR4);
255 ccr4 |= CCR4_DTE;
256 ccr4 |= CCR4_MEM;
257 #ifdef CPU_FASTER_5X86_FPU
258 ccr4 |= CCR4_FASTFPE;
259 #else
260 ccr4 &= ~CCR4_FASTFPE;
261 #endif
262 ccr4 &= ~CCR4_IOMASK;
263 /********************************************************************
264 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
265 * should be 0 for errata fix.
266 ********************************************************************/
267 #ifdef CPU_IORT
268 ccr4 |= CPU_IORT & CCR4_IOMASK;
269 #endif
270 write_cyrix_reg(CCR4, ccr4);
271
272 /* Initialize PCR0. */
273 /****************************************************************
274 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
275 * BTB_EN might make your system unstable.
276 ****************************************************************/
277 pcr0 = read_cyrix_reg(PCR0);
278 #ifdef CPU_RSTK_EN
279 pcr0 |= PCR0_RSTK;
280 #else
281 pcr0 &= ~PCR0_RSTK;
282 #endif
283 #ifdef CPU_BTB_EN
284 pcr0 |= PCR0_BTB;
285 #else
286 pcr0 &= ~PCR0_BTB;
287 #endif
288 #ifdef CPU_LOOP_EN
289 pcr0 |= PCR0_LOOP;
290 #else
291 pcr0 &= ~PCR0_LOOP;
292 #endif
293
294 /****************************************************************
295 * WARNING: if you use a memory mapped I/O device, don't use
296 * DISABLE_5X86_LSSER option, which may reorder memory mapped
297 * I/O access.
298 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
299 ****************************************************************/
300 #ifdef CPU_DISABLE_5X86_LSSER
301 pcr0 &= ~PCR0_LSSER;
302 #else
303 pcr0 |= PCR0_LSSER;
304 #endif
305 write_cyrix_reg(PCR0, pcr0);
306
307 /* Restore CCR3. */
308 write_cyrix_reg(CCR3, ccr3);
309
310 (void)read_cyrix_reg(0x80); /* dummy */
311
312 /* Unlock NW bit in CR0. */
313 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
314 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
315 /* Lock NW bit in CR0. */
316 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
317
318 intr_restore(saveintr);
319 }
320
321 #ifdef CPU_I486_ON_386
322 /*
323 * There are i486 based upgrade products for i386 machines.
324 * In this case, BIOS doesn't enable CPU cache.
325 */
326 static void
327 init_i486_on_386(void)
328 {
329 register_t saveintr;
330
331 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
332 need_post_dma_flush = 1;
333 #endif
334
335 saveintr = intr_disable();
336
337 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
338
339 intr_restore(saveintr);
340 }
341 #endif
342
343 /*
344 * Cyrix 6x86
345 *
346 * XXX - What should I do here? Please let me know.
347 */
348 static void
349 init_6x86(void)
350 {
351 register_t saveintr;
352 u_char ccr3, ccr4;
353
354 saveintr = intr_disable();
355
356 load_cr0(rcr0() | CR0_CD | CR0_NW);
357 wbinvd();
358
359 /* Initialize CCR0. */
360 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
361
362 /* Initialize CCR1. */
363 #ifdef CPU_CYRIX_NO_LOCK
364 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
365 #else
366 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
367 #endif
368
369 /* Initialize CCR2. */
370 #ifdef CPU_SUSP_HLT
371 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
372 #else
373 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
374 #endif
375
376 ccr3 = read_cyrix_reg(CCR3);
377 write_cyrix_reg(CCR3, CCR3_MAPEN0);
378
379 /* Initialize CCR4. */
380 ccr4 = read_cyrix_reg(CCR4);
381 ccr4 |= CCR4_DTE;
382 ccr4 &= ~CCR4_IOMASK;
383 #ifdef CPU_IORT
384 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
385 #else
386 write_cyrix_reg(CCR4, ccr4 | 7);
387 #endif
388
389 /* Initialize CCR5. */
390 #ifdef CPU_WT_ALLOC
391 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
392 #endif
393
394 /* Restore CCR3. */
395 write_cyrix_reg(CCR3, ccr3);
396
397 /* Unlock NW bit in CR0. */
398 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
399
400 /*
401 * Earlier revision of the 6x86 CPU could crash the system if
402 * L1 cache is in write-back mode.
403 */
404 if ((cyrix_did & 0xff00) > 0x1600)
405 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
406 else {
407 /* Revision 2.6 and lower. */
408 #ifdef CYRIX_CACHE_REALLY_WORKS
409 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
410 #else
411 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
412 #endif
413 }
414
415 /* Lock NW bit in CR0. */
416 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
417
418 intr_restore(saveintr);
419 }
420 #endif /* I486_CPU */
421
422 #ifdef I586_CPU
423 /*
424 * IDT WinChip C6/2/2A/2B/3
425 *
426 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
427 */
428 static void
429 init_winchip(void)
430 {
431 u_int regs[4];
432 uint64_t fcr;
433
434 fcr = rdmsr(0x0107);
435
436 /*
437 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
438 */
439 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
440 fcr &= ~(1ULL << 11);
441
442 /*
443 * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
444 */
445 if (CPUID_TO_MODEL(cpu_id) >= 8)
446 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
447
448 wrmsr(0x0107, fcr);
449 do_cpuid(1, regs);
450 cpu_feature = regs[3];
451 }
452 #endif
453
454 #ifdef I686_CPU
455 /*
456 * Cyrix 6x86MX (code-named M2)
457 *
458 * XXX - What should I do here? Please let me know.
459 */
460 static void
461 init_6x86MX(void)
462 {
463 register_t saveintr;
464 u_char ccr3, ccr4;
465
466 saveintr = intr_disable();
467
468 load_cr0(rcr0() | CR0_CD | CR0_NW);
469 wbinvd();
470
471 /* Initialize CCR0. */
472 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
473
474 /* Initialize CCR1. */
475 #ifdef CPU_CYRIX_NO_LOCK
476 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
477 #else
478 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
479 #endif
480
481 /* Initialize CCR2. */
482 #ifdef CPU_SUSP_HLT
483 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
484 #else
485 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
486 #endif
487
488 ccr3 = read_cyrix_reg(CCR3);
489 write_cyrix_reg(CCR3, CCR3_MAPEN0);
490
491 /* Initialize CCR4. */
492 ccr4 = read_cyrix_reg(CCR4);
493 ccr4 &= ~CCR4_IOMASK;
494 #ifdef CPU_IORT
495 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
496 #else
497 write_cyrix_reg(CCR4, ccr4 | 7);
498 #endif
499
500 /* Initialize CCR5. */
501 #ifdef CPU_WT_ALLOC
502 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
503 #endif
504
505 /* Restore CCR3. */
506 write_cyrix_reg(CCR3, ccr3);
507
508 /* Unlock NW bit in CR0. */
509 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
510
511 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
512
513 /* Lock NW bit in CR0. */
514 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
515
516 intr_restore(saveintr);
517 }
518
519 static void
520 init_ppro(void)
521 {
522 u_int64_t apicbase;
523
524 /*
525 * Local APIC should be disabled if it is not going to be used.
526 */
527 apicbase = rdmsr(MSR_APICBASE);
528 apicbase &= ~APICBASE_ENABLED;
529 wrmsr(MSR_APICBASE, apicbase);
530 }
531
532 /*
533 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
534 * L2 cache).
535 */
536 static void
537 init_mendocino(void)
538 {
539 #ifdef CPU_PPRO2CELERON
540 register_t saveintr;
541 u_int64_t bbl_cr_ctl3;
542
543 saveintr = intr_disable();
544
545 load_cr0(rcr0() | CR0_CD | CR0_NW);
546 wbinvd();
547
548 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
549
550 /* If the L2 cache is configured, do nothing. */
551 if (!(bbl_cr_ctl3 & 1)) {
552 bbl_cr_ctl3 = 0x134052bLL;
553
554 /* Set L2 Cache Latency (Default: 5). */
555 #ifdef CPU_CELERON_L2_LATENCY
556 #if CPU_L2_LATENCY > 15
557 #error invalid CPU_L2_LATENCY.
558 #endif
559 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
560 #else
561 bbl_cr_ctl3 |= 5 << 1;
562 #endif
563 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
564 }
565
566 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
567 intr_restore(saveintr);
568 #endif /* CPU_PPRO2CELERON */
569 }
570
571 /*
572 * Initialize special VIA features
573 */
574 static void
575 init_via(void)
576 {
577 u_int regs[4], val;
578 uint64_t fcr;
579
580 /*
581 * Explicitly enable CX8 and PGE on C3.
582 *
583 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
584 */
585 if (CPUID_TO_MODEL(cpu_id) <= 9)
586 fcr = (1 << 1) | (1 << 7);
587 else
588 fcr = 0;
589
590 /*
591 * Check extended CPUID for PadLock features.
592 *
593 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
594 */
595 do_cpuid(0xc0000000, regs);
596 if (regs[0] >= 0xc0000001) {
597 do_cpuid(0xc0000001, regs);
598 val = regs[3];
599 } else
600 val = 0;
601
602 /* Enable RNG if present. */
603 if ((val & VIA_CPUID_HAS_RNG) != 0) {
604 via_feature_rng = VIA_HAS_RNG;
605 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
606 }
607
608 /* Enable PadLock if present. */
609 if ((val & VIA_CPUID_HAS_ACE) != 0)
610 via_feature_xcrypt |= VIA_HAS_AES;
611 if ((val & VIA_CPUID_HAS_ACE2) != 0)
612 via_feature_xcrypt |= VIA_HAS_AESCTR;
613 if ((val & VIA_CPUID_HAS_PHE) != 0)
614 via_feature_xcrypt |= VIA_HAS_SHA;
615 if ((val & VIA_CPUID_HAS_PMM) != 0)
616 via_feature_xcrypt |= VIA_HAS_MM;
617 if (via_feature_xcrypt != 0)
618 fcr |= 1 << 28;
619
620 wrmsr(0x1107, rdmsr(0x1107) | fcr);
621 }
622
623 #endif /* I686_CPU */
624
625 #if defined(I586_CPU) || defined(I686_CPU)
626 static void
627 init_transmeta(void)
628 {
629 u_int regs[0];
630
631 /* Expose all hidden features. */
632 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
633 do_cpuid(1, regs);
634 cpu_feature = regs[3];
635 }
636 #endif
637
638 /*
639 * Initialize CR4 (Control register 4) to enable SSE instructions.
640 */
641 void
642 enable_sse(void)
643 {
644 #if defined(CPU_ENABLE_SSE)
645 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
646 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
647 cpu_fxsr = hw_instruction_sse = 1;
648 }
649 #endif
650 }
651
652 extern int elf32_nxstack;
653
654 void
655 initializecpu(void)
656 {
657
658 switch (cpu) {
659 #ifdef I486_CPU
660 case CPU_BLUE:
661 init_bluelightning();
662 break;
663 case CPU_486DLC:
664 init_486dlc();
665 break;
666 case CPU_CY486DX:
667 init_cy486dx();
668 break;
669 case CPU_M1SC:
670 init_5x86();
671 break;
672 #ifdef CPU_I486_ON_386
673 case CPU_486:
674 init_i486_on_386();
675 break;
676 #endif
677 case CPU_M1:
678 init_6x86();
679 break;
680 #endif /* I486_CPU */
681 #ifdef I586_CPU
682 case CPU_586:
683 switch (cpu_vendor_id) {
684 case CPU_VENDOR_CENTAUR:
685 init_winchip();
686 break;
687 case CPU_VENDOR_TRANSMETA:
688 init_transmeta();
689 break;
690 }
691 break;
692 #endif
693 #ifdef I686_CPU
694 case CPU_M2:
695 init_6x86MX();
696 break;
697 case CPU_686:
698 switch (cpu_vendor_id) {
699 case CPU_VENDOR_INTEL:
700 switch (cpu_id & 0xff0) {
701 case 0x610:
702 init_ppro();
703 break;
704 case 0x660:
705 init_mendocino();
706 break;
707 }
708 break;
709 #ifdef CPU_ATHLON_SSE_HACK
710 case CPU_VENDOR_AMD:
711 /*
712 * Sometimes the BIOS doesn't enable SSE instructions.
713 * According to AMD document 20734, the mobile
714 * Duron, the (mobile) Athlon 4 and the Athlon MP
715 * support SSE. These correspond to cpu_id 0x66X
716 * or 0x67X.
717 */
718 if ((cpu_feature & CPUID_XMM) == 0 &&
719 ((cpu_id & ~0xf) == 0x660 ||
720 (cpu_id & ~0xf) == 0x670 ||
721 (cpu_id & ~0xf) == 0x680)) {
722 u_int regs[4];
723 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
724 do_cpuid(1, regs);
725 cpu_feature = regs[3];
726 }
727 break;
728 #endif
729 case CPU_VENDOR_CENTAUR:
730 init_via();
731 break;
732 case CPU_VENDOR_TRANSMETA:
733 init_transmeta();
734 break;
735 }
736 #ifdef PAE
737 if ((amd_feature & AMDID_NX) != 0) {
738 uint64_t msr;
739
740 msr = rdmsr(MSR_EFER) | EFER_NXE;
741 wrmsr(MSR_EFER, msr);
742 pg_nx = PG_NX;
743 elf32_nxstack = 1;
744 }
745 #endif
746 break;
747 #endif
748 default:
749 break;
750 }
751 enable_sse();
752
753 /*
754 * CPUID with %eax = 1, %ebx returns
755 * Bits 15-8: CLFLUSH line size
756 * (Value * 8 = cache line size in bytes)
757 */
758 if ((cpu_feature & CPUID_CLFSH) != 0)
759 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
760 /*
761 * XXXKIB: (temporary) hack to work around traps generated
762 * when CLFLUSHing APIC register window under virtualization
763 * environments. These environments tend to disable the
764 * CPUID_SS feature even though the native CPU supports it.
765 */
766 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
767 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
768 cpu_feature &= ~CPUID_CLFSH;
769 /*
770 * Allow to disable CLFLUSH feature manually by
771 * hw.clflush_disable tunable.
772 */
773 if (hw_clflush_disable == 1)
774 cpu_feature &= ~CPUID_CLFSH;
775
776 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
777 /*
778 * OS should flush L1 cache by itself because no PC-98 supports
779 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
780 * when need_pre_dma_flush = 1, use invd instruction after DMA
781 * transfer when need_post_dma_flush = 1. If your CPU upgrade
782 * product supports hardware cache control, you can add the
783 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
784 * This option eliminates unneeded cache flush instruction(s).
785 */
786 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
787 switch (cpu) {
788 #ifdef I486_CPU
789 case CPU_486DLC:
790 need_post_dma_flush = 1;
791 break;
792 case CPU_M1SC:
793 need_pre_dma_flush = 1;
794 break;
795 case CPU_CY486DX:
796 need_pre_dma_flush = 1;
797 #ifdef CPU_I486_ON_386
798 need_post_dma_flush = 1;
799 #endif
800 break;
801 #endif
802 default:
803 break;
804 }
805 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
806 switch (cpu_id & 0xFF0) {
807 case 0x470: /* Enhanced Am486DX2 WB */
808 case 0x490: /* Enhanced Am486DX4 WB */
809 case 0x4F0: /* Am5x86 WB */
810 need_pre_dma_flush = 1;
811 break;
812 }
813 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
814 need_post_dma_flush = 1;
815 } else {
816 #ifdef CPU_I486_ON_386
817 need_pre_dma_flush = 1;
818 #endif
819 }
820 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
821 }
822
823 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
824 /*
825 * Enable write allocate feature of AMD processors.
826 * Following two functions require the Maxmem variable being set.
827 */
828 void
829 enable_K5_wt_alloc(void)
830 {
831 u_int64_t msr;
832 register_t saveintr;
833
834 /*
835 * Write allocate is supported only on models 1, 2, and 3, with
836 * a stepping of 4 or greater.
837 */
838 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
839 saveintr = intr_disable();
840 msr = rdmsr(0x83); /* HWCR */
841 wrmsr(0x83, msr & !(0x10));
842
843 /*
844 * We have to tell the chip where the top of memory is,
845 * since video cards could have frame bufferes there,
846 * memory-mapped I/O could be there, etc.
847 */
848 if(Maxmem > 0)
849 msr = Maxmem / 16;
850 else
851 msr = 0;
852 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
853 #ifdef PC98
854 if (!(inb(0x43b) & 4)) {
855 wrmsr(0x86, 0x0ff00f0);
856 msr |= AMD_WT_ALLOC_PRE;
857 }
858 #else
859 /*
860 * There is no way to know wheter 15-16M hole exists or not.
861 * Therefore, we disable write allocate for this range.
862 */
863 wrmsr(0x86, 0x0ff00f0);
864 msr |= AMD_WT_ALLOC_PRE;
865 #endif
866 wrmsr(0x85, msr);
867
868 msr=rdmsr(0x83);
869 wrmsr(0x83, msr|0x10); /* enable write allocate */
870 intr_restore(saveintr);
871 }
872 }
873
874 void
875 enable_K6_wt_alloc(void)
876 {
877 quad_t size;
878 u_int64_t whcr;
879 register_t saveintr;
880
881 saveintr = intr_disable();
882 wbinvd();
883
884 #ifdef CPU_DISABLE_CACHE
885 /*
886 * Certain K6-2 box becomes unstable when write allocation is
887 * enabled.
888 */
889 /*
890 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
891 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
892 * All other bits in TR12 have no effect on the processer's operation.
893 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
894 * on the AMD-K6.
895 */
896 wrmsr(0x0000000e, (u_int64_t)0x0008);
897 #endif
898 /* Don't assume that memory size is aligned with 4M. */
899 if (Maxmem > 0)
900 size = ((Maxmem >> 8) + 3) >> 2;
901 else
902 size = 0;
903
904 /* Limit is 508M bytes. */
905 if (size > 0x7f)
906 size = 0x7f;
907 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
908
909 #if defined(PC98) || defined(NO_MEMORY_HOLE)
910 if (whcr & (0x7fLL << 1)) {
911 #ifdef PC98
912 /*
913 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
914 * 15-16M range.
915 */
916 if (!(inb(0x43b) & 4))
917 whcr &= ~0x0001LL;
918 else
919 #endif
920 whcr |= 0x0001LL;
921 }
922 #else
923 /*
924 * There is no way to know wheter 15-16M hole exists or not.
925 * Therefore, we disable write allocate for this range.
926 */
927 whcr &= ~0x0001LL;
928 #endif
929 wrmsr(0x0c0000082, whcr);
930
931 intr_restore(saveintr);
932 }
933
934 void
935 enable_K6_2_wt_alloc(void)
936 {
937 quad_t size;
938 u_int64_t whcr;
939 register_t saveintr;
940
941 saveintr = intr_disable();
942 wbinvd();
943
944 #ifdef CPU_DISABLE_CACHE
945 /*
946 * Certain K6-2 box becomes unstable when write allocation is
947 * enabled.
948 */
949 /*
950 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
951 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
952 * All other bits in TR12 have no effect on the processer's operation.
953 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
954 * on the AMD-K6.
955 */
956 wrmsr(0x0000000e, (u_int64_t)0x0008);
957 #endif
958 /* Don't assume that memory size is aligned with 4M. */
959 if (Maxmem > 0)
960 size = ((Maxmem >> 8) + 3) >> 2;
961 else
962 size = 0;
963
964 /* Limit is 4092M bytes. */
965 if (size > 0x3fff)
966 size = 0x3ff;
967 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
968
969 #if defined(PC98) || defined(NO_MEMORY_HOLE)
970 if (whcr & (0x3ffLL << 22)) {
971 #ifdef PC98
972 /*
973 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
974 * 15-16M range.
975 */
976 if (!(inb(0x43b) & 4))
977 whcr &= ~(1LL << 16);
978 else
979 #endif
980 whcr |= 1LL << 16;
981 }
982 #else
983 /*
984 * There is no way to know wheter 15-16M hole exists or not.
985 * Therefore, we disable write allocate for this range.
986 */
987 whcr &= ~(1LL << 16);
988 #endif
989 wrmsr(0x0c0000082, whcr);
990
991 intr_restore(saveintr);
992 }
993 #endif /* I585_CPU && CPU_WT_ALLOC */
994
995 #include "opt_ddb.h"
996 #ifdef DDB
997 #include <ddb/ddb.h>
998
999 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1000 {
1001 register_t saveintr;
1002 u_int cr0;
1003 u_char ccr1, ccr2, ccr3;
1004 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1005
1006 cr0 = rcr0();
1007 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1008 saveintr = intr_disable();
1009
1010
1011 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1012 ccr0 = read_cyrix_reg(CCR0);
1013 }
1014 ccr1 = read_cyrix_reg(CCR1);
1015 ccr2 = read_cyrix_reg(CCR2);
1016 ccr3 = read_cyrix_reg(CCR3);
1017 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1018 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1019 ccr4 = read_cyrix_reg(CCR4);
1020 if ((cpu == CPU_M1) || (cpu == CPU_M2))
1021 ccr5 = read_cyrix_reg(CCR5);
1022 else
1023 pcr0 = read_cyrix_reg(PCR0);
1024 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
1025 }
1026 intr_restore(saveintr);
1027
1028 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1029 printf("CCR0=%x, ", (u_int)ccr0);
1030
1031 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1032 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1033 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1034 printf(", CCR4=%x, ", (u_int)ccr4);
1035 if (cpu == CPU_M1SC)
1036 printf("PCR0=%x\n", pcr0);
1037 else
1038 printf("CCR5=%x\n", ccr5);
1039 }
1040 }
1041 printf("CR0=%x\n", cr0);
1042 }
1043 #endif /* DDB */
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