1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/6.3/sys/i386/i386/intr_machdep.c 173941 2007-11-26 15:42:43Z scottl $
30 */
31
32 /*
33 * Machine dependent interrupt code for i386. For the i386, we have to
34 * deal with different PICs. Thus, we use the passed in vector to lookup
35 * an interrupt source associated with that vector. The interrupt source
36 * describes which PIC the source belongs to and includes methods to handle
37 * that source.
38 */
39
40 #include "opt_ddb.h"
41
42 #include <sys/param.h>
43 #include <sys/bus.h>
44 #include <sys/interrupt.h>
45 #include <sys/lock.h>
46 #include <sys/ktr.h>
47 #include <sys/kernel.h>
48 #include <sys/mutex.h>
49 #include <sys/proc.h>
50 #include <sys/syslog.h>
51 #include <sys/systm.h>
52 #include <machine/clock.h>
53 #include <machine/intr_machdep.h>
54 #ifdef DDB
55 #include <ddb/ddb.h>
56 #endif
57
58 #define MAX_STRAY_LOG 5
59
60 typedef void (*mask_fn)(void *);
61
62 static int intrcnt_index;
63 static struct intsrc *interrupt_sources[NUM_IO_INTS];
64 static struct mtx intr_table_lock;
65 static STAILQ_HEAD(, pic) pics;
66
67 #ifdef SMP
68 static int assign_cpu;
69
70 static void intr_assign_next_cpu(struct intsrc *isrc);
71 #endif
72
73 static void intr_init(void *__dummy);
74 static int intr_pic_registered(struct pic *pic);
75 static void intrcnt_setname(const char *name, int index);
76 static void intrcnt_updatename(struct intsrc *is);
77 static void intrcnt_register(struct intsrc *is);
78
79 static int
80 intr_pic_registered(struct pic *pic)
81 {
82 struct pic *p;
83
84 STAILQ_FOREACH(p, &pics, pics) {
85 if (p == pic)
86 return (1);
87 }
88 return (0);
89 }
90
91 /*
92 * Register a new interrupt controller (PIC). This is to support suspend
93 * and resume where we suspend/resume controllers rather than individual
94 * sources. This also allows controllers with no active sources (such as
95 * 8259As in a system using the APICs) to participate in suspend and resume.
96 */
97 int
98 intr_register_pic(struct pic *pic)
99 {
100 int error;
101
102 mtx_lock_spin(&intr_table_lock);
103 if (intr_pic_registered(pic))
104 error = EBUSY;
105 else {
106 STAILQ_INSERT_TAIL(&pics, pic, pics);
107 error = 0;
108 }
109 mtx_unlock_spin(&intr_table_lock);
110 return (error);
111 }
112
113 /*
114 * Register a new interrupt source with the global interrupt system.
115 * The global interrupts need to be disabled when this function is
116 * called.
117 */
118 int
119 intr_register_source(struct intsrc *isrc)
120 {
121 int error, vector;
122
123 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
124 vector = isrc->is_pic->pic_vector(isrc);
125 if (interrupt_sources[vector] != NULL)
126 return (EEXIST);
127 error = intr_event_create(&isrc->is_event, isrc, 0,
128 (mask_fn)isrc->is_pic->pic_enable_source, "irq%d:", vector);
129 if (error)
130 return (error);
131 mtx_lock_spin(&intr_table_lock);
132 if (interrupt_sources[vector] != NULL) {
133 mtx_unlock_spin(&intr_table_lock);
134 intr_event_destroy(isrc->is_event);
135 return (EEXIST);
136 }
137 intrcnt_register(isrc);
138 interrupt_sources[vector] = isrc;
139 isrc->is_enabled = 0;
140 mtx_unlock_spin(&intr_table_lock);
141 return (0);
142 }
143
144 struct intsrc *
145 intr_lookup_source(int vector)
146 {
147
148 return (interrupt_sources[vector]);
149 }
150
151 int
152 intr_add_handler(const char *name, int vector, driver_intr_t handler,
153 void *arg, enum intr_type flags, void **cookiep)
154 {
155 struct intsrc *isrc;
156 int error;
157
158 isrc = intr_lookup_source(vector);
159 if (isrc == NULL)
160 return (EINVAL);
161 error = intr_event_add_handler(isrc->is_event, name, handler, arg,
162 intr_priority(flags), flags, cookiep);
163 if (error == 0) {
164 intrcnt_updatename(isrc);
165 mtx_lock_spin(&intr_table_lock);
166 if (!isrc->is_enabled) {
167 isrc->is_enabled = 1;
168 #ifdef SMP
169 if (assign_cpu)
170 intr_assign_next_cpu(isrc);
171 #endif
172 mtx_unlock_spin(&intr_table_lock);
173 isrc->is_pic->pic_enable_intr(isrc);
174 } else
175 mtx_unlock_spin(&intr_table_lock);
176 isrc->is_pic->pic_enable_source(isrc);
177 }
178 return (error);
179 }
180
181 int
182 intr_remove_handler(void *cookie)
183 {
184 int error;
185
186 error = intr_event_remove_handler(cookie);
187 #ifdef XXX
188 if (error == 0)
189 intrcnt_updatename(/* XXX */);
190 #endif
191 return (error);
192 }
193
194 int
195 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
196 {
197 struct intsrc *isrc;
198
199 isrc = intr_lookup_source(vector);
200 if (isrc == NULL)
201 return (EINVAL);
202 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
203 }
204
205 void
206 intr_execute_handlers(struct intsrc *isrc, struct intrframe *iframe)
207 {
208 struct thread *td;
209 struct intr_event *ie;
210 struct intr_handler *ih;
211 int error, vector, thread;
212
213 td = curthread;
214
215 /*
216 * We count software interrupts when we process them. The
217 * code here follows previous practice, but there's an
218 * argument for counting hardware interrupts when they're
219 * processed too.
220 */
221 (*isrc->is_count)++;
222 PCPU_LAZY_INC(cnt.v_intr);
223
224 ie = isrc->is_event;
225
226 /*
227 * XXX: We assume that IRQ 0 is only used for the ISA timer
228 * device (clk).
229 */
230 vector = isrc->is_pic->pic_vector(isrc);
231 if (vector == 0)
232 clkintr_pending = 1;
233
234 /*
235 * For stray interrupts, mask and EOI the source, bump the
236 * stray count, and log the condition.
237 */
238 if (ie == NULL || TAILQ_EMPTY(&ie->ie_handlers)) {
239 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
240 (*isrc->is_straycount)++;
241 if (*isrc->is_straycount < MAX_STRAY_LOG)
242 log(LOG_ERR, "stray irq%d\n", vector);
243 else if (*isrc->is_straycount == MAX_STRAY_LOG)
244 log(LOG_CRIT,
245 "too many stray irq %d's: not logging anymore\n",
246 vector);
247 return;
248 }
249
250 /*
251 * Execute fast interrupt handlers directly.
252 * To support clock handlers, if a handler registers
253 * with a NULL argument, then we pass it a pointer to
254 * an intrframe as its argument.
255 */
256 td->td_intr_nesting_level++;
257 thread = 0;
258 critical_enter();
259 TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
260 if (!(ih->ih_flags & IH_FAST)) {
261 thread = 1;
262 continue;
263 }
264 CTR4(KTR_INTR, "%s: exec %p(%p) for %s", __func__,
265 ih->ih_handler, ih->ih_argument == NULL ? iframe :
266 ih->ih_argument, ih->ih_name);
267 if (ih->ih_argument == NULL)
268 ih->ih_handler(iframe);
269 else
270 ih->ih_handler(ih->ih_argument);
271 }
272
273 /*
274 * If there are any threaded handlers that need to run,
275 * mask the source as well as sending it an EOI. Otherwise,
276 * just send it an EOI but leave it unmasked.
277 */
278 if (thread)
279 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
280 else
281 isrc->is_pic->pic_eoi_source(isrc);
282
283 /* Schedule the ithread if needed. */
284 if (thread) {
285 error = intr_event_schedule_thread(ie);
286 KASSERT(error == 0, ("bad stray interrupt"));
287 }
288 critical_exit();
289 td->td_intr_nesting_level--;
290 }
291
292 void
293 intr_resume(void)
294 {
295 struct pic *pic;
296
297 mtx_lock_spin(&intr_table_lock);
298 STAILQ_FOREACH(pic, &pics, pics) {
299 if (pic->pic_resume != NULL)
300 pic->pic_resume(pic);
301 }
302 mtx_unlock_spin(&intr_table_lock);
303 }
304
305 void
306 intr_suspend(void)
307 {
308 struct pic *pic;
309
310 mtx_lock_spin(&intr_table_lock);
311 STAILQ_FOREACH(pic, &pics, pics) {
312 if (pic->pic_suspend != NULL)
313 pic->pic_suspend(pic);
314 }
315 mtx_unlock_spin(&intr_table_lock);
316 }
317
318 static void
319 intrcnt_setname(const char *name, int index)
320 {
321
322 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
323 MAXCOMLEN, name);
324 }
325
326 static void
327 intrcnt_updatename(struct intsrc *is)
328 {
329
330 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
331 }
332
333 static void
334 intrcnt_register(struct intsrc *is)
335 {
336 char straystr[MAXCOMLEN + 1];
337
338 /* mtx_assert(&intr_table_lock, MA_OWNED); */
339 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
340 is->is_index = intrcnt_index;
341 intrcnt_index += 2;
342 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
343 is->is_pic->pic_vector(is));
344 intrcnt_updatename(is);
345 is->is_count = &intrcnt[is->is_index];
346 intrcnt_setname(straystr, is->is_index + 1);
347 is->is_straycount = &intrcnt[is->is_index + 1];
348 }
349
350 void
351 intrcnt_add(const char *name, u_long **countp)
352 {
353
354 mtx_lock_spin(&intr_table_lock);
355 *countp = &intrcnt[intrcnt_index];
356 intrcnt_setname(name, intrcnt_index);
357 intrcnt_index++;
358 mtx_unlock_spin(&intr_table_lock);
359 }
360
361 static void
362 intr_init(void *dummy __unused)
363 {
364
365 intrcnt_setname("???", 0);
366 intrcnt_index = 1;
367 STAILQ_INIT(&pics);
368 mtx_init(&intr_table_lock, "intr table", NULL, MTX_SPIN);
369 }
370 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL)
371
372 #ifdef DDB
373 /*
374 * Dump data about interrupt handlers
375 */
376 DB_SHOW_COMMAND(irqs, db_show_irqs)
377 {
378 struct intsrc **isrc;
379 int i, quit, verbose;
380
381 quit = 0;
382 if (strcmp(modif, "v") == 0)
383 verbose = 1;
384 else
385 verbose = 0;
386 isrc = interrupt_sources;
387 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
388 for (i = 0; i < NUM_IO_INTS && !quit; i++, isrc++)
389 if (*isrc != NULL)
390 db_dump_intr_event((*isrc)->is_event, verbose);
391 }
392 #endif
393
394 #ifdef SMP
395 /*
396 * Support for balancing interrupt sources across CPUs. For now we just
397 * allocate CPUs round-robin.
398 */
399
400 static u_int cpu_apic_ids[MAXCPU];
401 static int current_cpu, num_cpus;
402
403 static void
404 intr_assign_next_cpu(struct intsrc *isrc)
405 {
406 struct pic *pic;
407 u_int apic_id;
408
409 /*
410 * Assign this source to a local APIC in a round-robin fashion.
411 */
412 pic = isrc->is_pic;
413 apic_id = cpu_apic_ids[current_cpu];
414 current_cpu++;
415 if (current_cpu >= num_cpus)
416 current_cpu = 0;
417 pic->pic_assign_cpu(isrc, apic_id);
418 }
419
420 /*
421 * Add a local APIC ID to our list of valid local APIC IDs that can
422 * be destinations of interrupts.
423 */
424 void
425 intr_add_cpu(u_int apic_id)
426 {
427
428 if (bootverbose)
429 printf("INTR: Adding local APIC %d as a target\n", apic_id);
430 if (num_cpus >= MAXCPU)
431 panic("WARNING: Local APIC IDs exhausted!");
432 cpu_apic_ids[num_cpus] = apic_id;
433 num_cpus++;
434 }
435
436 /*
437 * Distribute all the interrupt sources among the available CPUs once the
438 * AP's have been launched.
439 */
440 static void
441 intr_shuffle_irqs(void *arg __unused)
442 {
443 struct intsrc *isrc;
444 int i;
445
446 /* Don't bother on UP. */
447 if (num_cpus <= 1)
448 return;
449
450 /* Round-robin assign a CPU to each enabled source. */
451 mtx_lock_spin(&intr_table_lock);
452 assign_cpu = 1;
453 for (i = 0; i < NUM_IO_INTS; i++) {
454 isrc = interrupt_sources[i];
455 if (isrc != NULL && isrc->is_enabled)
456 intr_assign_next_cpu(isrc);
457 }
458 mtx_unlock_spin(&intr_table_lock);
459 }
460 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs, NULL)
461 #endif
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