The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/intr_machdep.c

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: releng/9.0/sys/i386/i386/intr_machdep.c 224187 2011-07-18 15:19:40Z attilio $
   30  */
   31 
   32 /*
   33  * Machine dependent interrupt code for i386.  For the i386, we have to
   34  * deal with different PICs.  Thus, we use the passed in vector to lookup
   35  * an interrupt source associated with that vector.  The interrupt source
   36  * describes which PIC the source belongs to and includes methods to handle
   37  * that source.
   38  */
   39 
   40 #include "opt_ddb.h"
   41 
   42 #include <sys/param.h>
   43 #include <sys/bus.h>
   44 #include <sys/interrupt.h>
   45 #include <sys/ktr.h>
   46 #include <sys/kernel.h>
   47 #include <sys/lock.h>
   48 #include <sys/mutex.h>
   49 #include <sys/proc.h>
   50 #include <sys/smp.h>
   51 #include <sys/syslog.h>
   52 #include <sys/systm.h>
   53 #include <machine/clock.h>
   54 #include <machine/intr_machdep.h>
   55 #include <machine/smp.h>
   56 #ifdef DDB
   57 #include <ddb/ddb.h>
   58 #endif
   59 
   60 #define MAX_STRAY_LOG   5
   61 
   62 typedef void (*mask_fn)(void *);
   63 
   64 static int intrcnt_index;
   65 static struct intsrc *interrupt_sources[NUM_IO_INTS];
   66 static struct mtx intr_table_lock;
   67 static struct mtx intrcnt_lock;
   68 static STAILQ_HEAD(, pic) pics;
   69 
   70 #ifdef SMP
   71 static int assign_cpu;
   72 #endif
   73 
   74 u_long intrcnt[INTRCNT_COUNT];
   75 char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
   76 size_t sintrcnt = sizeof(intrcnt);
   77 size_t sintrnames = sizeof(intrnames);
   78 
   79 static int      intr_assign_cpu(void *arg, u_char cpu);
   80 static void     intr_disable_src(void *arg);
   81 static void     intr_init(void *__dummy);
   82 static int      intr_pic_registered(struct pic *pic);
   83 static void     intrcnt_setname(const char *name, int index);
   84 static void     intrcnt_updatename(struct intsrc *is);
   85 static void     intrcnt_register(struct intsrc *is);
   86 
   87 static int
   88 intr_pic_registered(struct pic *pic)
   89 {
   90         struct pic *p;
   91 
   92         STAILQ_FOREACH(p, &pics, pics) {
   93                 if (p == pic)
   94                         return (1);
   95         }
   96         return (0);
   97 }
   98 
   99 /*
  100  * Register a new interrupt controller (PIC).  This is to support suspend
  101  * and resume where we suspend/resume controllers rather than individual
  102  * sources.  This also allows controllers with no active sources (such as
  103  * 8259As in a system using the APICs) to participate in suspend and resume.
  104  */
  105 int
  106 intr_register_pic(struct pic *pic)
  107 {
  108         int error;
  109 
  110         mtx_lock(&intr_table_lock);
  111         if (intr_pic_registered(pic))
  112                 error = EBUSY;
  113         else {
  114                 STAILQ_INSERT_TAIL(&pics, pic, pics);
  115                 error = 0;
  116         }
  117         mtx_unlock(&intr_table_lock);
  118         return (error);
  119 }
  120 
  121 /*
  122  * Register a new interrupt source with the global interrupt system.
  123  * The global interrupts need to be disabled when this function is
  124  * called.
  125  */
  126 int
  127 intr_register_source(struct intsrc *isrc)
  128 {
  129         int error, vector;
  130 
  131         KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
  132         vector = isrc->is_pic->pic_vector(isrc);
  133         if (interrupt_sources[vector] != NULL)
  134                 return (EEXIST);
  135         error = intr_event_create(&isrc->is_event, isrc, 0, vector,
  136             intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
  137             (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
  138             vector);
  139         if (error)
  140                 return (error);
  141         mtx_lock(&intr_table_lock);
  142         if (interrupt_sources[vector] != NULL) {
  143                 mtx_unlock(&intr_table_lock);
  144                 intr_event_destroy(isrc->is_event);
  145                 return (EEXIST);
  146         }
  147         intrcnt_register(isrc);
  148         interrupt_sources[vector] = isrc;
  149         isrc->is_handlers = 0;
  150         mtx_unlock(&intr_table_lock);
  151         return (0);
  152 }
  153 
  154 struct intsrc *
  155 intr_lookup_source(int vector)
  156 {
  157 
  158         return (interrupt_sources[vector]);
  159 }
  160 
  161 int
  162 intr_add_handler(const char *name, int vector, driver_filter_t filter,
  163     driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
  164 {
  165         struct intsrc *isrc;
  166         int error;
  167 
  168         isrc = intr_lookup_source(vector);
  169         if (isrc == NULL)
  170                 return (EINVAL);
  171         error = intr_event_add_handler(isrc->is_event, name, filter, handler,
  172             arg, intr_priority(flags), flags, cookiep);
  173         if (error == 0) {
  174                 mtx_lock(&intr_table_lock);
  175                 intrcnt_updatename(isrc);
  176                 isrc->is_handlers++;
  177                 if (isrc->is_handlers == 1) {
  178                         isrc->is_pic->pic_enable_intr(isrc);
  179                         isrc->is_pic->pic_enable_source(isrc);
  180                 }
  181                 mtx_unlock(&intr_table_lock);
  182         }
  183         return (error);
  184 }
  185 
  186 int
  187 intr_remove_handler(void *cookie)
  188 {
  189         struct intsrc *isrc;
  190         int error;
  191 
  192         isrc = intr_handler_source(cookie);
  193         error = intr_event_remove_handler(cookie);
  194         if (error == 0) {
  195                 mtx_lock(&intr_table_lock);
  196                 isrc->is_handlers--;
  197                 if (isrc->is_handlers == 0) {
  198                         isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
  199                         isrc->is_pic->pic_disable_intr(isrc);
  200                 }
  201                 intrcnt_updatename(isrc);
  202                 mtx_unlock(&intr_table_lock);
  203         }
  204         return (error);
  205 }
  206 
  207 int
  208 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
  209 {
  210         struct intsrc *isrc;
  211 
  212         isrc = intr_lookup_source(vector);
  213         if (isrc == NULL)
  214                 return (EINVAL);
  215         return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
  216 }
  217 
  218 static void
  219 intr_disable_src(void *arg)
  220 {
  221         struct intsrc *isrc;
  222 
  223         isrc = arg;
  224         isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
  225 }
  226 
  227 void
  228 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
  229 {
  230         struct intr_event *ie;
  231         int vector;
  232 
  233         /*
  234          * We count software interrupts when we process them.  The
  235          * code here follows previous practice, but there's an
  236          * argument for counting hardware interrupts when they're
  237          * processed too.
  238          */
  239         (*isrc->is_count)++;
  240         PCPU_INC(cnt.v_intr);
  241 
  242         ie = isrc->is_event;
  243 
  244         /*
  245          * XXX: We assume that IRQ 0 is only used for the ISA timer
  246          * device (clk).
  247          */
  248         vector = isrc->is_pic->pic_vector(isrc);
  249         if (vector == 0)
  250                 clkintr_pending = 1;
  251 
  252         /*
  253          * For stray interrupts, mask and EOI the source, bump the
  254          * stray count, and log the condition.
  255          */
  256         if (intr_event_handle(ie, frame) != 0) {
  257                 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
  258                 (*isrc->is_straycount)++;
  259                 if (*isrc->is_straycount < MAX_STRAY_LOG)
  260                         log(LOG_ERR, "stray irq%d\n", vector);
  261                 else if (*isrc->is_straycount == MAX_STRAY_LOG)
  262                         log(LOG_CRIT,
  263                             "too many stray irq %d's: not logging anymore\n",
  264                             vector);
  265         }
  266 }
  267 
  268 void
  269 intr_resume(void)
  270 {
  271         struct pic *pic;
  272 
  273         mtx_lock(&intr_table_lock);
  274         STAILQ_FOREACH(pic, &pics, pics) {
  275                 if (pic->pic_resume != NULL)
  276                         pic->pic_resume(pic);
  277         }
  278         mtx_unlock(&intr_table_lock);
  279 }
  280 
  281 void
  282 intr_suspend(void)
  283 {
  284         struct pic *pic;
  285 
  286         mtx_lock(&intr_table_lock);
  287         STAILQ_FOREACH(pic, &pics, pics) {
  288                 if (pic->pic_suspend != NULL)
  289                         pic->pic_suspend(pic);
  290         }
  291         mtx_unlock(&intr_table_lock);
  292 }
  293 
  294 static int
  295 intr_assign_cpu(void *arg, u_char cpu)
  296 {
  297 #ifdef SMP
  298         struct intsrc *isrc;
  299         int error;
  300 
  301         /*
  302          * Don't do anything during early boot.  We will pick up the
  303          * assignment once the APs are started.
  304          */
  305         if (assign_cpu && cpu != NOCPU) {
  306                 isrc = arg;
  307                 mtx_lock(&intr_table_lock);
  308                 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
  309                 mtx_unlock(&intr_table_lock);
  310         } else
  311                 error = 0;
  312         return (error);
  313 #else
  314         return (EOPNOTSUPP);
  315 #endif
  316 }
  317 
  318 static void
  319 intrcnt_setname(const char *name, int index)
  320 {
  321 
  322         snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
  323             MAXCOMLEN, name);
  324 }
  325 
  326 static void
  327 intrcnt_updatename(struct intsrc *is)
  328 {
  329 
  330         intrcnt_setname(is->is_event->ie_fullname, is->is_index);
  331 }
  332 
  333 static void
  334 intrcnt_register(struct intsrc *is)
  335 {
  336         char straystr[MAXCOMLEN + 1];
  337 
  338         KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
  339         mtx_lock_spin(&intrcnt_lock);
  340         is->is_index = intrcnt_index;
  341         intrcnt_index += 2;
  342         snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
  343             is->is_pic->pic_vector(is));
  344         intrcnt_updatename(is);
  345         is->is_count = &intrcnt[is->is_index];
  346         intrcnt_setname(straystr, is->is_index + 1);
  347         is->is_straycount = &intrcnt[is->is_index + 1];
  348         mtx_unlock_spin(&intrcnt_lock);
  349 }
  350 
  351 void
  352 intrcnt_add(const char *name, u_long **countp)
  353 {
  354 
  355         mtx_lock_spin(&intrcnt_lock);
  356         *countp = &intrcnt[intrcnt_index];
  357         intrcnt_setname(name, intrcnt_index);
  358         intrcnt_index++;
  359         mtx_unlock_spin(&intrcnt_lock);
  360 }
  361 
  362 static void
  363 intr_init(void *dummy __unused)
  364 {
  365 
  366         intrcnt_setname("???", 0);
  367         intrcnt_index = 1;
  368         STAILQ_INIT(&pics);
  369         mtx_init(&intr_table_lock, "intr sources", NULL, MTX_DEF);
  370         mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
  371 }
  372 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
  373 
  374 /* Add a description to an active interrupt handler. */
  375 int
  376 intr_describe(u_int vector, void *ih, const char *descr)
  377 {
  378         struct intsrc *isrc;
  379         int error;
  380 
  381         isrc = intr_lookup_source(vector);
  382         if (isrc == NULL)
  383                 return (EINVAL);
  384         error = intr_event_describe_handler(isrc->is_event, ih, descr);
  385         if (error)
  386                 return (error);
  387         intrcnt_updatename(isrc);
  388         return (0);
  389 }
  390 
  391 #ifdef DDB
  392 /*
  393  * Dump data about interrupt handlers
  394  */
  395 DB_SHOW_COMMAND(irqs, db_show_irqs)
  396 {
  397         struct intsrc **isrc;
  398         int i, verbose;
  399 
  400         if (strcmp(modif, "v") == 0)
  401                 verbose = 1;
  402         else
  403                 verbose = 0;
  404         isrc = interrupt_sources;
  405         for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
  406                 if (*isrc != NULL)
  407                         db_dump_intr_event((*isrc)->is_event, verbose);
  408 }
  409 #endif
  410 
  411 #ifdef SMP
  412 /*
  413  * Support for balancing interrupt sources across CPUs.  For now we just
  414  * allocate CPUs round-robin.
  415  */
  416 
  417 static cpuset_t intr_cpus;
  418 static int current_cpu;
  419 
  420 /*
  421  * Return the CPU that the next interrupt source should use.  For now
  422  * this just returns the next local APIC according to round-robin.
  423  */
  424 u_int
  425 intr_next_cpu(void)
  426 {
  427         u_int apic_id;
  428 
  429         /* Leave all interrupts on the BSP during boot. */
  430         if (!assign_cpu)
  431                 return (PCPU_GET(apic_id));
  432 
  433         mtx_lock_spin(&icu_lock);
  434         apic_id = cpu_apic_ids[current_cpu];
  435         do {
  436                 current_cpu++;
  437                 if (current_cpu > mp_maxid)
  438                         current_cpu = 0;
  439         } while (!CPU_ISSET(current_cpu, &intr_cpus));
  440         mtx_unlock_spin(&icu_lock);
  441         return (apic_id);
  442 }
  443 
  444 /* Attempt to bind the specified IRQ to the specified CPU. */
  445 int
  446 intr_bind(u_int vector, u_char cpu)
  447 {
  448         struct intsrc *isrc;
  449 
  450         isrc = intr_lookup_source(vector);
  451         if (isrc == NULL)
  452                 return (EINVAL);
  453         return (intr_event_bind(isrc->is_event, cpu));
  454 }
  455 
  456 /*
  457  * Add a CPU to our mask of valid CPUs that can be destinations of
  458  * interrupts.
  459  */
  460 void
  461 intr_add_cpu(u_int cpu)
  462 {
  463 
  464         if (cpu >= MAXCPU)
  465                 panic("%s: Invalid CPU ID", __func__);
  466         if (bootverbose)
  467                 printf("INTR: Adding local APIC %d as a target\n",
  468                     cpu_apic_ids[cpu]);
  469 
  470         CPU_SET(cpu, &intr_cpus);
  471 }
  472 
  473 /*
  474  * Distribute all the interrupt sources among the available CPUs once the
  475  * AP's have been launched.
  476  */
  477 static void
  478 intr_shuffle_irqs(void *arg __unused)
  479 {
  480         struct intsrc *isrc;
  481         int i;
  482 
  483 #ifdef XEN
  484         /*
  485          * Doesn't work yet
  486          */
  487         return;
  488 #endif
  489 
  490         /* The BSP is always a valid target. */
  491         CPU_SETOF(0, &intr_cpus);
  492 
  493         /* Don't bother on UP. */
  494         if (mp_ncpus == 1)
  495                 return;
  496 
  497         /* Round-robin assign a CPU to each enabled source. */
  498         mtx_lock(&intr_table_lock);
  499         assign_cpu = 1;
  500         for (i = 0; i < NUM_IO_INTS; i++) {
  501                 isrc = interrupt_sources[i];
  502                 if (isrc != NULL && isrc->is_handlers > 0) {
  503                         /*
  504                          * If this event is already bound to a CPU,
  505                          * then assign the source to that CPU instead
  506                          * of picking one via round-robin.  Note that
  507                          * this is careful to only advance the
  508                          * round-robin if the CPU assignment succeeds.
  509                          */
  510                         if (isrc->is_event->ie_cpu != NOCPU)
  511                                 (void)isrc->is_pic->pic_assign_cpu(isrc,
  512                                     cpu_apic_ids[isrc->is_event->ie_cpu]);
  513                         else if (isrc->is_pic->pic_assign_cpu(isrc,
  514                                 cpu_apic_ids[current_cpu]) == 0)
  515                                 (void)intr_next_cpu();
  516 
  517                 }
  518         }
  519         mtx_unlock(&intr_table_lock);
  520 }
  521 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
  522     NULL);
  523 #else
  524 /*
  525  * Always route interrupts to the current processor in the UP case.
  526  */
  527 u_int
  528 intr_next_cpu(void)
  529 {
  530 
  531         return (PCPU_GET(apic_id));
  532 }
  533 #endif

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