Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/i386/io_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_isa.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/sysctl.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 51 #include <machine/apicreg.h> 52 #include <machine/frame.h> 53 #include <machine/intr_machdep.h> 54 #include <machine/apicvar.h> 55 #include <machine/resource.h> 56 #include <machine/segments.h> 57 58 #define IOAPIC_ISA_INTS 16 59 #define IOAPIC_MEM_REGION 32 60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 62 63 #define IRQ_EXTINT (NUM_IO_INTS + 1) 64 #define IRQ_NMI (NUM_IO_INTS + 2) 65 #define IRQ_SMI (NUM_IO_INTS + 3) 66 #define IRQ_DISABLED (NUM_IO_INTS + 4) 67 68 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 69 70 /* 71 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 72 * as laid out in the ACPI System Interrupt number model where each I/O 73 * APIC has a contiguous chunk of the System Interrupt address space. 74 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 75 * IRQs behave as PCI IRQs by default. We also assume that the pin for 76 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 77 * configuration of individual pins as indicated by their tables. 78 * 79 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 80 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 81 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 82 */ 83 84 struct ioapic_intsrc { 85 struct intsrc io_intsrc; 86 u_int io_irq; 87 u_int io_intpin:8; 88 u_int io_vector:8; 89 u_int io_cpu:8; 90 u_int io_activehi:1; 91 u_int io_edgetrigger:1; 92 u_int io_masked:1; 93 int io_bus:4; 94 uint32_t io_lowreg; 95 }; 96 97 struct ioapic { 98 struct pic io_pic; 99 u_int io_id:8; /* logical ID */ 100 u_int io_apic_id:4; 101 u_int io_intbase:8; /* System Interrupt base */ 102 u_int io_numintr:8; 103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 104 vm_paddr_t io_paddr; 105 STAILQ_ENTRY(ioapic) io_next; 106 struct ioapic_intsrc io_pins[0]; 107 }; 108 109 static u_int ioapic_read(volatile ioapic_t *apic, int reg); 110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 111 static const char *ioapic_bus_string(int bus_type); 112 static void ioapic_print_irq(struct ioapic_intsrc *intpin); 113 static void ioapic_enable_source(struct intsrc *isrc); 114 static void ioapic_disable_source(struct intsrc *isrc, int eoi); 115 static void ioapic_eoi_source(struct intsrc *isrc); 116 static void ioapic_enable_intr(struct intsrc *isrc); 117 static void ioapic_disable_intr(struct intsrc *isrc); 118 static int ioapic_vector(struct intsrc *isrc); 119 static int ioapic_source_pending(struct intsrc *isrc); 120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 121 enum intr_polarity pol); 122 static void ioapic_resume(struct pic *pic); 123 static void ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 125 126 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 127 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source, 128 ioapic_eoi_source, ioapic_enable_intr, 129 ioapic_disable_intr, ioapic_vector, 130 ioapic_source_pending, NULL, ioapic_resume, 131 ioapic_config_intr, ioapic_assign_cpu }; 132 133 static int next_ioapic_base; 134 static u_int next_id; 135 136 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options"); 137 static int enable_extint; 138 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 139 "Enable the ExtINT pin in the first I/O APIC"); 140 TUNABLE_INT("hw.apic.enable_extint", &enable_extint); 141 142 static __inline void 143 _ioapic_eoi_source(struct intsrc *isrc) 144 { 145 lapic_eoi(); 146 } 147 148 static u_int 149 ioapic_read(volatile ioapic_t *apic, int reg) 150 { 151 152 mtx_assert(&icu_lock, MA_OWNED); 153 apic->ioregsel = reg; 154 return (apic->iowin); 155 } 156 157 static void 158 ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 159 { 160 161 mtx_assert(&icu_lock, MA_OWNED); 162 apic->ioregsel = reg; 163 apic->iowin = val; 164 } 165 166 static const char * 167 ioapic_bus_string(int bus_type) 168 { 169 170 switch (bus_type) { 171 case APIC_BUS_ISA: 172 return ("ISA"); 173 case APIC_BUS_EISA: 174 return ("EISA"); 175 case APIC_BUS_PCI: 176 return ("PCI"); 177 default: 178 return ("unknown"); 179 } 180 } 181 182 static void 183 ioapic_print_irq(struct ioapic_intsrc *intpin) 184 { 185 186 switch (intpin->io_irq) { 187 case IRQ_DISABLED: 188 printf("disabled"); 189 break; 190 case IRQ_EXTINT: 191 printf("ExtINT"); 192 break; 193 case IRQ_NMI: 194 printf("NMI"); 195 break; 196 case IRQ_SMI: 197 printf("SMI"); 198 break; 199 default: 200 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus), 201 intpin->io_irq); 202 } 203 } 204 205 static void 206 ioapic_enable_source(struct intsrc *isrc) 207 { 208 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 209 struct ioapic *io = (struct ioapic *)isrc->is_pic; 210 uint32_t flags; 211 212 mtx_lock_spin(&icu_lock); 213 if (intpin->io_masked) { 214 flags = intpin->io_lowreg & ~IOART_INTMASK; 215 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 216 flags); 217 intpin->io_masked = 0; 218 } 219 mtx_unlock_spin(&icu_lock); 220 } 221 222 static void 223 ioapic_disable_source(struct intsrc *isrc, int eoi) 224 { 225 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 226 struct ioapic *io = (struct ioapic *)isrc->is_pic; 227 uint32_t flags; 228 229 mtx_lock_spin(&icu_lock); 230 if (!intpin->io_masked && !intpin->io_edgetrigger) { 231 flags = intpin->io_lowreg | IOART_INTMSET; 232 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 233 flags); 234 intpin->io_masked = 1; 235 } 236 237 if (eoi == PIC_EOI) 238 _ioapic_eoi_source(isrc); 239 240 mtx_unlock_spin(&icu_lock); 241 } 242 243 static void 244 ioapic_eoi_source(struct intsrc *isrc) 245 { 246 247 _ioapic_eoi_source(isrc); 248 } 249 250 /* 251 * Completely program an intpin based on the data in its interrupt source 252 * structure. 253 */ 254 static void 255 ioapic_program_intpin(struct ioapic_intsrc *intpin) 256 { 257 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 258 uint32_t low, high, value; 259 260 /* 261 * If a pin is completely invalid or if it is valid but hasn't 262 * been enabled yet, just ensure that the pin is masked. 263 */ 264 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS && 265 intpin->io_vector == 0)) { 266 mtx_lock_spin(&icu_lock); 267 low = ioapic_read(io->io_addr, 268 IOAPIC_REDTBL_LO(intpin->io_intpin)); 269 if ((low & IOART_INTMASK) == IOART_INTMCLR) 270 ioapic_write(io->io_addr, 271 IOAPIC_REDTBL_LO(intpin->io_intpin), 272 low | IOART_INTMSET); 273 mtx_unlock_spin(&icu_lock); 274 return; 275 } 276 277 /* Set the destination. */ 278 low = IOART_DESTPHY; 279 high = intpin->io_cpu << APIC_ID_SHIFT; 280 281 /* Program the rest of the low word. */ 282 if (intpin->io_edgetrigger) 283 low |= IOART_TRGREDG; 284 else 285 low |= IOART_TRGRLVL; 286 if (intpin->io_activehi) 287 low |= IOART_INTAHI; 288 else 289 low |= IOART_INTALO; 290 if (intpin->io_masked) 291 low |= IOART_INTMSET; 292 switch (intpin->io_irq) { 293 case IRQ_EXTINT: 294 KASSERT(intpin->io_edgetrigger, 295 ("ExtINT not edge triggered")); 296 low |= IOART_DELEXINT; 297 break; 298 case IRQ_NMI: 299 KASSERT(intpin->io_edgetrigger, 300 ("NMI not edge triggered")); 301 low |= IOART_DELNMI; 302 break; 303 case IRQ_SMI: 304 KASSERT(intpin->io_edgetrigger, 305 ("SMI not edge triggered")); 306 low |= IOART_DELSMI; 307 break; 308 default: 309 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 310 intpin->io_irq)); 311 low |= IOART_DELFIXED | intpin->io_vector; 312 } 313 314 /* Write the values to the APIC. */ 315 mtx_lock_spin(&icu_lock); 316 intpin->io_lowreg = low; 317 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 318 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); 319 value &= ~IOART_DEST; 320 value |= high; 321 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); 322 mtx_unlock_spin(&icu_lock); 323 } 324 325 static void 326 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 327 { 328 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 329 struct ioapic *io = (struct ioapic *)isrc->is_pic; 330 331 intpin->io_cpu = apic_id; 332 if (bootverbose) { 333 printf("ioapic%u: Assigning ", io->io_id); 334 ioapic_print_irq(intpin); 335 printf(" to local APIC %u\n", intpin->io_cpu); 336 } 337 ioapic_program_intpin(intpin); 338 } 339 340 static void 341 ioapic_enable_intr(struct intsrc *isrc) 342 { 343 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 344 struct ioapic *io = (struct ioapic *)isrc->is_pic; 345 346 if (intpin->io_vector == 0) { 347 /* 348 * Allocate an APIC vector for this interrupt pin. Once 349 * we have a vector we program the interrupt pin. 350 */ 351 intpin->io_vector = apic_alloc_vector(intpin->io_irq); 352 if (bootverbose) { 353 printf("ioapic%u: routing intpin %u (", io->io_id, 354 intpin->io_intpin); 355 ioapic_print_irq(intpin); 356 printf(") to vector %u\n", intpin->io_vector); 357 } 358 ioapic_program_intpin(intpin); 359 apic_enable_vector(intpin->io_vector); 360 } 361 } 362 363 static void 364 ioapic_disable_intr(struct intsrc *isrc) 365 { 366 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 367 u_int vector; 368 369 if (intpin->io_vector != 0) { 370 /* Mask this interrupt pin and free its APIC vector. */ 371 vector = intpin->io_vector; 372 apic_disable_vector(vector); 373 intpin->io_masked = 1; 374 intpin->io_vector = 0; 375 ioapic_program_intpin(intpin); 376 apic_free_vector(vector, intpin->io_irq); 377 } 378 } 379 380 static int 381 ioapic_vector(struct intsrc *isrc) 382 { 383 struct ioapic_intsrc *pin; 384 385 pin = (struct ioapic_intsrc *)isrc; 386 return (pin->io_irq); 387 } 388 389 static int 390 ioapic_source_pending(struct intsrc *isrc) 391 { 392 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 393 394 if (intpin->io_vector == 0) 395 return 0; 396 return (lapic_intr_pending(intpin->io_vector)); 397 } 398 399 static int 400 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 401 enum intr_polarity pol) 402 { 403 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 404 struct ioapic *io = (struct ioapic *)isrc->is_pic; 405 int changed; 406 407 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 408 ("%s: Conforming trigger or polarity\n", __func__)); 409 410 /* 411 * EISA interrupts always use active high polarity, so don't allow 412 * them to be set to active low. 413 * 414 * XXX: Should we write to the ELCR if the trigger mode changes for 415 * an EISA IRQ or an ISA IRQ with the ELCR present? 416 */ 417 if (intpin->io_bus == APIC_BUS_EISA) 418 pol = INTR_POLARITY_HIGH; 419 changed = 0; 420 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 421 if (bootverbose) 422 printf("ioapic%u: Changing trigger for pin %u to %s\n", 423 io->io_id, intpin->io_intpin, 424 trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 425 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 426 changed++; 427 } 428 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 429 if (bootverbose) 430 printf("ioapic%u: Changing polarity for pin %u to %s\n", 431 io->io_id, intpin->io_intpin, 432 pol == INTR_POLARITY_HIGH ? "high" : "low"); 433 intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 434 changed++; 435 } 436 if (changed) 437 ioapic_program_intpin(intpin); 438 return (0); 439 } 440 441 static void 442 ioapic_resume(struct pic *pic) 443 { 444 struct ioapic *io = (struct ioapic *)pic; 445 int i; 446 447 for (i = 0; i < io->io_numintr; i++) 448 ioapic_program_intpin(&io->io_pins[i]); 449 } 450 451 /* 452 * Create a plain I/O APIC object. 453 */ 454 void * 455 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 456 { 457 struct ioapic *io; 458 struct ioapic_intsrc *intpin; 459 volatile ioapic_t *apic; 460 u_int numintr, i; 461 uint32_t value; 462 463 /* Map the register window so we can access the device. */ 464 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 465 mtx_lock_spin(&icu_lock); 466 value = ioapic_read(apic, IOAPIC_VER); 467 mtx_unlock_spin(&icu_lock); 468 469 /* If it's version register doesn't seem to work, punt. */ 470 if (value == 0xffffffff) { 471 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION); 472 return (NULL); 473 } 474 475 /* Determine the number of vectors and set the APIC ID. */ 476 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 477 io = malloc(sizeof(struct ioapic) + 478 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 479 io->io_pic = ioapic_template; 480 mtx_lock_spin(&icu_lock); 481 io->io_id = next_id++; 482 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 483 if (apic_id != -1 && io->io_apic_id != apic_id) { 484 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT); 485 mtx_unlock_spin(&icu_lock); 486 io->io_apic_id = apic_id; 487 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id, 488 apic_id); 489 } else 490 mtx_unlock_spin(&icu_lock); 491 if (intbase == -1) { 492 intbase = next_ioapic_base; 493 printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 494 intbase); 495 } else if (intbase != next_ioapic_base && bootverbose) 496 printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 497 io->io_id, intbase, next_ioapic_base); 498 io->io_intbase = intbase; 499 next_ioapic_base = intbase + numintr; 500 io->io_numintr = numintr; 501 io->io_addr = apic; 502 io->io_paddr = addr; 503 504 /* 505 * Initialize pins. Start off with interrupts disabled. Default 506 * to active-hi and edge-triggered for ISA interrupts and active-lo 507 * and level-triggered for all others. 508 */ 509 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 510 mtx_lock_spin(&icu_lock); 511 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 512 intpin->io_intsrc.is_pic = (struct pic *)io; 513 intpin->io_intpin = i; 514 intpin->io_irq = intbase + i; 515 516 /* 517 * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 518 * Assume that pins 1-15 are ISA interrupts and that all 519 * other pins are PCI interrupts. 520 */ 521 if (intpin->io_irq == 0) 522 ioapic_set_extint(io, i); 523 else if (intpin->io_irq < IOAPIC_ISA_INTS) { 524 intpin->io_bus = APIC_BUS_ISA; 525 intpin->io_activehi = 1; 526 intpin->io_edgetrigger = 1; 527 intpin->io_masked = 1; 528 } else { 529 intpin->io_bus = APIC_BUS_PCI; 530 intpin->io_activehi = 0; 531 intpin->io_edgetrigger = 0; 532 intpin->io_masked = 1; 533 } 534 535 /* 536 * Route interrupts to the BSP by default. Interrupts may 537 * be routed to other CPUs later after they are enabled. 538 */ 539 intpin->io_cpu = PCPU_GET(apic_id); 540 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 541 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 542 } 543 mtx_unlock_spin(&icu_lock); 544 545 return (io); 546 } 547 548 int 549 ioapic_get_vector(void *cookie, u_int pin) 550 { 551 struct ioapic *io; 552 553 io = (struct ioapic *)cookie; 554 if (pin >= io->io_numintr) 555 return (-1); 556 return (io->io_pins[pin].io_irq); 557 } 558 559 int 560 ioapic_disable_pin(void *cookie, u_int pin) 561 { 562 struct ioapic *io; 563 564 io = (struct ioapic *)cookie; 565 if (pin >= io->io_numintr) 566 return (EINVAL); 567 if (io->io_pins[pin].io_irq == IRQ_DISABLED) 568 return (EINVAL); 569 io->io_pins[pin].io_irq = IRQ_DISABLED; 570 if (bootverbose) 571 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 572 return (0); 573 } 574 575 int 576 ioapic_remap_vector(void *cookie, u_int pin, int vector) 577 { 578 struct ioapic *io; 579 580 io = (struct ioapic *)cookie; 581 if (pin >= io->io_numintr || vector < 0) 582 return (EINVAL); 583 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 584 return (EINVAL); 585 io->io_pins[pin].io_irq = vector; 586 if (bootverbose) 587 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 588 vector, pin); 589 return (0); 590 } 591 592 int 593 ioapic_set_bus(void *cookie, u_int pin, int bus_type) 594 { 595 struct ioapic *io; 596 597 if (bus_type < 0 || bus_type > APIC_BUS_MAX) 598 return (EINVAL); 599 io = (struct ioapic *)cookie; 600 if (pin >= io->io_numintr) 601 return (EINVAL); 602 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 603 return (EINVAL); 604 if (io->io_pins[pin].io_bus == bus_type) 605 return (0); 606 io->io_pins[pin].io_bus = bus_type; 607 if (bootverbose) 608 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 609 ioapic_bus_string(bus_type)); 610 return (0); 611 } 612 613 int 614 ioapic_set_nmi(void *cookie, u_int pin) 615 { 616 struct ioapic *io; 617 618 io = (struct ioapic *)cookie; 619 if (pin >= io->io_numintr) 620 return (EINVAL); 621 if (io->io_pins[pin].io_irq == IRQ_NMI) 622 return (0); 623 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 624 return (EINVAL); 625 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 626 io->io_pins[pin].io_irq = IRQ_NMI; 627 io->io_pins[pin].io_masked = 0; 628 io->io_pins[pin].io_edgetrigger = 1; 629 io->io_pins[pin].io_activehi = 1; 630 if (bootverbose) 631 printf("ioapic%u: Routing NMI -> intpin %d\n", 632 io->io_id, pin); 633 return (0); 634 } 635 636 int 637 ioapic_set_smi(void *cookie, u_int pin) 638 { 639 struct ioapic *io; 640 641 io = (struct ioapic *)cookie; 642 if (pin >= io->io_numintr) 643 return (EINVAL); 644 if (io->io_pins[pin].io_irq == IRQ_SMI) 645 return (0); 646 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 647 return (EINVAL); 648 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 649 io->io_pins[pin].io_irq = IRQ_SMI; 650 io->io_pins[pin].io_masked = 0; 651 io->io_pins[pin].io_edgetrigger = 1; 652 io->io_pins[pin].io_activehi = 1; 653 if (bootverbose) 654 printf("ioapic%u: Routing SMI -> intpin %d\n", 655 io->io_id, pin); 656 return (0); 657 } 658 659 int 660 ioapic_set_extint(void *cookie, u_int pin) 661 { 662 struct ioapic *io; 663 664 io = (struct ioapic *)cookie; 665 if (pin >= io->io_numintr) 666 return (EINVAL); 667 if (io->io_pins[pin].io_irq == IRQ_EXTINT) 668 return (0); 669 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 670 return (EINVAL); 671 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 672 io->io_pins[pin].io_irq = IRQ_EXTINT; 673 if (enable_extint) 674 io->io_pins[pin].io_masked = 0; 675 else 676 io->io_pins[pin].io_masked = 1; 677 io->io_pins[pin].io_edgetrigger = 1; 678 io->io_pins[pin].io_activehi = 1; 679 if (bootverbose) 680 printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 681 io->io_id, pin); 682 return (0); 683 } 684 685 int 686 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 687 { 688 struct ioapic *io; 689 int activehi; 690 691 io = (struct ioapic *)cookie; 692 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 693 return (EINVAL); 694 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 695 return (EINVAL); 696 activehi = (pol == INTR_POLARITY_HIGH); 697 if (io->io_pins[pin].io_activehi == activehi) 698 return (0); 699 io->io_pins[pin].io_activehi = activehi; 700 if (bootverbose) 701 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 702 pol == INTR_POLARITY_HIGH ? "high" : "low"); 703 return (0); 704 } 705 706 int 707 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 708 { 709 struct ioapic *io; 710 int edgetrigger; 711 712 io = (struct ioapic *)cookie; 713 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 714 return (EINVAL); 715 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 716 return (EINVAL); 717 edgetrigger = (trigger == INTR_TRIGGER_EDGE); 718 if (io->io_pins[pin].io_edgetrigger == edgetrigger) 719 return (0); 720 io->io_pins[pin].io_edgetrigger = edgetrigger; 721 if (bootverbose) 722 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 723 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 724 return (0); 725 } 726 727 /* 728 * Register a complete I/O APIC object with the interrupt subsystem. 729 */ 730 void 731 ioapic_register(void *cookie) 732 { 733 struct ioapic_intsrc *pin; 734 struct ioapic *io; 735 volatile ioapic_t *apic; 736 uint32_t flags; 737 int i; 738 739 io = (struct ioapic *)cookie; 740 apic = io->io_addr; 741 mtx_lock_spin(&icu_lock); 742 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 743 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 744 mtx_unlock_spin(&icu_lock); 745 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n", 746 io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 747 io->io_intbase + io->io_numintr - 1); 748 749 /* Register valid pins as interrupt sources. */ 750 intr_register_pic(&io->io_pic); 751 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 752 if (pin->io_irq < NUM_IO_INTS) 753 intr_register_source(&pin->io_intsrc); 754 } 755 756 /* A simple new-bus driver to consume PCI I/O APIC devices. */ 757 static int 758 ioapic_pci_probe(device_t dev) 759 { 760 761 if (pci_get_class(dev) == PCIC_BASEPERIPH && 762 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 763 switch (pci_get_progif(dev)) { 764 case PCIP_BASEPERIPH_PIC_IO_APIC: 765 device_set_desc(dev, "IO APIC"); 766 break; 767 case PCIP_BASEPERIPH_PIC_IOX_APIC: 768 device_set_desc(dev, "IO(x) APIC"); 769 break; 770 default: 771 return (ENXIO); 772 } 773 device_quiet(dev); 774 return (-10000); 775 } 776 return (ENXIO); 777 } 778 779 static int 780 ioapic_pci_attach(device_t dev) 781 { 782 783 return (0); 784 } 785 786 static device_method_t ioapic_pci_methods[] = { 787 /* Device interface */ 788 DEVMETHOD(device_probe, ioapic_pci_probe), 789 DEVMETHOD(device_attach, ioapic_pci_attach), 790 791 { 0, 0 } 792 }; 793 794 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 795 796 static devclass_t ioapic_devclass; 797 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0); 798 799 /* 800 * A new-bus driver to consume the memory resources associated with 801 * the APICs in the system. On some systems ACPI or PnPBIOS system 802 * resource devices may already claim these resources. To keep from 803 * breaking those devices, we attach ourself to the nexus device after 804 * legacy0 and acpi0 and ignore any allocation failures. 805 */ 806 static void 807 apic_identify(driver_t *driver, device_t parent) 808 { 809 810 /* 811 * Add at order 12. acpi0 is probed at order 10 and legacy0 812 * is probed at order 11. 813 */ 814 if (lapic_paddr != 0) 815 BUS_ADD_CHILD(parent, 12, "apic", 0); 816 } 817 818 static int 819 apic_probe(device_t dev) 820 { 821 822 device_set_desc(dev, "APIC resources"); 823 device_quiet(dev); 824 return (0); 825 } 826 827 static void 828 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 829 { 830 int error; 831 832 #ifdef PAE 833 /* 834 * Resources use long's to track resources, so we can't 835 * include memory regions above 4GB. 836 */ 837 if (base >= ~0ul) 838 return; 839 #endif 840 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 841 if (error) 842 panic("apic_add_resource: resource %d failed set with %d", rid, 843 error); 844 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 845 } 846 847 static int 848 apic_attach(device_t dev) 849 { 850 struct ioapic *io; 851 int i; 852 853 /* Reserve the local APIC. */ 854 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t)); 855 i = 1; 856 STAILQ_FOREACH(io, &ioapic_list, io_next) { 857 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 858 i++; 859 } 860 return (0); 861 } 862 863 static device_method_t apic_methods[] = { 864 /* Device interface */ 865 DEVMETHOD(device_identify, apic_identify), 866 DEVMETHOD(device_probe, apic_probe), 867 DEVMETHOD(device_attach, apic_attach), 868 869 { 0, 0 } 870 }; 871 872 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 873 874 static devclass_t apic_devclass; 875 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
Cache object: f7de5fe0c5d32ea3f7ee597356c7d4c2
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