The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/local_apic.c

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * Copyright (c) 1996, by Steve Passe
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. The name of the developer may NOT be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 /*
   31  * Local APIC support on Pentium and later processors.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD$");
   36 
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/bus.h>
   40 #include <sys/kernel.h>
   41 #include <sys/pcpu.h>
   42 
   43 #include <vm/vm.h>
   44 #include <vm/pmap.h>
   45 
   46 #include <machine/apicreg.h>
   47 #include <machine/cputypes.h>
   48 #include <machine/frame.h>
   49 #include <machine/intr_machdep.h>
   50 #include <machine/apicvar.h>
   51 #include <machine/md_var.h>
   52 #include <machine/smp.h>
   53 #include <machine/specialreg.h>
   54 
   55 /*
   56  * We can handle up to 60 APICs via our logical cluster IDs, but currently
   57  * the physical IDs on Intel processors up to the Pentium 4 are limited to
   58  * 16.
   59  */
   60 #define MAX_APICID      16
   61 
   62 /* Sanity checks on IDT vectors. */
   63 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS);
   64 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
   65 
   66 /*
   67  * Support for local APICs.  Local APICs manage interrupts on each
   68  * individual processor as opposed to I/O APICs which receive interrupts
   69  * from I/O devices and then forward them on to the local APICs.
   70  *
   71  * Local APICs can also send interrupts to each other thus providing the
   72  * mechanism for IPIs.
   73  */
   74 
   75 struct lvt {
   76         u_int lvt_edgetrigger:1;
   77         u_int lvt_activehi:1;
   78         u_int lvt_masked:1;
   79         u_int lvt_active:1;
   80         u_int lvt_mode:16;
   81         u_int lvt_vector:8;
   82 };
   83 
   84 struct lapic {
   85         struct lvt la_lvts[LVT_MAX + 1];
   86         u_int la_id:8;
   87         u_int la_cluster:4;
   88         u_int la_cluster_id:2;
   89         u_int la_present:1;
   90 } static lapics[MAX_APICID];
   91 
   92 /* XXX: should thermal be an NMI? */
   93 
   94 /* Global defaults for local APIC LVT entries. */
   95 static struct lvt lvts[LVT_MAX + 1] = {
   96         { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 },  /* LINT0: masked ExtINT */
   97         { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },     /* LINT1: NMI */
   98         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },   /* Timer: needs a vector */
   99         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },   /* Error: needs a vector */
  100         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },   /* PMC */
  101         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },   /* Thermal: needs a vector */
  102 };
  103 
  104 static inthand_t *ioint_handlers[] = {
  105         NULL,                   /* 0 - 31 */
  106         IDTVEC(apic_isr1),      /* 32 - 63 */
  107         IDTVEC(apic_isr2),      /* 64 - 95 */
  108         IDTVEC(apic_isr3),      /* 96 - 127 */
  109         IDTVEC(apic_isr4),      /* 128 - 159 */
  110         IDTVEC(apic_isr5),      /* 160 - 191 */
  111         IDTVEC(apic_isr6),      /* 192 - 223 */
  112         IDTVEC(apic_isr7),      /* 224 - 255 */
  113 };
  114 
  115 volatile lapic_t *lapic;
  116 
  117 static uint32_t
  118 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
  119 {
  120         struct lvt *lvt;
  121 
  122         KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
  123         if (la->la_lvts[pin].lvt_active)
  124                 lvt = &la->la_lvts[pin];
  125         else
  126                 lvt = &lvts[pin];
  127 
  128         value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
  129             APIC_LVT_VECTOR);
  130         if (lvt->lvt_edgetrigger == 0)
  131                 value |= APIC_LVT_TM;
  132         if (lvt->lvt_activehi == 0)
  133                 value |= APIC_LVT_IIPP_INTALO;
  134         if (lvt->lvt_masked)
  135                 value |= APIC_LVT_M;
  136         value |= lvt->lvt_mode;
  137         switch (lvt->lvt_mode) {
  138         case APIC_LVT_DM_NMI:
  139         case APIC_LVT_DM_SMI:
  140         case APIC_LVT_DM_INIT:
  141         case APIC_LVT_DM_EXTINT:
  142                 if (!lvt->lvt_edgetrigger) {
  143                         printf("lapic%u: Forcing LINT%u to edge trigger\n",
  144                             la->la_id, pin);
  145                         value |= APIC_LVT_TM;
  146                 }
  147                 /* Use a vector of 0. */
  148                 break;
  149         case APIC_LVT_DM_FIXED:
  150 #if 0
  151                 value |= lvt->lvt_vector;
  152 #else
  153                 panic("Fixed LINT pins not supported");
  154 #endif
  155                 break;
  156         default:
  157                 panic("bad APIC LVT delivery mode: %#x\n", value);
  158         }
  159         return (value);
  160 }
  161 
  162 /*
  163  * Map the local APIC and setup necessary interrupt vectors.
  164  */
  165 void
  166 lapic_init(uintptr_t addr)
  167 {
  168         u_int32_t value;
  169 
  170         /* Map the local APIC and setup the spurious interrupt handler. */
  171         KASSERT(trunc_page(addr) == addr,
  172             ("local APIC not aligned on a page boundary"));
  173         lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
  174         setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
  175             GSEL(GCODE_SEL, SEL_KPL));
  176 
  177         /* Perform basic initialization of the BSP's local APIC. */
  178         value = lapic->svr;
  179         value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  180         value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  181         lapic->svr = value;
  182 
  183         /* Set BSP's per-CPU local APIC ID. */
  184         PCPU_SET(apic_id, lapic_id());
  185 
  186         /* XXX: timer/error/thermal interrupts */
  187 }
  188 
  189 /*
  190  * Create a local APIC instance.
  191  */
  192 void
  193 lapic_create(u_int apic_id, int boot_cpu)
  194 {
  195         int i;
  196 
  197         if (apic_id >= MAX_APICID) {
  198                 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
  199                 if (boot_cpu)
  200                         panic("Can't ignore BSP");
  201                 return;
  202         }
  203         KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
  204             apic_id));
  205 
  206         /*
  207          * Assume no local LVT overrides and a cluster of 0 and
  208          * intra-cluster ID of 0.
  209          */
  210         lapics[apic_id].la_present = 1;
  211         lapics[apic_id].la_id = apic_id;
  212         for (i = 0; i < LVT_MAX; i++) {
  213                 lapics[apic_id].la_lvts[i] = lvts[i];
  214                 lapics[apic_id].la_lvts[i].lvt_active = 0;
  215         }
  216 
  217 #ifdef SMP
  218         cpu_add(apic_id, boot_cpu);
  219 #endif
  220 }
  221 
  222 /*
  223  * Dump contents of local APIC registers
  224  */
  225 void
  226 lapic_dump(const char* str)
  227 {
  228 
  229         printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
  230         printf("     ID: 0x%08x   VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
  231             lapic->id, lapic->version, lapic->ldr, lapic->dfr);
  232         printf("  lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
  233             lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
  234 }
  235 
  236 void
  237 lapic_enable_intr(u_int irq)
  238 {
  239         u_int vector;
  240 
  241         vector = apic_irq_to_idt(irq);
  242         KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
  243         KASSERT(ioint_handlers[vector / 32] != NULL,
  244             ("No ISR handler for IRQ %u", irq));
  245         setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
  246             GSEL(GCODE_SEL, SEL_KPL));
  247 }
  248 
  249 void
  250 lapic_setup(void)
  251 {
  252         struct lapic *la;
  253         u_int32_t value, maxlvt;
  254         register_t eflags;
  255 
  256         la = &lapics[lapic_id()];
  257         KASSERT(la->la_present, ("missing APIC structure"));
  258         eflags = intr_disable();
  259         maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
  260 
  261         /* Program LINT[01] LVT entries. */
  262         lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
  263         lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
  264 
  265         /* XXX: more LVT entries */
  266 
  267         /* Clear the TPR. */
  268         value = lapic->tpr;
  269         value &= ~APIC_TPR_PRIO;
  270         lapic->tpr = value;
  271 
  272         /* Use the cluster model for logical IDs. */
  273         value = lapic->dfr;
  274         value &= ~APIC_DFR_MODEL_MASK;
  275         value |= APIC_DFR_MODEL_CLUSTER;
  276         lapic->dfr = value;
  277 
  278         /* Set this APIC's logical ID. */
  279         value = lapic->ldr;
  280         value &= ~APIC_ID_MASK;
  281         value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT |
  282             1 << la->la_cluster_id) << APIC_ID_SHIFT;
  283         lapic->ldr = value;
  284 
  285         /* Setup spurious vector and enable the local APIC. */
  286         value = lapic->svr;
  287         value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  288         value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  289         lapic->svr = value;
  290         intr_restore(eflags);
  291 }
  292 
  293 void
  294 lapic_disable(void)
  295 {
  296         uint32_t value;
  297 
  298         /* Software disable the local APIC. */
  299         value = lapic->svr;
  300         value &= ~APIC_SVR_SWEN;
  301         lapic->svr = value;
  302 }
  303 
  304 int
  305 lapic_id(void)
  306 {
  307 
  308         KASSERT(lapic != NULL, ("local APIC is not mapped"));
  309         return (lapic->id >> APIC_ID_SHIFT);
  310 }
  311 
  312 int
  313 lapic_intr_pending(u_int vector)
  314 {
  315         volatile u_int32_t *irr;
  316 
  317         /*
  318          * The IRR registers are an array of 128-bit registers each of
  319          * which only describes 32 interrupts in the low 32 bits..  Thus,
  320          * we divide the vector by 32 to get the 128-bit index.  We then
  321          * multiply that index by 4 to get the equivalent index from
  322          * treating the IRR as an array of 32-bit registers.  Finally, we
  323          * modulus the vector by 32 to determine the individual bit to
  324          * test.
  325          */
  326         irr = &lapic->irr0;
  327         return (irr[(vector / 32) * 4] & 1 << (vector % 32));
  328 }
  329 
  330 void
  331 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
  332 {
  333         struct lapic *la;
  334 
  335         KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
  336             __func__, apic_id));
  337         KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
  338             __func__, cluster));
  339         KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
  340             ("%s: intra cluster id %u too big", __func__, cluster_id));
  341         la = &lapics[apic_id];
  342         la->la_cluster = cluster;
  343         la->la_cluster_id = cluster_id;
  344 }
  345 
  346 int
  347 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
  348 {
  349 
  350         if (pin > LVT_MAX)
  351                 return (EINVAL);
  352         if (apic_id == APIC_ID_ALL) {
  353                 lvts[pin].lvt_masked = masked;
  354                 if (bootverbose)
  355                         printf("lapic:");
  356         } else {
  357                 KASSERT(lapics[apic_id].la_present,
  358                     ("%s: missing APIC %u", __func__, apic_id));
  359                 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
  360                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  361                 if (bootverbose)
  362                         printf("lapic%u:", apic_id);
  363         }
  364         if (bootverbose)
  365                 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
  366         return (0);
  367 }
  368 
  369 int
  370 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
  371 {
  372         struct lvt *lvt;
  373 
  374         if (pin > LVT_MAX)
  375                 return (EINVAL);
  376         if (apic_id == APIC_ID_ALL) {
  377                 lvt = &lvts[pin];
  378                 if (bootverbose)
  379                         printf("lapic:");
  380         } else {
  381                 KASSERT(lapics[apic_id].la_present,
  382                     ("%s: missing APIC %u", __func__, apic_id));
  383                 lvt = &lapics[apic_id].la_lvts[pin];
  384                 lvt->lvt_active = 1;
  385                 if (bootverbose)
  386                         printf("lapic%u:", apic_id);
  387         }
  388         lvt->lvt_mode = mode;
  389         switch (mode) {
  390         case APIC_LVT_DM_NMI:
  391         case APIC_LVT_DM_SMI:
  392         case APIC_LVT_DM_INIT:
  393         case APIC_LVT_DM_EXTINT:
  394                 lvt->lvt_edgetrigger = 1;
  395                 lvt->lvt_activehi = 1;
  396                 if (mode == APIC_LVT_DM_EXTINT)
  397                         lvt->lvt_masked = 1;
  398                 else
  399                         lvt->lvt_masked = 0;
  400                 break;
  401         default:
  402                 panic("Unsupported delivery mode: 0x%x\n", mode);
  403         }
  404         if (bootverbose) {
  405                 printf(" Routing ");
  406                 switch (mode) {
  407                 case APIC_LVT_DM_NMI:
  408                         printf("NMI");
  409                         break;
  410                 case APIC_LVT_DM_SMI:
  411                         printf("SMI");
  412                         break;
  413                 case APIC_LVT_DM_INIT:
  414                         printf("INIT");
  415                         break;
  416                 case APIC_LVT_DM_EXTINT:
  417                         printf("ExtINT");
  418                         break;
  419                 }
  420                 printf(" -> LINT%u\n", pin);
  421         }
  422         return (0);
  423 }
  424 
  425 int
  426 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
  427 {
  428 
  429         if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
  430                 return (EINVAL);
  431         if (apic_id == APIC_ID_ALL) {
  432                 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
  433                 if (bootverbose)
  434                         printf("lapic:");
  435         } else {
  436                 KASSERT(lapics[apic_id].la_present,
  437                     ("%s: missing APIC %u", __func__, apic_id));
  438                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  439                 lapics[apic_id].la_lvts[pin].lvt_activehi =
  440                     (pol == INTR_POLARITY_HIGH);
  441                 if (bootverbose)
  442                         printf("lapic%u:", apic_id);
  443         }
  444         if (bootverbose)
  445                 printf(" LINT%u polarity: active-%s\n", pin,
  446                     pol == INTR_POLARITY_HIGH ? "high" : "low");
  447         return (0);
  448 }
  449 
  450 int
  451 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
  452 {
  453 
  454         if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
  455                 return (EINVAL);
  456         if (apic_id == APIC_ID_ALL) {
  457                 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  458                 if (bootverbose)
  459                         printf("lapic:");
  460         } else {
  461                 KASSERT(lapics[apic_id].la_present,
  462                     ("%s: missing APIC %u", __func__, apic_id));
  463                 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
  464                     (trigger == INTR_TRIGGER_EDGE);
  465                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  466                 if (bootverbose)
  467                         printf("lapic%u:", apic_id);
  468         }
  469         if (bootverbose)
  470                 printf(" LINT%u trigger: %s\n", pin,
  471                     trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  472         return (0);
  473 }
  474 
  475 void
  476 lapic_eoi(void)
  477 {
  478 
  479         lapic->eoi = 0;
  480 }
  481 
  482 void
  483 lapic_handle_intr(struct intrframe frame)
  484 {
  485         struct intsrc *isrc;
  486 
  487         if (frame.if_vec == -1)
  488                 panic("Couldn't get vector from ISR!");
  489         isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec));
  490         intr_execute_handlers(isrc, &frame);
  491 }
  492 
  493 /* Translate between IDT vectors and IRQ vectors. */
  494 u_int
  495 apic_irq_to_idt(u_int irq)
  496 {
  497         u_int vector;
  498 
  499         KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  500         vector = irq + APIC_IO_INTS;
  501         if (vector >= IDT_SYSCALL)
  502                 vector++;
  503         return (vector);
  504 }
  505 
  506 u_int
  507 apic_idt_to_irq(u_int vector)
  508 {
  509 
  510         KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  511             vector <= APIC_IO_INTS + NUM_IO_INTS,
  512             ("Vector %u does not map to an IRQ line", vector));
  513         if (vector > IDT_SYSCALL)
  514                 vector--;
  515         return (vector - APIC_IO_INTS);
  516 }
  517 
  518 /*
  519  * APIC probing support code.  This includes code to manage enumerators.
  520  */
  521 
  522 static SLIST_HEAD(, apic_enumerator) enumerators =
  523         SLIST_HEAD_INITIALIZER(enumerators);
  524 static struct apic_enumerator *best_enum;
  525         
  526 void
  527 apic_register_enumerator(struct apic_enumerator *enumerator)
  528 {
  529 #ifdef INVARIANTS
  530         struct apic_enumerator *apic_enum;
  531 
  532         SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
  533                 if (apic_enum == enumerator)
  534                         panic("%s: Duplicate register of %s", __func__,
  535                             enumerator->apic_name);
  536         }
  537 #endif
  538         SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
  539 }
  540 
  541 /*
  542  * Probe the APIC enumerators, enumerate CPUs, and initialize the
  543  * local APIC.
  544  */
  545 static void
  546 apic_init(void *dummy __unused)
  547 {
  548         struct apic_enumerator *enumerator;
  549         uint64_t apic_base;
  550         int retval, best;
  551 
  552         /* We only support built in local APICs. */
  553         if (!(cpu_feature & CPUID_APIC))
  554                 return;
  555 
  556         /* Don't probe if APIC mode is disabled. */
  557         if (resource_disabled("apic", 0))
  558                 return;
  559 
  560         /* First, probe all the enumerators to find the best match. */
  561         best_enum = NULL;
  562         best = 0;
  563         SLIST_FOREACH(enumerator, &enumerators, apic_next) {
  564                 retval = enumerator->apic_probe();
  565                 if (retval > 0)
  566                         continue;
  567                 if (best_enum == NULL || best < retval) {
  568                         best_enum = enumerator;
  569                         best = retval;
  570                 }
  571         }
  572         if (best_enum == NULL) {
  573                 if (bootverbose)
  574                         printf("APIC: Could not find any APICs.\n");
  575                 return;
  576         }
  577 
  578         if (bootverbose)
  579                 printf("APIC: Using the %s enumerator.\n",
  580                     best_enum->apic_name);
  581 
  582         /*
  583          * To work around an errata, we disable the local APIC on some
  584          * CPUs during early startup.  We need to turn the local APIC back
  585          * on on such CPUs now.
  586          */
  587         if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
  588             (cpu_id & 0xff0) == 0x610) {
  589                 apic_base = rdmsr(MSR_APICBASE);
  590                 apic_base |= APICBASE_ENABLED;
  591                 wrmsr(MSR_APICBASE, apic_base);
  592         }
  593 
  594         /* Second, probe the CPU's in the system. */
  595         retval = best_enum->apic_probe_cpus();
  596         if (retval != 0)
  597                 printf("%s: Failed to probe CPUs: returned %d\n",
  598                     best_enum->apic_name, retval);
  599 
  600         /* Third, initialize the local APIC. */
  601         retval = best_enum->apic_setup_local();
  602         if (retval != 0)
  603                 printf("%s: Failed to setup the local APIC: returned %d\n",
  604                     best_enum->apic_name, retval);
  605 #ifdef SMP
  606         /* Last, setup the cpu topology now that we have probed CPUs */
  607         mp_topology();
  608 #endif
  609 }
  610 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
  611 
  612 /*
  613  * Setup the I/O APICs.
  614  */
  615 static void
  616 apic_setup_io(void *dummy __unused)
  617 {
  618         int retval;
  619 
  620         if (best_enum == NULL)
  621                 return;
  622         retval = best_enum->apic_setup_io();
  623         if (retval != 0)
  624                 printf("%s: Failed to setup I/O APICs: returned %d\n",
  625                     best_enum->apic_name, retval);
  626 
  627         /*
  628          * Finish setting up the local APIC on the BSP once we know how to
  629          * properly program the LINT pins.
  630          */
  631         lapic_setup();
  632         if (bootverbose)
  633                 lapic_dump("BSP");
  634 }
  635 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
  636 
  637 #ifdef SMP
  638 /*
  639  * Inter Processor Interrupt functions.  The lapic_ipi_*() functions are
  640  * private the sys/i386 code.  The public interface for the rest of the
  641  * kernel is defined in mp_machdep.c.
  642  */
  643 
  644 int
  645 lapic_ipi_wait(int delay)
  646 {
  647         int x, incr;
  648 
  649         /*
  650          * Wait delay loops for IPI to be sent.  This is highly bogus
  651          * since this is sensitive to CPU clock speed.  If delay is
  652          * -1, we wait forever.
  653          */
  654         if (delay == -1) {
  655                 incr = 0;
  656                 delay = 1;
  657         } else
  658                 incr = 1;
  659         for (x = 0; x < delay; x += incr) {
  660                 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
  661                         return (1);
  662                 ia32_pause();
  663         }
  664         return (0);
  665 }
  666 
  667 void
  668 lapic_ipi_raw(register_t icrlo, u_int dest)
  669 {
  670         register_t value, eflags;
  671 
  672         /* XXX: Need more sanity checking of icrlo? */
  673         KASSERT(lapic != NULL, ("%s called too early", __func__));
  674         KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
  675             ("%s: invalid dest field", __func__));
  676         KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
  677             ("%s: reserved bits set in ICR LO register", __func__));
  678 
  679         /* Set destination in ICR HI register if it is being used. */
  680         eflags = intr_disable();
  681         if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
  682                 value = lapic->icr_hi;
  683                 value &= ~APIC_ID_MASK;
  684                 value |= dest << APIC_ID_SHIFT;
  685                 lapic->icr_hi = value;
  686         }
  687 
  688         /* Program the contents of the IPI and dispatch it. */
  689         value = lapic->icr_lo;
  690         value &= APIC_ICRLO_RESV_MASK;
  691         value |= icrlo;
  692         lapic->icr_lo = value;
  693         intr_restore(eflags);
  694 }
  695 
  696 #define BEFORE_SPIN     1000000
  697 #ifdef DETECT_DEADLOCK
  698 #define AFTER_SPIN      1000
  699 #endif
  700 
  701 void
  702 lapic_ipi_vectored(u_int vector, int dest)
  703 {
  704         register_t icrlo, destfield;
  705 
  706         KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
  707             ("%s: invalid vector %d", __func__, vector));
  708 
  709         icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
  710             APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
  711         destfield = 0;
  712         switch (dest) {
  713         case APIC_IPI_DEST_SELF:
  714                 icrlo |= APIC_DEST_SELF;
  715                 break;
  716         case APIC_IPI_DEST_ALL:
  717                 icrlo |= APIC_DEST_ALLISELF;
  718                 break;
  719         case APIC_IPI_DEST_OTHERS:
  720                 icrlo |= APIC_DEST_ALLESELF;
  721                 break;
  722         default:
  723                 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
  724                     ("%s: invalid destination 0x%x", __func__, dest));
  725                 destfield = dest;
  726         }
  727 
  728         /* Wait for an earlier IPI to finish. */
  729         if (!lapic_ipi_wait(BEFORE_SPIN))
  730                 panic("APIC: Previous IPI is stuck");
  731 
  732         lapic_ipi_raw(icrlo, destfield);
  733 
  734 #ifdef DETECT_DEADLOCK
  735         /* Wait for IPI to be delivered. */
  736         if (!lapic_ipi_wait(AFTER_SPIN)) {
  737 #ifdef needsattention
  738                 /*
  739                  * XXX FIXME:
  740                  *
  741                  * The above function waits for the message to actually be
  742                  * delivered.  It breaks out after an arbitrary timeout
  743                  * since the message should eventually be delivered (at
  744                  * least in theory) and that if it wasn't we would catch
  745                  * the failure with the check above when the next IPI is
  746                  * sent.
  747                  *
  748                  * We could skiip this wait entirely, EXCEPT it probably
  749                  * protects us from other routines that assume that the
  750                  * message was delivered and acted upon when this function
  751                  * returns.
  752                  */
  753                 printf("APIC: IPI might be stuck\n");
  754 #else /* !needsattention */
  755                 /* Wait until mesage is sent without a timeout. */
  756                 while (lapic->icr_lo & APIC_DELSTAT_PEND)
  757                         ia32_pause();
  758 #endif /* needsattention */
  759         }
  760 #endif /* DETECT_DEADLOCK */
  761 }
  762 #endif /* SMP */

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