1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.1/sys/i386/i386/local_apic.c 158179 2006-04-30 16:44:43Z cvs2svn $");
36
37 #include "opt_hwpmc_hooks.h"
38
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/pcpu.h>
48 #include <sys/smp.h>
49
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52
53 #include <machine/apicreg.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/apicvar.h>
58 #include <machine/md_var.h>
59 #include <machine/smp.h>
60 #include <machine/specialreg.h>
61
62 #ifdef DDB
63 #include <sys/interrupt.h>
64 #include <ddb/ddb.h>
65 #endif
66
67 /*
68 * We can handle up to 60 APICs via our logical cluster IDs, but currently
69 * the physical IDs on Intel processors up to the Pentium 4 are limited to
70 * 16.
71 */
72 #define MAX_APICID 16
73
74 /* Sanity checks on IDT vectors. */
75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
77 CTASSERT(APIC_LOCAL_INTS == 240);
78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
79
80 #define LAPIC_TIMER_HZ_DIVIDER 2
81 #define LAPIC_TIMER_STATHZ_DIVIDER 15
82 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
83
84 /* Magic IRQ values for the timer and syscalls. */
85 #define IRQ_TIMER (NUM_IO_INTS + 1)
86 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
87
88 /*
89 * Support for local APICs. Local APICs manage interrupts on each
90 * individual processor as opposed to I/O APICs which receive interrupts
91 * from I/O devices and then forward them on to the local APICs.
92 *
93 * Local APICs can also send interrupts to each other thus providing the
94 * mechanism for IPIs.
95 */
96
97 struct lvt {
98 u_int lvt_edgetrigger:1;
99 u_int lvt_activehi:1;
100 u_int lvt_masked:1;
101 u_int lvt_active:1;
102 u_int lvt_mode:16;
103 u_int lvt_vector:8;
104 };
105
106 struct lapic {
107 struct lvt la_lvts[LVT_MAX + 1];
108 u_int la_id:8;
109 u_int la_cluster:4;
110 u_int la_cluster_id:2;
111 u_int la_present:1;
112 u_long *la_timer_count;
113 u_long la_hard_ticks;
114 u_long la_stat_ticks;
115 u_long la_prof_ticks;
116 } static lapics[MAX_APICID];
117
118 /* XXX: should thermal be an NMI? */
119
120 /* Global defaults for local APIC LVT entries. */
121 static struct lvt lvts[LVT_MAX + 1] = {
122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
126 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
128 };
129
130 static inthand_t *ioint_handlers[] = {
131 NULL, /* 0 - 31 */
132 IDTVEC(apic_isr1), /* 32 - 63 */
133 IDTVEC(apic_isr2), /* 64 - 95 */
134 IDTVEC(apic_isr3), /* 96 - 127 */
135 IDTVEC(apic_isr4), /* 128 - 159 */
136 IDTVEC(apic_isr5), /* 160 - 191 */
137 IDTVEC(apic_isr6), /* 192 - 223 */
138 IDTVEC(apic_isr7), /* 224 - 255 */
139 };
140
141 /* Include IDT_SYSCALL to make indexing easier. */
142 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
143
144 static u_int32_t lapic_timer_divisors[] = {
145 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
146 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
147 };
148
149 volatile lapic_t *lapic;
150 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
151
152 static void lapic_enable(void);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
158
159 static uint32_t
160 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
161 {
162 struct lvt *lvt;
163
164 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
165 if (la->la_lvts[pin].lvt_active)
166 lvt = &la->la_lvts[pin];
167 else
168 lvt = &lvts[pin];
169
170 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
171 APIC_LVT_VECTOR);
172 if (lvt->lvt_edgetrigger == 0)
173 value |= APIC_LVT_TM;
174 if (lvt->lvt_activehi == 0)
175 value |= APIC_LVT_IIPP_INTALO;
176 if (lvt->lvt_masked)
177 value |= APIC_LVT_M;
178 value |= lvt->lvt_mode;
179 switch (lvt->lvt_mode) {
180 case APIC_LVT_DM_NMI:
181 case APIC_LVT_DM_SMI:
182 case APIC_LVT_DM_INIT:
183 case APIC_LVT_DM_EXTINT:
184 if (!lvt->lvt_edgetrigger) {
185 printf("lapic%u: Forcing LINT%u to edge trigger\n",
186 la->la_id, pin);
187 value |= APIC_LVT_TM;
188 }
189 /* Use a vector of 0. */
190 break;
191 case APIC_LVT_DM_FIXED:
192 value |= lvt->lvt_vector;
193 break;
194 default:
195 panic("bad APIC LVT delivery mode: %#x\n", value);
196 }
197 return (value);
198 }
199
200 /*
201 * Map the local APIC and setup necessary interrupt vectors.
202 */
203 void
204 lapic_init(uintptr_t addr)
205 {
206
207 /* Map the local APIC and setup the spurious interrupt handler. */
208 KASSERT(trunc_page(addr) == addr,
209 ("local APIC not aligned on a page boundary"));
210 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
211 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
212 GSEL(GCODE_SEL, SEL_KPL));
213
214 /* Perform basic initialization of the BSP's local APIC. */
215 lapic_enable();
216 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
217
218 /* Set BSP's per-CPU local APIC ID. */
219 PCPU_SET(apic_id, lapic_id());
220 intr_add_cpu(PCPU_GET(apic_id));
221
222 /* Local APIC timer interrupt. */
223 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
224 GSEL(GCODE_SEL, SEL_KPL));
225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
226
227 /* XXX: error/thermal interrupts */
228 }
229
230 /*
231 * Create a local APIC instance.
232 */
233 void
234 lapic_create(u_int apic_id, int boot_cpu)
235 {
236 int i;
237
238 if (apic_id >= MAX_APICID) {
239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
240 if (boot_cpu)
241 panic("Can't ignore BSP");
242 return;
243 }
244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
245 apic_id));
246
247 /*
248 * Assume no local LVT overrides and a cluster of 0 and
249 * intra-cluster ID of 0.
250 */
251 lapics[apic_id].la_present = 1;
252 lapics[apic_id].la_id = apic_id;
253 for (i = 0; i < LVT_MAX; i++) {
254 lapics[apic_id].la_lvts[i] = lvts[i];
255 lapics[apic_id].la_lvts[i].lvt_active = 0;
256 }
257
258 #ifdef SMP
259 cpu_add(apic_id, boot_cpu);
260 #endif
261 }
262
263 /*
264 * Dump contents of local APIC registers
265 */
266 void
267 lapic_dump(const char* str)
268 {
269
270 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
271 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
272 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
273 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
274 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
275 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
276 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
277 lapic->lvt_pcint);
278 }
279
280 void
281 lapic_setup(void)
282 {
283 struct lapic *la;
284 u_int32_t maxlvt;
285 register_t eflags;
286 char buf[MAXCOMLEN + 1];
287
288 la = &lapics[lapic_id()];
289 KASSERT(la->la_present, ("missing APIC structure"));
290 eflags = intr_disable();
291 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
292
293 /* Initialize the TPR to allow all interrupts. */
294 lapic_set_tpr(0);
295
296 /* Setup spurious vector and enable the local APIC. */
297 lapic_enable();
298
299 /* Program LINT[01] LVT entries. */
300 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
301 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
302 #ifdef HWPMC_HOOKS
303 /* Program the PMC LVT entry if present. */
304 if (maxlvt >= LVT_PMC)
305 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
306 #endif
307
308 /* Program timer LVT and setup handler. */
309 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
310 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
311 intrcnt_add(buf, &la->la_timer_count);
312 if (PCPU_GET(cpuid) != 0) {
313 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
314 lapic_id()));
315 lapic_timer_set_divisor(lapic_timer_divisor);
316 lapic_timer_periodic(lapic_timer_period);
317 lapic_timer_enable_intr();
318 }
319
320 /* XXX: Error and thermal LVTs */
321
322 intr_restore(eflags);
323 }
324
325 /*
326 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
327 * that it can drive hardclock, statclock, and profclock. This function
328 * returns true if it is able to use the local APIC timer to drive the
329 * clocks and false if it is not able.
330 */
331 int
332 lapic_setup_clock(void)
333 {
334 u_long value;
335
336 /* Can't drive the timer without a local APIC. */
337 if (lapic == NULL)
338 return (0);
339
340 /* Start off with a divisor of 2 (power on reset default). */
341 lapic_timer_divisor = 2;
342
343 /* Try to calibrate the local APIC timer. */
344 do {
345 lapic_timer_set_divisor(lapic_timer_divisor);
346 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
347 DELAY(2000000);
348 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
349 if (value != APIC_TIMER_MAX_COUNT)
350 break;
351 lapic_timer_divisor <<= 1;
352 } while (lapic_timer_divisor <= 128);
353 if (lapic_timer_divisor > 128)
354 panic("lapic: Divisor too big");
355 value /= 2;
356 if (bootverbose)
357 printf("lapic: Divisor %lu, Frequency %lu hz\n",
358 lapic_timer_divisor, value);
359
360 /*
361 * We will drive the timer at a small multiple of hz and drive
362 * both of the other timers with similarly small but relatively
363 * prime divisors.
364 */
365 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
366 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
367 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
368 lapic_timer_period = value / lapic_timer_hz;
369
370 /*
371 * Start up the timer on the BSP. The APs will kick off their
372 * timer during lapic_setup().
373 */
374 lapic_timer_periodic(lapic_timer_period);
375 lapic_timer_enable_intr();
376 return (1);
377 }
378
379 void
380 lapic_disable(void)
381 {
382 uint32_t value;
383
384 /* Software disable the local APIC. */
385 value = lapic->svr;
386 value &= ~APIC_SVR_SWEN;
387 lapic->svr = value;
388 }
389
390 static void
391 lapic_enable(void)
392 {
393 u_int32_t value;
394
395 /* Program the spurious vector to enable the local APIC. */
396 value = lapic->svr;
397 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
398 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
399 lapic->svr = value;
400 }
401
402 int
403 lapic_id(void)
404 {
405
406 KASSERT(lapic != NULL, ("local APIC is not mapped"));
407 return (lapic->id >> APIC_ID_SHIFT);
408 }
409
410 int
411 lapic_intr_pending(u_int vector)
412 {
413 volatile u_int32_t *irr;
414
415 /*
416 * The IRR registers are an array of 128-bit registers each of
417 * which only describes 32 interrupts in the low 32 bits.. Thus,
418 * we divide the vector by 32 to get the 128-bit index. We then
419 * multiply that index by 4 to get the equivalent index from
420 * treating the IRR as an array of 32-bit registers. Finally, we
421 * modulus the vector by 32 to determine the individual bit to
422 * test.
423 */
424 irr = &lapic->irr0;
425 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
426 }
427
428 void
429 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
430 {
431 struct lapic *la;
432
433 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
434 __func__, apic_id));
435 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
436 __func__, cluster));
437 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
438 ("%s: intra cluster id %u too big", __func__, cluster_id));
439 la = &lapics[apic_id];
440 la->la_cluster = cluster;
441 la->la_cluster_id = cluster_id;
442 }
443
444 int
445 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
446 {
447
448 if (pin > LVT_MAX)
449 return (EINVAL);
450 if (apic_id == APIC_ID_ALL) {
451 lvts[pin].lvt_masked = masked;
452 if (bootverbose)
453 printf("lapic:");
454 } else {
455 KASSERT(lapics[apic_id].la_present,
456 ("%s: missing APIC %u", __func__, apic_id));
457 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
458 lapics[apic_id].la_lvts[pin].lvt_active = 1;
459 if (bootverbose)
460 printf("lapic%u:", apic_id);
461 }
462 if (bootverbose)
463 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
464 return (0);
465 }
466
467 int
468 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
469 {
470 struct lvt *lvt;
471
472 if (pin > LVT_MAX)
473 return (EINVAL);
474 if (apic_id == APIC_ID_ALL) {
475 lvt = &lvts[pin];
476 if (bootverbose)
477 printf("lapic:");
478 } else {
479 KASSERT(lapics[apic_id].la_present,
480 ("%s: missing APIC %u", __func__, apic_id));
481 lvt = &lapics[apic_id].la_lvts[pin];
482 lvt->lvt_active = 1;
483 if (bootverbose)
484 printf("lapic%u:", apic_id);
485 }
486 lvt->lvt_mode = mode;
487 switch (mode) {
488 case APIC_LVT_DM_NMI:
489 case APIC_LVT_DM_SMI:
490 case APIC_LVT_DM_INIT:
491 case APIC_LVT_DM_EXTINT:
492 lvt->lvt_edgetrigger = 1;
493 lvt->lvt_activehi = 1;
494 if (mode == APIC_LVT_DM_EXTINT)
495 lvt->lvt_masked = 1;
496 else
497 lvt->lvt_masked = 0;
498 break;
499 default:
500 panic("Unsupported delivery mode: 0x%x\n", mode);
501 }
502 if (bootverbose) {
503 printf(" Routing ");
504 switch (mode) {
505 case APIC_LVT_DM_NMI:
506 printf("NMI");
507 break;
508 case APIC_LVT_DM_SMI:
509 printf("SMI");
510 break;
511 case APIC_LVT_DM_INIT:
512 printf("INIT");
513 break;
514 case APIC_LVT_DM_EXTINT:
515 printf("ExtINT");
516 break;
517 }
518 printf(" -> LINT%u\n", pin);
519 }
520 return (0);
521 }
522
523 int
524 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
525 {
526
527 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
528 return (EINVAL);
529 if (apic_id == APIC_ID_ALL) {
530 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
531 if (bootverbose)
532 printf("lapic:");
533 } else {
534 KASSERT(lapics[apic_id].la_present,
535 ("%s: missing APIC %u", __func__, apic_id));
536 lapics[apic_id].la_lvts[pin].lvt_active = 1;
537 lapics[apic_id].la_lvts[pin].lvt_activehi =
538 (pol == INTR_POLARITY_HIGH);
539 if (bootverbose)
540 printf("lapic%u:", apic_id);
541 }
542 if (bootverbose)
543 printf(" LINT%u polarity: %s\n", pin,
544 pol == INTR_POLARITY_HIGH ? "high" : "low");
545 return (0);
546 }
547
548 int
549 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
550 {
551
552 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
553 return (EINVAL);
554 if (apic_id == APIC_ID_ALL) {
555 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
556 if (bootverbose)
557 printf("lapic:");
558 } else {
559 KASSERT(lapics[apic_id].la_present,
560 ("%s: missing APIC %u", __func__, apic_id));
561 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
562 (trigger == INTR_TRIGGER_EDGE);
563 lapics[apic_id].la_lvts[pin].lvt_active = 1;
564 if (bootverbose)
565 printf("lapic%u:", apic_id);
566 }
567 if (bootverbose)
568 printf(" LINT%u trigger: %s\n", pin,
569 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
570 return (0);
571 }
572
573 /*
574 * Adjust the TPR of the current CPU so that it blocks all interrupts below
575 * the passed in vector.
576 */
577 void
578 lapic_set_tpr(u_int vector)
579 {
580 #ifdef CHEAP_TPR
581 lapic->tpr = vector;
582 #else
583 u_int32_t tpr;
584
585 tpr = lapic->tpr & ~APIC_TPR_PRIO;
586 tpr |= vector;
587 lapic->tpr = tpr;
588 #endif
589 }
590
591 void
592 lapic_eoi(void)
593 {
594
595 lapic->eoi = 0;
596 }
597
598 void
599 lapic_handle_intr(struct intrframe frame)
600 {
601 struct intsrc *isrc;
602
603 if (frame.if_vec == -1)
604 panic("Couldn't get vector from ISR!");
605 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec));
606 intr_execute_handlers(isrc, &frame);
607 }
608
609 void
610 lapic_handle_timer(struct clockframe frame)
611 {
612 struct lapic *la;
613
614 la = &lapics[PCPU_GET(apic_id)];
615 (*la->la_timer_count)++;
616 critical_enter();
617
618 /* Fire hardclock at hz. */
619 la->la_hard_ticks += hz;
620 if (la->la_hard_ticks >= lapic_timer_hz) {
621 la->la_hard_ticks -= lapic_timer_hz;
622 if (PCPU_GET(cpuid) == 0)
623 hardclock(&frame);
624 else
625 hardclock_process(&frame);
626 }
627
628 /* Fire statclock at stathz. */
629 la->la_stat_ticks += stathz;
630 if (la->la_stat_ticks >= lapic_timer_hz) {
631 la->la_stat_ticks -= lapic_timer_hz;
632 statclock(&frame);
633 }
634
635 /* Fire profclock at profhz, but only when needed. */
636 la->la_prof_ticks += profhz;
637 if (la->la_prof_ticks >= lapic_timer_hz) {
638 la->la_prof_ticks -= lapic_timer_hz;
639 if (profprocs != 0)
640 profclock(&frame);
641 }
642 critical_exit();
643 }
644
645 static void
646 lapic_timer_set_divisor(u_int divisor)
647 {
648
649 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
650 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
651 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
652 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
653 }
654
655 static void
656 lapic_timer_oneshot(u_int count)
657 {
658 u_int32_t value;
659
660 value = lapic->lvt_timer;
661 value &= ~APIC_LVTT_TM;
662 value |= APIC_LVTT_TM_ONE_SHOT;
663 lapic->lvt_timer = value;
664 lapic->icr_timer = count;
665 }
666
667 static void
668 lapic_timer_periodic(u_int count)
669 {
670 u_int32_t value;
671
672 value = lapic->lvt_timer;
673 value &= ~APIC_LVTT_TM;
674 value |= APIC_LVTT_TM_PERIODIC;
675 lapic->lvt_timer = value;
676 lapic->icr_timer = count;
677 }
678
679 static void
680 lapic_timer_enable_intr(void)
681 {
682 u_int32_t value;
683
684 value = lapic->lvt_timer;
685 value &= ~APIC_LVT_M;
686 lapic->lvt_timer = value;
687 }
688
689 /* Request a free IDT vector to be used by the specified IRQ. */
690 u_int
691 apic_alloc_vector(u_int irq)
692 {
693 u_int vector;
694
695 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
696
697 /*
698 * Search for a free vector. Currently we just use a very simple
699 * algorithm to find the first free vector.
700 */
701 mtx_lock_spin(&icu_lock);
702 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
703 if (ioint_irqs[vector] != 0)
704 continue;
705 ioint_irqs[vector] = irq;
706 mtx_unlock_spin(&icu_lock);
707 return (vector + APIC_IO_INTS);
708 }
709 mtx_unlock_spin(&icu_lock);
710 panic("Couldn't find an APIC vector for IRQ %u", irq);
711 }
712
713 void
714 apic_enable_vector(u_int vector)
715 {
716
717 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
718 KASSERT(ioint_handlers[vector / 32] != NULL,
719 ("No ISR handler for vector %u", vector));
720 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
721 GSEL(GCODE_SEL, SEL_KPL));
722 }
723
724 /* Release an APIC vector when it's no longer in use. */
725 void
726 apic_free_vector(u_int vector, u_int irq)
727 {
728 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
729 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
730 ("Vector %u does not map to an IRQ line", vector));
731 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
732 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
733 mtx_lock_spin(&icu_lock);
734 ioint_irqs[vector - APIC_IO_INTS] = 0;
735 mtx_unlock_spin(&icu_lock);
736 }
737
738 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
739 u_int
740 apic_idt_to_irq(u_int vector)
741 {
742
743 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
744 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
745 ("Vector %u does not map to an IRQ line", vector));
746 return (ioint_irqs[vector - APIC_IO_INTS]);
747 }
748
749 #ifdef DDB
750 /*
751 * Dump data about APIC IDT vector mappings.
752 */
753 DB_SHOW_COMMAND(apic, db_show_apic)
754 {
755 struct intsrc *isrc;
756 int quit, i, verbose;
757 u_int irq;
758
759 quit = 0;
760 if (strcmp(modif, "vv") == 0)
761 verbose = 2;
762 else if (strcmp(modif, "v") == 0)
763 verbose = 1;
764 else
765 verbose = 0;
766 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
767 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
768 irq = ioint_irqs[i];
769 if (irq != 0 && irq != IRQ_SYSCALL) {
770 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
771 if (irq == IRQ_TIMER)
772 db_printf("lapic timer\n");
773 else if (irq < NUM_IO_INTS) {
774 isrc = intr_lookup_source(irq);
775 if (isrc == NULL || verbose == 0)
776 db_printf("IRQ %u\n", irq);
777 else
778 db_dump_intr_event(isrc->is_event,
779 verbose == 2);
780 } else
781 db_printf("IRQ %u ???\n", irq);
782 }
783 }
784 }
785 #endif
786
787 /*
788 * APIC probing support code. This includes code to manage enumerators.
789 */
790
791 static SLIST_HEAD(, apic_enumerator) enumerators =
792 SLIST_HEAD_INITIALIZER(enumerators);
793 static struct apic_enumerator *best_enum;
794
795 void
796 apic_register_enumerator(struct apic_enumerator *enumerator)
797 {
798 #ifdef INVARIANTS
799 struct apic_enumerator *apic_enum;
800
801 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
802 if (apic_enum == enumerator)
803 panic("%s: Duplicate register of %s", __func__,
804 enumerator->apic_name);
805 }
806 #endif
807 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
808 }
809
810 /*
811 * Probe the APIC enumerators, enumerate CPUs, and initialize the
812 * local APIC.
813 */
814 static void
815 apic_init(void *dummy __unused)
816 {
817 struct apic_enumerator *enumerator;
818 uint64_t apic_base;
819 int retval, best;
820
821 /* We only support built in local APICs. */
822 if (!(cpu_feature & CPUID_APIC))
823 return;
824
825 /* Don't probe if APIC mode is disabled. */
826 if (resource_disabled("apic", 0))
827 return;
828
829 /* First, probe all the enumerators to find the best match. */
830 best_enum = NULL;
831 best = 0;
832 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
833 retval = enumerator->apic_probe();
834 if (retval > 0)
835 continue;
836 if (best_enum == NULL || best < retval) {
837 best_enum = enumerator;
838 best = retval;
839 }
840 }
841 if (best_enum == NULL) {
842 if (bootverbose)
843 printf("APIC: Could not find any APICs.\n");
844 return;
845 }
846
847 if (bootverbose)
848 printf("APIC: Using the %s enumerator.\n",
849 best_enum->apic_name);
850
851 /*
852 * To work around an errata, we disable the local APIC on some
853 * CPUs during early startup. We need to turn the local APIC back
854 * on on such CPUs now.
855 */
856 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
857 (cpu_id & 0xff0) == 0x610) {
858 apic_base = rdmsr(MSR_APICBASE);
859 apic_base |= APICBASE_ENABLED;
860 wrmsr(MSR_APICBASE, apic_base);
861 }
862
863 /* Second, probe the CPU's in the system. */
864 retval = best_enum->apic_probe_cpus();
865 if (retval != 0)
866 printf("%s: Failed to probe CPUs: returned %d\n",
867 best_enum->apic_name, retval);
868
869 /* Third, initialize the local APIC. */
870 retval = best_enum->apic_setup_local();
871 if (retval != 0)
872 printf("%s: Failed to setup the local APIC: returned %d\n",
873 best_enum->apic_name, retval);
874 #ifdef SMP
875 /* Last, setup the cpu topology now that we have probed CPUs */
876 mp_topology();
877 #endif
878 }
879 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
880
881 /*
882 * Setup the I/O APICs.
883 */
884 static void
885 apic_setup_io(void *dummy __unused)
886 {
887 int retval;
888
889 if (best_enum == NULL)
890 return;
891 retval = best_enum->apic_setup_io();
892 if (retval != 0)
893 printf("%s: Failed to setup I/O APICs: returned %d\n",
894 best_enum->apic_name, retval);
895
896 /*
897 * Finish setting up the local APIC on the BSP once we know how to
898 * properly program the LINT pins.
899 */
900 lapic_setup();
901 if (bootverbose)
902 lapic_dump("BSP");
903 }
904 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
905
906 #ifdef SMP
907 /*
908 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
909 * private to the sys/i386 code. The public interface for the rest of the
910 * kernel is defined in mp_machdep.c.
911 */
912 int
913 lapic_ipi_wait(int delay)
914 {
915 int x, incr;
916
917 /*
918 * Wait delay loops for IPI to be sent. This is highly bogus
919 * since this is sensitive to CPU clock speed. If delay is
920 * -1, we wait forever.
921 */
922 if (delay == -1) {
923 incr = 0;
924 delay = 1;
925 } else
926 incr = 1;
927 for (x = 0; x < delay; x += incr) {
928 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
929 return (1);
930 ia32_pause();
931 }
932 return (0);
933 }
934
935 void
936 lapic_ipi_raw(register_t icrlo, u_int dest)
937 {
938 register_t value, eflags;
939
940 /* XXX: Need more sanity checking of icrlo? */
941 KASSERT(lapic != NULL, ("%s called too early", __func__));
942 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
943 ("%s: invalid dest field", __func__));
944 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
945 ("%s: reserved bits set in ICR LO register", __func__));
946
947 /* Set destination in ICR HI register if it is being used. */
948 eflags = intr_disable();
949 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
950 value = lapic->icr_hi;
951 value &= ~APIC_ID_MASK;
952 value |= dest << APIC_ID_SHIFT;
953 lapic->icr_hi = value;
954 }
955
956 /* Program the contents of the IPI and dispatch it. */
957 value = lapic->icr_lo;
958 value &= APIC_ICRLO_RESV_MASK;
959 value |= icrlo;
960 lapic->icr_lo = value;
961 intr_restore(eflags);
962 }
963
964 #define BEFORE_SPIN 1000000
965 #ifdef DETECT_DEADLOCK
966 #define AFTER_SPIN 1000
967 #endif
968
969 void
970 lapic_ipi_vectored(u_int vector, int dest)
971 {
972 register_t icrlo, destfield;
973
974 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
975 ("%s: invalid vector %d", __func__, vector));
976
977 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
978 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
979 destfield = 0;
980 switch (dest) {
981 case APIC_IPI_DEST_SELF:
982 icrlo |= APIC_DEST_SELF;
983 break;
984 case APIC_IPI_DEST_ALL:
985 icrlo |= APIC_DEST_ALLISELF;
986 break;
987 case APIC_IPI_DEST_OTHERS:
988 icrlo |= APIC_DEST_ALLESELF;
989 break;
990 default:
991 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
992 ("%s: invalid destination 0x%x", __func__, dest));
993 destfield = dest;
994 }
995
996 /* Wait for an earlier IPI to finish. */
997 if (!lapic_ipi_wait(BEFORE_SPIN)) {
998 if (panicstr != NULL)
999 return;
1000 else
1001 panic("APIC: Previous IPI is stuck");
1002 }
1003
1004 lapic_ipi_raw(icrlo, destfield);
1005
1006 #ifdef DETECT_DEADLOCK
1007 /* Wait for IPI to be delivered. */
1008 if (!lapic_ipi_wait(AFTER_SPIN)) {
1009 #ifdef needsattention
1010 /*
1011 * XXX FIXME:
1012 *
1013 * The above function waits for the message to actually be
1014 * delivered. It breaks out after an arbitrary timeout
1015 * since the message should eventually be delivered (at
1016 * least in theory) and that if it wasn't we would catch
1017 * the failure with the check above when the next IPI is
1018 * sent.
1019 *
1020 * We could skip this wait entirely, EXCEPT it probably
1021 * protects us from other routines that assume that the
1022 * message was delivered and acted upon when this function
1023 * returns.
1024 */
1025 printf("APIC: IPI might be stuck\n");
1026 #else /* !needsattention */
1027 /* Wait until mesage is sent without a timeout. */
1028 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1029 ia32_pause();
1030 #endif /* needsattention */
1031 }
1032 #endif /* DETECT_DEADLOCK */
1033 }
1034 #endif /* SMP */
Cache object: f62c4fab403db98e9a73ad939666f251
|