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sys/i386/i386/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/6.2/sys/i386/i386/local_apic.c 163803 2006-10-30 18:03:04Z jhb $"); 36 37 #include "opt_hwpmc_hooks.h" 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/pcpu.h> 48 #include <sys/smp.h> 49 50 #include <vm/vm.h> 51 #include <vm/pmap.h> 52 53 #include <machine/apicreg.h> 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/apicvar.h> 58 #include <machine/md_var.h> 59 #include <machine/smp.h> 60 #include <machine/specialreg.h> 61 62 #ifdef DDB 63 #include <sys/interrupt.h> 64 #include <ddb/ddb.h> 65 #endif 66 67 /* 68 * We can handle up to 60 APICs via our logical cluster IDs, but currently 69 * the physical IDs on Intel processors up to the Pentium 4 are limited to 70 * 16. 71 */ 72 #define MAX_APICID 16 73 74 /* Sanity checks on IDT vectors. */ 75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 77 CTASSERT(APIC_LOCAL_INTS == 240); 78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 79 80 #define LAPIC_TIMER_HZ_DIVIDER 2 81 #define LAPIC_TIMER_STATHZ_DIVIDER 15 82 #define LAPIC_TIMER_PROFHZ_DIVIDER 3 83 84 /* Magic IRQ values for the timer and syscalls. */ 85 #define IRQ_TIMER (NUM_IO_INTS + 1) 86 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 87 88 /* 89 * Support for local APICs. Local APICs manage interrupts on each 90 * individual processor as opposed to I/O APICs which receive interrupts 91 * from I/O devices and then forward them on to the local APICs. 92 * 93 * Local APICs can also send interrupts to each other thus providing the 94 * mechanism for IPIs. 95 */ 96 97 struct lvt { 98 u_int lvt_edgetrigger:1; 99 u_int lvt_activehi:1; 100 u_int lvt_masked:1; 101 u_int lvt_active:1; 102 u_int lvt_mode:16; 103 u_int lvt_vector:8; 104 }; 105 106 struct lapic { 107 struct lvt la_lvts[LVT_MAX + 1]; 108 u_int la_id:8; 109 u_int la_cluster:4; 110 u_int la_cluster_id:2; 111 u_int la_present:1; 112 u_long *la_timer_count; 113 u_long la_hard_ticks; 114 u_long la_stat_ticks; 115 u_long la_prof_ticks; 116 } static lapics[MAX_APICID]; 117 118 /* XXX: should thermal be an NMI? */ 119 120 /* Global defaults for local APIC LVT entries. */ 121 static struct lvt lvts[LVT_MAX + 1] = { 122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 126 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 128 }; 129 130 static inthand_t *ioint_handlers[] = { 131 NULL, /* 0 - 31 */ 132 IDTVEC(apic_isr1), /* 32 - 63 */ 133 IDTVEC(apic_isr2), /* 64 - 95 */ 134 IDTVEC(apic_isr3), /* 96 - 127 */ 135 IDTVEC(apic_isr4), /* 128 - 159 */ 136 IDTVEC(apic_isr5), /* 160 - 191 */ 137 IDTVEC(apic_isr6), /* 192 - 223 */ 138 IDTVEC(apic_isr7), /* 224 - 255 */ 139 }; 140 141 /* Include IDT_SYSCALL to make indexing easier. */ 142 static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 143 144 static u_int32_t lapic_timer_divisors[] = { 145 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 146 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 147 }; 148 149 volatile lapic_t *lapic; 150 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 151 152 static void lapic_enable(void); 153 static void lapic_resume(struct pic *pic); 154 static void lapic_timer_enable_intr(void); 155 static void lapic_timer_oneshot(u_int count); 156 static void lapic_timer_periodic(u_int count); 157 static void lapic_timer_set_divisor(u_int divisor); 158 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 159 160 struct pic lapic_pic = { .pic_resume = lapic_resume }; 161 162 static uint32_t 163 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 164 { 165 struct lvt *lvt; 166 167 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 168 if (la->la_lvts[pin].lvt_active) 169 lvt = &la->la_lvts[pin]; 170 else 171 lvt = &lvts[pin]; 172 173 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 174 APIC_LVT_VECTOR); 175 if (lvt->lvt_edgetrigger == 0) 176 value |= APIC_LVT_TM; 177 if (lvt->lvt_activehi == 0) 178 value |= APIC_LVT_IIPP_INTALO; 179 if (lvt->lvt_masked) 180 value |= APIC_LVT_M; 181 value |= lvt->lvt_mode; 182 switch (lvt->lvt_mode) { 183 case APIC_LVT_DM_NMI: 184 case APIC_LVT_DM_SMI: 185 case APIC_LVT_DM_INIT: 186 case APIC_LVT_DM_EXTINT: 187 if (!lvt->lvt_edgetrigger) { 188 printf("lapic%u: Forcing LINT%u to edge trigger\n", 189 la->la_id, pin); 190 value |= APIC_LVT_TM; 191 } 192 /* Use a vector of 0. */ 193 break; 194 case APIC_LVT_DM_FIXED: 195 value |= lvt->lvt_vector; 196 break; 197 default: 198 panic("bad APIC LVT delivery mode: %#x\n", value); 199 } 200 return (value); 201 } 202 203 /* 204 * Map the local APIC and setup necessary interrupt vectors. 205 */ 206 void 207 lapic_init(uintptr_t addr) 208 { 209 210 /* Map the local APIC and setup the spurious interrupt handler. */ 211 KASSERT(trunc_page(addr) == addr, 212 ("local APIC not aligned on a page boundary")); 213 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 215 GSEL(GCODE_SEL, SEL_KPL)); 216 217 /* Perform basic initialization of the BSP's local APIC. */ 218 lapic_enable(); 219 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 220 221 /* Set BSP's per-CPU local APIC ID. */ 222 PCPU_SET(apic_id, lapic_id()); 223 intr_add_cpu(PCPU_GET(apic_id)); 224 225 /* Local APIC timer interrupt. */ 226 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 227 GSEL(GCODE_SEL, SEL_KPL)); 228 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 229 230 /* XXX: error/thermal interrupts */ 231 } 232 233 /* 234 * Create a local APIC instance. 235 */ 236 void 237 lapic_create(u_int apic_id, int boot_cpu) 238 { 239 int i; 240 241 if (apic_id >= MAX_APICID) { 242 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 243 if (boot_cpu) 244 panic("Can't ignore BSP"); 245 return; 246 } 247 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 248 apic_id)); 249 250 /* 251 * Assume no local LVT overrides and a cluster of 0 and 252 * intra-cluster ID of 0. 253 */ 254 lapics[apic_id].la_present = 1; 255 lapics[apic_id].la_id = apic_id; 256 for (i = 0; i < LVT_MAX; i++) { 257 lapics[apic_id].la_lvts[i] = lvts[i]; 258 lapics[apic_id].la_lvts[i].lvt_active = 0; 259 } 260 261 #ifdef SMP 262 cpu_add(apic_id, boot_cpu); 263 #endif 264 } 265 266 /* 267 * Dump contents of local APIC registers 268 */ 269 void 270 lapic_dump(const char* str) 271 { 272 273 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 274 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 275 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 276 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 277 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 278 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 279 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 280 lapic->lvt_pcint); 281 } 282 283 void 284 lapic_setup(int boot) 285 { 286 struct lapic *la; 287 u_int32_t maxlvt; 288 register_t eflags; 289 char buf[MAXCOMLEN + 1]; 290 291 la = &lapics[lapic_id()]; 292 KASSERT(la->la_present, ("missing APIC structure")); 293 eflags = intr_disable(); 294 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 295 296 /* Initialize the TPR to allow all interrupts. */ 297 lapic_set_tpr(0); 298 299 /* Setup spurious vector and enable the local APIC. */ 300 lapic_enable(); 301 302 /* Program LINT[01] LVT entries. */ 303 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 304 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 305 #ifdef HWPMC_HOOKS 306 /* Program the PMC LVT entry if present. */ 307 if (maxlvt >= LVT_PMC) 308 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 309 #endif 310 311 /* Program timer LVT and setup handler. */ 312 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 313 if (boot) { 314 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 315 intrcnt_add(buf, &la->la_timer_count); 316 } 317 318 /* We don't setup the timer during boot on the BSP until later. */ 319 if (!(boot && PCPU_GET(cpuid) == 0)) { 320 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 321 lapic_id())); 322 lapic_timer_set_divisor(lapic_timer_divisor); 323 lapic_timer_periodic(lapic_timer_period); 324 lapic_timer_enable_intr(); 325 } 326 327 /* XXX: Error and thermal LVTs */ 328 329 intr_restore(eflags); 330 } 331 332 /* 333 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 334 * that it can drive hardclock, statclock, and profclock. This function 335 * returns true if it is able to use the local APIC timer to drive the 336 * clocks and false if it is not able. 337 */ 338 int 339 lapic_setup_clock(void) 340 { 341 u_long value; 342 343 /* Can't drive the timer without a local APIC. */ 344 if (lapic == NULL) 345 return (0); 346 347 /* Start off with a divisor of 2 (power on reset default). */ 348 lapic_timer_divisor = 2; 349 350 /* Try to calibrate the local APIC timer. */ 351 do { 352 lapic_timer_set_divisor(lapic_timer_divisor); 353 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 354 DELAY(2000000); 355 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 356 if (value != APIC_TIMER_MAX_COUNT) 357 break; 358 lapic_timer_divisor <<= 1; 359 } while (lapic_timer_divisor <= 128); 360 if (lapic_timer_divisor > 128) 361 panic("lapic: Divisor too big"); 362 value /= 2; 363 if (bootverbose) 364 printf("lapic: Divisor %lu, Frequency %lu hz\n", 365 lapic_timer_divisor, value); 366 367 /* 368 * We will drive the timer at a small multiple of hz and drive 369 * both of the other timers with similarly small but relatively 370 * prime divisors. 371 */ 372 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 373 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 374 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 375 lapic_timer_period = value / lapic_timer_hz; 376 377 /* 378 * Start up the timer on the BSP. The APs will kick off their 379 * timer during lapic_setup(). 380 */ 381 lapic_timer_periodic(lapic_timer_period); 382 lapic_timer_enable_intr(); 383 return (1); 384 } 385 386 void 387 lapic_disable(void) 388 { 389 uint32_t value; 390 391 /* Software disable the local APIC. */ 392 value = lapic->svr; 393 value &= ~APIC_SVR_SWEN; 394 lapic->svr = value; 395 } 396 397 static void 398 lapic_enable(void) 399 { 400 u_int32_t value; 401 402 /* Program the spurious vector to enable the local APIC. */ 403 value = lapic->svr; 404 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 405 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 406 lapic->svr = value; 407 } 408 409 /* Reset the local APIC on the BSP during resume. */ 410 static void 411 lapic_resume(struct pic *pic) 412 { 413 414 lapic_setup(0); 415 } 416 417 int 418 lapic_id(void) 419 { 420 421 KASSERT(lapic != NULL, ("local APIC is not mapped")); 422 return (lapic->id >> APIC_ID_SHIFT); 423 } 424 425 int 426 lapic_intr_pending(u_int vector) 427 { 428 volatile u_int32_t *irr; 429 430 /* 431 * The IRR registers are an array of 128-bit registers each of 432 * which only describes 32 interrupts in the low 32 bits.. Thus, 433 * we divide the vector by 32 to get the 128-bit index. We then 434 * multiply that index by 4 to get the equivalent index from 435 * treating the IRR as an array of 32-bit registers. Finally, we 436 * modulus the vector by 32 to determine the individual bit to 437 * test. 438 */ 439 irr = &lapic->irr0; 440 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 441 } 442 443 void 444 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 445 { 446 struct lapic *la; 447 448 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 449 __func__, apic_id)); 450 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 451 __func__, cluster)); 452 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 453 ("%s: intra cluster id %u too big", __func__, cluster_id)); 454 la = &lapics[apic_id]; 455 la->la_cluster = cluster; 456 la->la_cluster_id = cluster_id; 457 } 458 459 int 460 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 461 { 462 463 if (pin > LVT_MAX) 464 return (EINVAL); 465 if (apic_id == APIC_ID_ALL) { 466 lvts[pin].lvt_masked = masked; 467 if (bootverbose) 468 printf("lapic:"); 469 } else { 470 KASSERT(lapics[apic_id].la_present, 471 ("%s: missing APIC %u", __func__, apic_id)); 472 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 473 lapics[apic_id].la_lvts[pin].lvt_active = 1; 474 if (bootverbose) 475 printf("lapic%u:", apic_id); 476 } 477 if (bootverbose) 478 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 479 return (0); 480 } 481 482 int 483 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 484 { 485 struct lvt *lvt; 486 487 if (pin > LVT_MAX) 488 return (EINVAL); 489 if (apic_id == APIC_ID_ALL) { 490 lvt = &lvts[pin]; 491 if (bootverbose) 492 printf("lapic:"); 493 } else { 494 KASSERT(lapics[apic_id].la_present, 495 ("%s: missing APIC %u", __func__, apic_id)); 496 lvt = &lapics[apic_id].la_lvts[pin]; 497 lvt->lvt_active = 1; 498 if (bootverbose) 499 printf("lapic%u:", apic_id); 500 } 501 lvt->lvt_mode = mode; 502 switch (mode) { 503 case APIC_LVT_DM_NMI: 504 case APIC_LVT_DM_SMI: 505 case APIC_LVT_DM_INIT: 506 case APIC_LVT_DM_EXTINT: 507 lvt->lvt_edgetrigger = 1; 508 lvt->lvt_activehi = 1; 509 if (mode == APIC_LVT_DM_EXTINT) 510 lvt->lvt_masked = 1; 511 else 512 lvt->lvt_masked = 0; 513 break; 514 default: 515 panic("Unsupported delivery mode: 0x%x\n", mode); 516 } 517 if (bootverbose) { 518 printf(" Routing "); 519 switch (mode) { 520 case APIC_LVT_DM_NMI: 521 printf("NMI"); 522 break; 523 case APIC_LVT_DM_SMI: 524 printf("SMI"); 525 break; 526 case APIC_LVT_DM_INIT: 527 printf("INIT"); 528 break; 529 case APIC_LVT_DM_EXTINT: 530 printf("ExtINT"); 531 break; 532 } 533 printf(" -> LINT%u\n", pin); 534 } 535 return (0); 536 } 537 538 int 539 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 540 { 541 542 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 543 return (EINVAL); 544 if (apic_id == APIC_ID_ALL) { 545 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 546 if (bootverbose) 547 printf("lapic:"); 548 } else { 549 KASSERT(lapics[apic_id].la_present, 550 ("%s: missing APIC %u", __func__, apic_id)); 551 lapics[apic_id].la_lvts[pin].lvt_active = 1; 552 lapics[apic_id].la_lvts[pin].lvt_activehi = 553 (pol == INTR_POLARITY_HIGH); 554 if (bootverbose) 555 printf("lapic%u:", apic_id); 556 } 557 if (bootverbose) 558 printf(" LINT%u polarity: %s\n", pin, 559 pol == INTR_POLARITY_HIGH ? "high" : "low"); 560 return (0); 561 } 562 563 int 564 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 565 { 566 567 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 568 return (EINVAL); 569 if (apic_id == APIC_ID_ALL) { 570 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 571 if (bootverbose) 572 printf("lapic:"); 573 } else { 574 KASSERT(lapics[apic_id].la_present, 575 ("%s: missing APIC %u", __func__, apic_id)); 576 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 577 (trigger == INTR_TRIGGER_EDGE); 578 lapics[apic_id].la_lvts[pin].lvt_active = 1; 579 if (bootverbose) 580 printf("lapic%u:", apic_id); 581 } 582 if (bootverbose) 583 printf(" LINT%u trigger: %s\n", pin, 584 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 585 return (0); 586 } 587 588 /* 589 * Adjust the TPR of the current CPU so that it blocks all interrupts below 590 * the passed in vector. 591 */ 592 void 593 lapic_set_tpr(u_int vector) 594 { 595 #ifdef CHEAP_TPR 596 lapic->tpr = vector; 597 #else 598 u_int32_t tpr; 599 600 tpr = lapic->tpr & ~APIC_TPR_PRIO; 601 tpr |= vector; 602 lapic->tpr = tpr; 603 #endif 604 } 605 606 void 607 lapic_eoi(void) 608 { 609 610 lapic->eoi = 0; 611 } 612 613 void 614 lapic_handle_intr(struct intrframe frame) 615 { 616 struct intsrc *isrc; 617 618 if (frame.if_vec == -1) 619 panic("Couldn't get vector from ISR!"); 620 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec)); 621 intr_execute_handlers(isrc, &frame); 622 } 623 624 void 625 lapic_handle_timer(struct clockframe frame) 626 { 627 struct lapic *la; 628 629 la = &lapics[PCPU_GET(apic_id)]; 630 (*la->la_timer_count)++; 631 critical_enter(); 632 633 /* Fire hardclock at hz. */ 634 la->la_hard_ticks += hz; 635 if (la->la_hard_ticks >= lapic_timer_hz) { 636 la->la_hard_ticks -= lapic_timer_hz; 637 if (PCPU_GET(cpuid) == 0) 638 hardclock(&frame); 639 else 640 hardclock_process(&frame); 641 } 642 643 /* Fire statclock at stathz. */ 644 la->la_stat_ticks += stathz; 645 if (la->la_stat_ticks >= lapic_timer_hz) { 646 la->la_stat_ticks -= lapic_timer_hz; 647 statclock(&frame); 648 } 649 650 /* Fire profclock at profhz, but only when needed. */ 651 la->la_prof_ticks += profhz; 652 if (la->la_prof_ticks >= lapic_timer_hz) { 653 la->la_prof_ticks -= lapic_timer_hz; 654 if (profprocs != 0) 655 profclock(&frame); 656 } 657 critical_exit(); 658 } 659 660 static void 661 lapic_timer_set_divisor(u_int divisor) 662 { 663 664 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 665 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 666 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 667 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 668 } 669 670 static void 671 lapic_timer_oneshot(u_int count) 672 { 673 u_int32_t value; 674 675 value = lapic->lvt_timer; 676 value &= ~APIC_LVTT_TM; 677 value |= APIC_LVTT_TM_ONE_SHOT; 678 lapic->lvt_timer = value; 679 lapic->icr_timer = count; 680 } 681 682 static void 683 lapic_timer_periodic(u_int count) 684 { 685 u_int32_t value; 686 687 value = lapic->lvt_timer; 688 value &= ~APIC_LVTT_TM; 689 value |= APIC_LVTT_TM_PERIODIC; 690 lapic->lvt_timer = value; 691 lapic->icr_timer = count; 692 } 693 694 static void 695 lapic_timer_enable_intr(void) 696 { 697 u_int32_t value; 698 699 value = lapic->lvt_timer; 700 value &= ~APIC_LVT_M; 701 lapic->lvt_timer = value; 702 } 703 704 /* Request a free IDT vector to be used by the specified IRQ. */ 705 u_int 706 apic_alloc_vector(u_int irq) 707 { 708 u_int vector; 709 710 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 711 712 /* 713 * Search for a free vector. Currently we just use a very simple 714 * algorithm to find the first free vector. 715 */ 716 mtx_lock_spin(&icu_lock); 717 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 718 if (ioint_irqs[vector] != 0) 719 continue; 720 ioint_irqs[vector] = irq; 721 mtx_unlock_spin(&icu_lock); 722 return (vector + APIC_IO_INTS); 723 } 724 mtx_unlock_spin(&icu_lock); 725 panic("Couldn't find an APIC vector for IRQ %u", irq); 726 } 727 728 void 729 apic_enable_vector(u_int vector) 730 { 731 732 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 733 KASSERT(ioint_handlers[vector / 32] != NULL, 734 ("No ISR handler for vector %u", vector)); 735 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 736 GSEL(GCODE_SEL, SEL_KPL)); 737 } 738 739 /* Release an APIC vector when it's no longer in use. */ 740 void 741 apic_free_vector(u_int vector, u_int irq) 742 { 743 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 744 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 745 ("Vector %u does not map to an IRQ line", vector)); 746 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 747 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 748 mtx_lock_spin(&icu_lock); 749 ioint_irqs[vector - APIC_IO_INTS] = 0; 750 mtx_unlock_spin(&icu_lock); 751 } 752 753 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 754 u_int 755 apic_idt_to_irq(u_int vector) 756 { 757 758 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 759 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 760 ("Vector %u does not map to an IRQ line", vector)); 761 return (ioint_irqs[vector - APIC_IO_INTS]); 762 } 763 764 #ifdef DDB 765 /* 766 * Dump data about APIC IDT vector mappings. 767 */ 768 DB_SHOW_COMMAND(apic, db_show_apic) 769 { 770 struct intsrc *isrc; 771 int quit, i, verbose; 772 u_int irq; 773 774 quit = 0; 775 if (strcmp(modif, "vv") == 0) 776 verbose = 2; 777 else if (strcmp(modif, "v") == 0) 778 verbose = 1; 779 else 780 verbose = 0; 781 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 782 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) { 783 irq = ioint_irqs[i]; 784 if (irq != 0 && irq != IRQ_SYSCALL) { 785 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 786 if (irq == IRQ_TIMER) 787 db_printf("lapic timer\n"); 788 else if (irq < NUM_IO_INTS) { 789 isrc = intr_lookup_source(irq); 790 if (isrc == NULL || verbose == 0) 791 db_printf("IRQ %u\n", irq); 792 else 793 db_dump_intr_event(isrc->is_event, 794 verbose == 2); 795 } else 796 db_printf("IRQ %u ???\n", irq); 797 } 798 } 799 } 800 801 static void 802 dump_mask(const char *prefix, uint32_t v, int base) 803 { 804 int i, first; 805 806 first = 1; 807 for (i = 0; i < 32; i++) 808 if (v & (1 << i)) { 809 if (first) { 810 db_printf("%s:", prefix); 811 first = 0; 812 } 813 db_printf(" %02x", base + i); 814 } 815 if (!first) 816 db_printf("\n"); 817 } 818 819 /* Show info from the lapic regs for this CPU. */ 820 DB_SHOW_COMMAND(lapic, db_show_lapic) 821 { 822 uint32_t v; 823 824 db_printf("lapic ID = %d\n", lapic_id()); 825 v = lapic->version; 826 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 827 v & 0xf); 828 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 829 v = lapic->svr; 830 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 831 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 832 db_printf("TPR = %02x\n", lapic->tpr); 833 834 #define dump_field(prefix, index) \ 835 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 836 index * 32) 837 838 db_printf("In-service Interrupts:\n"); 839 dump_field(isr, 0); 840 dump_field(isr, 1); 841 dump_field(isr, 2); 842 dump_field(isr, 3); 843 dump_field(isr, 4); 844 dump_field(isr, 5); 845 dump_field(isr, 6); 846 dump_field(isr, 7); 847 848 db_printf("TMR Interrupts:\n"); 849 dump_field(tmr, 0); 850 dump_field(tmr, 1); 851 dump_field(tmr, 2); 852 dump_field(tmr, 3); 853 dump_field(tmr, 4); 854 dump_field(tmr, 5); 855 dump_field(tmr, 6); 856 dump_field(tmr, 7); 857 858 db_printf("IRR Interrupts:\n"); 859 dump_field(irr, 0); 860 dump_field(irr, 1); 861 dump_field(irr, 2); 862 dump_field(irr, 3); 863 dump_field(irr, 4); 864 dump_field(irr, 5); 865 dump_field(irr, 6); 866 dump_field(irr, 7); 867 868 #undef dump_field 869 } 870 #endif 871 872 /* 873 * APIC probing support code. This includes code to manage enumerators. 874 */ 875 876 static SLIST_HEAD(, apic_enumerator) enumerators = 877 SLIST_HEAD_INITIALIZER(enumerators); 878 static struct apic_enumerator *best_enum; 879 880 void 881 apic_register_enumerator(struct apic_enumerator *enumerator) 882 { 883 #ifdef INVARIANTS 884 struct apic_enumerator *apic_enum; 885 886 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 887 if (apic_enum == enumerator) 888 panic("%s: Duplicate register of %s", __func__, 889 enumerator->apic_name); 890 } 891 #endif 892 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 893 } 894 895 /* 896 * Probe the APIC enumerators, enumerate CPUs, and initialize the 897 * local APIC. 898 */ 899 static void 900 apic_init(void *dummy __unused) 901 { 902 struct apic_enumerator *enumerator; 903 uint64_t apic_base; 904 int retval, best; 905 906 /* We only support built in local APICs. */ 907 if (!(cpu_feature & CPUID_APIC)) 908 return; 909 910 /* Don't probe if APIC mode is disabled. */ 911 if (resource_disabled("apic", 0)) 912 return; 913 914 /* First, probe all the enumerators to find the best match. */ 915 best_enum = NULL; 916 best = 0; 917 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 918 retval = enumerator->apic_probe(); 919 if (retval > 0) 920 continue; 921 if (best_enum == NULL || best < retval) { 922 best_enum = enumerator; 923 best = retval; 924 } 925 } 926 if (best_enum == NULL) { 927 if (bootverbose) 928 printf("APIC: Could not find any APICs.\n"); 929 return; 930 } 931 932 if (bootverbose) 933 printf("APIC: Using the %s enumerator.\n", 934 best_enum->apic_name); 935 936 /* 937 * To work around an errata, we disable the local APIC on some 938 * CPUs during early startup. We need to turn the local APIC back 939 * on on such CPUs now. 940 */ 941 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 942 (cpu_id & 0xff0) == 0x610) { 943 apic_base = rdmsr(MSR_APICBASE); 944 apic_base |= APICBASE_ENABLED; 945 wrmsr(MSR_APICBASE, apic_base); 946 } 947 948 /* Second, probe the CPU's in the system. */ 949 retval = best_enum->apic_probe_cpus(); 950 if (retval != 0) 951 printf("%s: Failed to probe CPUs: returned %d\n", 952 best_enum->apic_name, retval); 953 954 /* Third, initialize the local APIC. */ 955 retval = best_enum->apic_setup_local(); 956 if (retval != 0) 957 printf("%s: Failed to setup the local APIC: returned %d\n", 958 best_enum->apic_name, retval); 959 #ifdef SMP 960 /* Last, setup the cpu topology now that we have probed CPUs */ 961 mp_topology(); 962 #endif 963 } 964 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 965 966 /* 967 * Setup the I/O APICs. 968 */ 969 static void 970 apic_setup_io(void *dummy __unused) 971 { 972 int retval; 973 974 if (best_enum == NULL) 975 return; 976 retval = best_enum->apic_setup_io(); 977 if (retval != 0) 978 printf("%s: Failed to setup I/O APICs: returned %d\n", 979 best_enum->apic_name, retval); 980 981 /* 982 * Finish setting up the local APIC on the BSP once we know how to 983 * properly program the LINT pins. 984 */ 985 lapic_setup(1); 986 intr_register_pic(&lapic_pic); 987 if (bootverbose) 988 lapic_dump("BSP"); 989 } 990 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 991 992 #ifdef SMP 993 /* 994 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 995 * private to the sys/i386 code. The public interface for the rest of the 996 * kernel is defined in mp_machdep.c. 997 */ 998 int 999 lapic_ipi_wait(int delay) 1000 { 1001 int x, incr; 1002 1003 /* 1004 * Wait delay loops for IPI to be sent. This is highly bogus 1005 * since this is sensitive to CPU clock speed. If delay is 1006 * -1, we wait forever. 1007 */ 1008 if (delay == -1) { 1009 incr = 0; 1010 delay = 1; 1011 } else 1012 incr = 1; 1013 for (x = 0; x < delay; x += incr) { 1014 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1015 return (1); 1016 ia32_pause(); 1017 } 1018 return (0); 1019 } 1020 1021 void 1022 lapic_ipi_raw(register_t icrlo, u_int dest) 1023 { 1024 register_t value, eflags; 1025 1026 /* XXX: Need more sanity checking of icrlo? */ 1027 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1028 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1029 ("%s: invalid dest field", __func__)); 1030 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1031 ("%s: reserved bits set in ICR LO register", __func__)); 1032 1033 /* Set destination in ICR HI register if it is being used. */ 1034 eflags = intr_disable(); 1035 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1036 value = lapic->icr_hi; 1037 value &= ~APIC_ID_MASK; 1038 value |= dest << APIC_ID_SHIFT; 1039 lapic->icr_hi = value; 1040 } 1041 1042 /* Program the contents of the IPI and dispatch it. */ 1043 value = lapic->icr_lo; 1044 value &= APIC_ICRLO_RESV_MASK; 1045 value |= icrlo; 1046 lapic->icr_lo = value; 1047 intr_restore(eflags); 1048 } 1049 1050 #define BEFORE_SPIN 1000000 1051 #ifdef DETECT_DEADLOCK 1052 #define AFTER_SPIN 1000 1053 #endif 1054 1055 void 1056 lapic_ipi_vectored(u_int vector, int dest) 1057 { 1058 register_t icrlo, destfield; 1059 1060 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1061 ("%s: invalid vector %d", __func__, vector)); 1062 1063 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1064 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1065 destfield = 0; 1066 switch (dest) { 1067 case APIC_IPI_DEST_SELF: 1068 icrlo |= APIC_DEST_SELF; 1069 break; 1070 case APIC_IPI_DEST_ALL: 1071 icrlo |= APIC_DEST_ALLISELF; 1072 break; 1073 case APIC_IPI_DEST_OTHERS: 1074 icrlo |= APIC_DEST_ALLESELF; 1075 break; 1076 default: 1077 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1078 ("%s: invalid destination 0x%x", __func__, dest)); 1079 destfield = dest; 1080 } 1081 1082 /* Wait for an earlier IPI to finish. */ 1083 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1084 if (panicstr != NULL) 1085 return; 1086 else 1087 panic("APIC: Previous IPI is stuck"); 1088 } 1089 1090 lapic_ipi_raw(icrlo, destfield); 1091 1092 #ifdef DETECT_DEADLOCK 1093 /* Wait for IPI to be delivered. */ 1094 if (!lapic_ipi_wait(AFTER_SPIN)) { 1095 #ifdef needsattention 1096 /* 1097 * XXX FIXME: 1098 * 1099 * The above function waits for the message to actually be 1100 * delivered. It breaks out after an arbitrary timeout 1101 * since the message should eventually be delivered (at 1102 * least in theory) and that if it wasn't we would catch 1103 * the failure with the check above when the next IPI is 1104 * sent. 1105 * 1106 * We could skip this wait entirely, EXCEPT it probably 1107 * protects us from other routines that assume that the 1108 * message was delivered and acted upon when this function 1109 * returns. 1110 */ 1111 printf("APIC: IPI might be stuck\n"); 1112 #else /* !needsattention */ 1113 /* Wait until mesage is sent without a timeout. */ 1114 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1115 ia32_pause(); 1116 #endif /* needsattention */ 1117 } 1118 #endif /* DETECT_DEADLOCK */ 1119 } 1120 #endif /* SMP */
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