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sys/i386/i386/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/6.3/sys/i386/i386/local_apic.c 173886 2007-11-24 19:45:58Z cvs2svn $"); 36 37 #include "opt_hwpmc_hooks.h" 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/pcpu.h> 48 #include <sys/smp.h> 49 50 #include <vm/vm.h> 51 #include <vm/pmap.h> 52 53 #include <machine/apicreg.h> 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/apicvar.h> 58 #include <machine/md_var.h> 59 #include <machine/smp.h> 60 #include <machine/specialreg.h> 61 62 #ifdef DDB 63 #include <sys/interrupt.h> 64 #include <ddb/ddb.h> 65 #endif 66 67 /* Sanity checks on IDT vectors. */ 68 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 69 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 70 CTASSERT(APIC_LOCAL_INTS == 240); 71 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 72 73 #define LAPIC_TIMER_HZ_DIVIDER 2 74 #define LAPIC_TIMER_STATHZ_DIVIDER 15 75 #define LAPIC_TIMER_PROFHZ_DIVIDER 3 76 77 /* Magic IRQ values for the timer and syscalls. */ 78 #define IRQ_TIMER (NUM_IO_INTS + 1) 79 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 80 81 /* 82 * Support for local APICs. Local APICs manage interrupts on each 83 * individual processor as opposed to I/O APICs which receive interrupts 84 * from I/O devices and then forward them on to the local APICs. 85 * 86 * Local APICs can also send interrupts to each other thus providing the 87 * mechanism for IPIs. 88 */ 89 90 struct lvt { 91 u_int lvt_edgetrigger:1; 92 u_int lvt_activehi:1; 93 u_int lvt_masked:1; 94 u_int lvt_active:1; 95 u_int lvt_mode:16; 96 u_int lvt_vector:8; 97 }; 98 99 struct lapic { 100 struct lvt la_lvts[LVT_MAX + 1]; 101 u_int la_id:8; 102 u_int la_cluster:4; 103 u_int la_cluster_id:2; 104 u_int la_present:1; 105 u_long *la_timer_count; 106 u_long la_hard_ticks; 107 u_long la_stat_ticks; 108 u_long la_prof_ticks; 109 } static lapics[MAX_APIC_ID + 1]; 110 111 /* XXX: should thermal be an NMI? */ 112 113 /* Global defaults for local APIC LVT entries. */ 114 static struct lvt lvts[LVT_MAX + 1] = { 115 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 116 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 117 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 118 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 121 }; 122 123 static inthand_t *ioint_handlers[] = { 124 NULL, /* 0 - 31 */ 125 IDTVEC(apic_isr1), /* 32 - 63 */ 126 IDTVEC(apic_isr2), /* 64 - 95 */ 127 IDTVEC(apic_isr3), /* 96 - 127 */ 128 IDTVEC(apic_isr4), /* 128 - 159 */ 129 IDTVEC(apic_isr5), /* 160 - 191 */ 130 IDTVEC(apic_isr6), /* 192 - 223 */ 131 IDTVEC(apic_isr7), /* 224 - 255 */ 132 }; 133 134 /* Include IDT_SYSCALL to make indexing easier. */ 135 static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 136 137 static u_int32_t lapic_timer_divisors[] = { 138 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 139 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 140 }; 141 142 volatile lapic_t *lapic; 143 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 144 145 static void lapic_enable(void); 146 static void lapic_resume(struct pic *pic); 147 static void lapic_timer_enable_intr(void); 148 static void lapic_timer_oneshot(u_int count); 149 static void lapic_timer_periodic(u_int count); 150 static void lapic_timer_set_divisor(u_int divisor); 151 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 152 153 struct pic lapic_pic = { .pic_resume = lapic_resume }; 154 155 static uint32_t 156 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 157 { 158 struct lvt *lvt; 159 160 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 161 if (la->la_lvts[pin].lvt_active) 162 lvt = &la->la_lvts[pin]; 163 else 164 lvt = &lvts[pin]; 165 166 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 167 APIC_LVT_VECTOR); 168 if (lvt->lvt_edgetrigger == 0) 169 value |= APIC_LVT_TM; 170 if (lvt->lvt_activehi == 0) 171 value |= APIC_LVT_IIPP_INTALO; 172 if (lvt->lvt_masked) 173 value |= APIC_LVT_M; 174 value |= lvt->lvt_mode; 175 switch (lvt->lvt_mode) { 176 case APIC_LVT_DM_NMI: 177 case APIC_LVT_DM_SMI: 178 case APIC_LVT_DM_INIT: 179 case APIC_LVT_DM_EXTINT: 180 if (!lvt->lvt_edgetrigger) { 181 printf("lapic%u: Forcing LINT%u to edge trigger\n", 182 la->la_id, pin); 183 value |= APIC_LVT_TM; 184 } 185 /* Use a vector of 0. */ 186 break; 187 case APIC_LVT_DM_FIXED: 188 value |= lvt->lvt_vector; 189 break; 190 default: 191 panic("bad APIC LVT delivery mode: %#x\n", value); 192 } 193 return (value); 194 } 195 196 /* 197 * Map the local APIC and setup necessary interrupt vectors. 198 */ 199 void 200 lapic_init(uintptr_t addr) 201 { 202 203 /* Map the local APIC and setup the spurious interrupt handler. */ 204 KASSERT(trunc_page(addr) == addr, 205 ("local APIC not aligned on a page boundary")); 206 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 207 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 208 GSEL(GCODE_SEL, SEL_KPL)); 209 210 /* Perform basic initialization of the BSP's local APIC. */ 211 lapic_enable(); 212 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 213 214 /* Set BSP's per-CPU local APIC ID. */ 215 PCPU_SET(apic_id, lapic_id()); 216 intr_add_cpu(PCPU_GET(apic_id)); 217 218 /* Local APIC timer interrupt. */ 219 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 220 GSEL(GCODE_SEL, SEL_KPL)); 221 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 222 223 /* XXX: error/thermal interrupts */ 224 } 225 226 /* 227 * Create a local APIC instance. 228 */ 229 void 230 lapic_create(u_int apic_id, int boot_cpu) 231 { 232 int i; 233 234 if (apic_id > MAX_APIC_ID) { 235 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 236 if (boot_cpu) 237 panic("Can't ignore BSP"); 238 return; 239 } 240 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 241 apic_id)); 242 243 /* 244 * Assume no local LVT overrides and a cluster of 0 and 245 * intra-cluster ID of 0. 246 */ 247 lapics[apic_id].la_present = 1; 248 lapics[apic_id].la_id = apic_id; 249 for (i = 0; i < LVT_MAX; i++) { 250 lapics[apic_id].la_lvts[i] = lvts[i]; 251 lapics[apic_id].la_lvts[i].lvt_active = 0; 252 } 253 254 #ifdef SMP 255 cpu_add(apic_id, boot_cpu); 256 #endif 257 } 258 259 /* 260 * Dump contents of local APIC registers 261 */ 262 void 263 lapic_dump(const char* str) 264 { 265 266 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 267 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 268 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 269 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 270 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 271 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 272 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 273 lapic->lvt_pcint); 274 } 275 276 void 277 lapic_setup(int boot) 278 { 279 struct lapic *la; 280 u_int32_t maxlvt; 281 register_t eflags; 282 char buf[MAXCOMLEN + 1]; 283 284 la = &lapics[lapic_id()]; 285 KASSERT(la->la_present, ("missing APIC structure")); 286 eflags = intr_disable(); 287 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 288 289 /* Initialize the TPR to allow all interrupts. */ 290 lapic_set_tpr(0); 291 292 /* Setup spurious vector and enable the local APIC. */ 293 lapic_enable(); 294 295 /* Program LINT[01] LVT entries. */ 296 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 297 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 298 #ifdef HWPMC_HOOKS 299 /* Program the PMC LVT entry if present. */ 300 if (maxlvt >= LVT_PMC) 301 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 302 #endif 303 304 /* Program timer LVT and setup handler. */ 305 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 306 if (boot) { 307 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 308 intrcnt_add(buf, &la->la_timer_count); 309 } 310 311 /* We don't setup the timer during boot on the BSP until later. */ 312 if (!(boot && PCPU_GET(cpuid) == 0)) { 313 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 314 lapic_id())); 315 lapic_timer_set_divisor(lapic_timer_divisor); 316 lapic_timer_periodic(lapic_timer_period); 317 lapic_timer_enable_intr(); 318 } 319 320 /* XXX: Error and thermal LVTs */ 321 322 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 323 /* 324 * Detect the presence of C1E capability mostly on latest 325 * dual-cores (or future) k8 family. This feature renders 326 * the local APIC timer dead, so we disable it by reading 327 * the Interrupt Pending Message register and clearing both 328 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 329 * 330 * Reference: 331 * "BIOS and Kernel Developer's Guide for AMD NPT 332 * Family 0Fh Processors" 333 * #32559 revision 3.00 334 */ 335 if ((cpu_id & 0x00000f00) == 0x00000f00 && 336 (cpu_id & 0x0fff0000) >= 0x00040000) { 337 uint64_t msr; 338 339 msr = rdmsr(0xc0010055); 340 if (msr & 0x18000000) 341 wrmsr(0xc0010055, msr & ~0x18000000ULL); 342 } 343 } 344 345 intr_restore(eflags); 346 } 347 348 /* 349 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 350 * that it can drive hardclock, statclock, and profclock. This function 351 * returns true if it is able to use the local APIC timer to drive the 352 * clocks and false if it is not able. 353 */ 354 int 355 lapic_setup_clock(void) 356 { 357 u_long value; 358 359 /* Can't drive the timer without a local APIC. */ 360 if (lapic == NULL) 361 return (0); 362 363 /* Start off with a divisor of 2 (power on reset default). */ 364 lapic_timer_divisor = 2; 365 366 /* Try to calibrate the local APIC timer. */ 367 do { 368 lapic_timer_set_divisor(lapic_timer_divisor); 369 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 370 DELAY(2000000); 371 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 372 if (value != APIC_TIMER_MAX_COUNT) 373 break; 374 lapic_timer_divisor <<= 1; 375 } while (lapic_timer_divisor <= 128); 376 if (lapic_timer_divisor > 128) 377 panic("lapic: Divisor too big"); 378 value /= 2; 379 if (bootverbose) 380 printf("lapic: Divisor %lu, Frequency %lu hz\n", 381 lapic_timer_divisor, value); 382 383 /* 384 * We will drive the timer at a small multiple of hz and drive 385 * both of the other timers with similarly small but relatively 386 * prime divisors. 387 */ 388 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 389 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 390 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 391 lapic_timer_period = value / lapic_timer_hz; 392 393 /* 394 * Start up the timer on the BSP. The APs will kick off their 395 * timer during lapic_setup(). 396 */ 397 lapic_timer_periodic(lapic_timer_period); 398 lapic_timer_enable_intr(); 399 return (1); 400 } 401 402 void 403 lapic_disable(void) 404 { 405 uint32_t value; 406 407 /* Software disable the local APIC. */ 408 value = lapic->svr; 409 value &= ~APIC_SVR_SWEN; 410 lapic->svr = value; 411 } 412 413 static void 414 lapic_enable(void) 415 { 416 u_int32_t value; 417 418 /* Program the spurious vector to enable the local APIC. */ 419 value = lapic->svr; 420 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 421 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 422 lapic->svr = value; 423 } 424 425 /* Reset the local APIC on the BSP during resume. */ 426 static void 427 lapic_resume(struct pic *pic) 428 { 429 430 lapic_setup(0); 431 } 432 433 int 434 lapic_id(void) 435 { 436 437 KASSERT(lapic != NULL, ("local APIC is not mapped")); 438 return (lapic->id >> APIC_ID_SHIFT); 439 } 440 441 int 442 lapic_intr_pending(u_int vector) 443 { 444 volatile u_int32_t *irr; 445 446 /* 447 * The IRR registers are an array of 128-bit registers each of 448 * which only describes 32 interrupts in the low 32 bits.. Thus, 449 * we divide the vector by 32 to get the 128-bit index. We then 450 * multiply that index by 4 to get the equivalent index from 451 * treating the IRR as an array of 32-bit registers. Finally, we 452 * modulus the vector by 32 to determine the individual bit to 453 * test. 454 */ 455 irr = &lapic->irr0; 456 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 457 } 458 459 void 460 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 461 { 462 struct lapic *la; 463 464 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 465 __func__, apic_id)); 466 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 467 __func__, cluster)); 468 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 469 ("%s: intra cluster id %u too big", __func__, cluster_id)); 470 la = &lapics[apic_id]; 471 la->la_cluster = cluster; 472 la->la_cluster_id = cluster_id; 473 } 474 475 int 476 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 477 { 478 479 if (pin > LVT_MAX) 480 return (EINVAL); 481 if (apic_id == APIC_ID_ALL) { 482 lvts[pin].lvt_masked = masked; 483 if (bootverbose) 484 printf("lapic:"); 485 } else { 486 KASSERT(lapics[apic_id].la_present, 487 ("%s: missing APIC %u", __func__, apic_id)); 488 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 489 lapics[apic_id].la_lvts[pin].lvt_active = 1; 490 if (bootverbose) 491 printf("lapic%u:", apic_id); 492 } 493 if (bootverbose) 494 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 495 return (0); 496 } 497 498 int 499 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 500 { 501 struct lvt *lvt; 502 503 if (pin > LVT_MAX) 504 return (EINVAL); 505 if (apic_id == APIC_ID_ALL) { 506 lvt = &lvts[pin]; 507 if (bootverbose) 508 printf("lapic:"); 509 } else { 510 KASSERT(lapics[apic_id].la_present, 511 ("%s: missing APIC %u", __func__, apic_id)); 512 lvt = &lapics[apic_id].la_lvts[pin]; 513 lvt->lvt_active = 1; 514 if (bootverbose) 515 printf("lapic%u:", apic_id); 516 } 517 lvt->lvt_mode = mode; 518 switch (mode) { 519 case APIC_LVT_DM_NMI: 520 case APIC_LVT_DM_SMI: 521 case APIC_LVT_DM_INIT: 522 case APIC_LVT_DM_EXTINT: 523 lvt->lvt_edgetrigger = 1; 524 lvt->lvt_activehi = 1; 525 if (mode == APIC_LVT_DM_EXTINT) 526 lvt->lvt_masked = 1; 527 else 528 lvt->lvt_masked = 0; 529 break; 530 default: 531 panic("Unsupported delivery mode: 0x%x\n", mode); 532 } 533 if (bootverbose) { 534 printf(" Routing "); 535 switch (mode) { 536 case APIC_LVT_DM_NMI: 537 printf("NMI"); 538 break; 539 case APIC_LVT_DM_SMI: 540 printf("SMI"); 541 break; 542 case APIC_LVT_DM_INIT: 543 printf("INIT"); 544 break; 545 case APIC_LVT_DM_EXTINT: 546 printf("ExtINT"); 547 break; 548 } 549 printf(" -> LINT%u\n", pin); 550 } 551 return (0); 552 } 553 554 int 555 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 556 { 557 558 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 559 return (EINVAL); 560 if (apic_id == APIC_ID_ALL) { 561 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 562 if (bootverbose) 563 printf("lapic:"); 564 } else { 565 KASSERT(lapics[apic_id].la_present, 566 ("%s: missing APIC %u", __func__, apic_id)); 567 lapics[apic_id].la_lvts[pin].lvt_active = 1; 568 lapics[apic_id].la_lvts[pin].lvt_activehi = 569 (pol == INTR_POLARITY_HIGH); 570 if (bootverbose) 571 printf("lapic%u:", apic_id); 572 } 573 if (bootverbose) 574 printf(" LINT%u polarity: %s\n", pin, 575 pol == INTR_POLARITY_HIGH ? "high" : "low"); 576 return (0); 577 } 578 579 int 580 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 581 { 582 583 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 584 return (EINVAL); 585 if (apic_id == APIC_ID_ALL) { 586 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 587 if (bootverbose) 588 printf("lapic:"); 589 } else { 590 KASSERT(lapics[apic_id].la_present, 591 ("%s: missing APIC %u", __func__, apic_id)); 592 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 593 (trigger == INTR_TRIGGER_EDGE); 594 lapics[apic_id].la_lvts[pin].lvt_active = 1; 595 if (bootverbose) 596 printf("lapic%u:", apic_id); 597 } 598 if (bootverbose) 599 printf(" LINT%u trigger: %s\n", pin, 600 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 601 return (0); 602 } 603 604 /* 605 * Adjust the TPR of the current CPU so that it blocks all interrupts below 606 * the passed in vector. 607 */ 608 void 609 lapic_set_tpr(u_int vector) 610 { 611 #ifdef CHEAP_TPR 612 lapic->tpr = vector; 613 #else 614 u_int32_t tpr; 615 616 tpr = lapic->tpr & ~APIC_TPR_PRIO; 617 tpr |= vector; 618 lapic->tpr = tpr; 619 #endif 620 } 621 622 void 623 lapic_eoi(void) 624 { 625 626 lapic->eoi = 0; 627 } 628 629 void 630 lapic_handle_intr(struct intrframe frame) 631 { 632 struct intsrc *isrc; 633 634 if (frame.if_vec == -1) 635 panic("Couldn't get vector from ISR!"); 636 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec)); 637 intr_execute_handlers(isrc, &frame); 638 } 639 640 void 641 lapic_handle_timer(struct clockframe frame) 642 { 643 struct lapic *la; 644 645 #if defined(SMP) && !defined(SCHED_ULE) 646 /* 647 * Don't do any accounting for the disabled HTT cores, since it 648 * will provide misleading numbers for the userland. 649 * 650 * No locking is necessary here, since even if we loose the race 651 * when hlt_cpus_mask changes it is not a big deal, really. 652 * 653 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 654 * and unlike other schedulers it actually schedules threads to 655 * those CPUs. 656 */ 657 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 658 return; 659 #endif 660 661 la = &lapics[PCPU_GET(apic_id)]; 662 (*la->la_timer_count)++; 663 critical_enter(); 664 665 /* Fire hardclock at hz. */ 666 la->la_hard_ticks += hz; 667 if (la->la_hard_ticks >= lapic_timer_hz) { 668 la->la_hard_ticks -= lapic_timer_hz; 669 if (PCPU_GET(cpuid) == 0) 670 hardclock(&frame); 671 else 672 hardclock_process(&frame); 673 } 674 675 /* Fire statclock at stathz. */ 676 la->la_stat_ticks += stathz; 677 if (la->la_stat_ticks >= lapic_timer_hz) { 678 la->la_stat_ticks -= lapic_timer_hz; 679 statclock(&frame); 680 } 681 682 /* Fire profclock at profhz, but only when needed. */ 683 la->la_prof_ticks += profhz; 684 if (la->la_prof_ticks >= lapic_timer_hz) { 685 la->la_prof_ticks -= lapic_timer_hz; 686 if (profprocs != 0) 687 profclock(&frame); 688 } 689 critical_exit(); 690 } 691 692 static void 693 lapic_timer_set_divisor(u_int divisor) 694 { 695 696 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 697 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 698 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 699 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 700 } 701 702 static void 703 lapic_timer_oneshot(u_int count) 704 { 705 u_int32_t value; 706 707 value = lapic->lvt_timer; 708 value &= ~APIC_LVTT_TM; 709 value |= APIC_LVTT_TM_ONE_SHOT; 710 lapic->lvt_timer = value; 711 lapic->icr_timer = count; 712 } 713 714 static void 715 lapic_timer_periodic(u_int count) 716 { 717 u_int32_t value; 718 719 value = lapic->lvt_timer; 720 value &= ~APIC_LVTT_TM; 721 value |= APIC_LVTT_TM_PERIODIC; 722 lapic->lvt_timer = value; 723 lapic->icr_timer = count; 724 } 725 726 static void 727 lapic_timer_enable_intr(void) 728 { 729 u_int32_t value; 730 731 value = lapic->lvt_timer; 732 value &= ~APIC_LVT_M; 733 lapic->lvt_timer = value; 734 } 735 736 /* Request a free IDT vector to be used by the specified IRQ. */ 737 u_int 738 apic_alloc_vector(u_int irq) 739 { 740 u_int vector; 741 742 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 743 744 /* 745 * Search for a free vector. Currently we just use a very simple 746 * algorithm to find the first free vector. 747 */ 748 mtx_lock_spin(&icu_lock); 749 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 750 if (ioint_irqs[vector] != 0) 751 continue; 752 ioint_irqs[vector] = irq; 753 mtx_unlock_spin(&icu_lock); 754 return (vector + APIC_IO_INTS); 755 } 756 mtx_unlock_spin(&icu_lock); 757 panic("Couldn't find an APIC vector for IRQ %u", irq); 758 } 759 760 /* 761 * Request 'count' free contiguous IDT vectors to be used by 'count' 762 * IRQs. 'count' must be a power of two and the vectors will be 763 * aligned on a boundary of 'align'. If the request cannot be 764 * satisfied, 0 is returned. 765 */ 766 u_int 767 apic_alloc_vectors(u_int *irqs, u_int count, u_int align) 768 { 769 u_int first, run, vector; 770 771 KASSERT(powerof2(count), ("bad count")); 772 KASSERT(powerof2(align), ("bad align")); 773 KASSERT(align >= count, ("align < count")); 774 #ifdef INVARIANTS 775 for (run = 0; run < count; run++) 776 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 777 irqs[run], run)); 778 #endif 779 780 /* 781 * Search for 'count' free vectors. As with apic_alloc_vector(), 782 * this just uses a simple first fit algorithm. 783 */ 784 run = 0; 785 first = 0; 786 mtx_lock_spin(&icu_lock); 787 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 788 789 /* Vector is in use, end run. */ 790 if (ioint_irqs[vector] != 0) { 791 run = 0; 792 first = 0; 793 continue; 794 } 795 796 /* Start a new run if run == 0 and vector is aligned. */ 797 if (run == 0) { 798 if ((vector & (align - 1)) != 0) 799 continue; 800 first = vector; 801 } 802 run++; 803 804 /* Keep looping if the run isn't long enough yet. */ 805 if (run < count) 806 continue; 807 808 /* Found a run, assign IRQs and return the first vector. */ 809 for (vector = 0; vector < count; vector++) 810 ioint_irqs[first + vector] = irqs[vector]; 811 mtx_unlock_spin(&icu_lock); 812 return (first + APIC_IO_INTS); 813 } 814 mtx_unlock_spin(&icu_lock); 815 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 816 return (0); 817 } 818 819 void 820 apic_enable_vector(u_int vector) 821 { 822 823 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 824 KASSERT(ioint_handlers[vector / 32] != NULL, 825 ("No ISR handler for vector %u", vector)); 826 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 827 GSEL(GCODE_SEL, SEL_KPL)); 828 } 829 830 /* Release an APIC vector when it's no longer in use. */ 831 void 832 apic_free_vector(u_int vector, u_int irq) 833 { 834 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 835 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 836 ("Vector %u does not map to an IRQ line", vector)); 837 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 838 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 839 mtx_lock_spin(&icu_lock); 840 ioint_irqs[vector - APIC_IO_INTS] = 0; 841 mtx_unlock_spin(&icu_lock); 842 } 843 844 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 845 u_int 846 apic_idt_to_irq(u_int vector) 847 { 848 849 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 850 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 851 ("Vector %u does not map to an IRQ line", vector)); 852 return (ioint_irqs[vector - APIC_IO_INTS]); 853 } 854 855 #ifdef DDB 856 /* 857 * Dump data about APIC IDT vector mappings. 858 */ 859 DB_SHOW_COMMAND(apic, db_show_apic) 860 { 861 struct intsrc *isrc; 862 int quit, i, verbose; 863 u_int irq; 864 865 quit = 0; 866 if (strcmp(modif, "vv") == 0) 867 verbose = 2; 868 else if (strcmp(modif, "v") == 0) 869 verbose = 1; 870 else 871 verbose = 0; 872 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 873 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) { 874 irq = ioint_irqs[i]; 875 if (irq != 0 && irq != IRQ_SYSCALL) { 876 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 877 if (irq == IRQ_TIMER) 878 db_printf("lapic timer\n"); 879 else if (irq < NUM_IO_INTS) { 880 isrc = intr_lookup_source(irq); 881 if (isrc == NULL || verbose == 0) 882 db_printf("IRQ %u\n", irq); 883 else 884 db_dump_intr_event(isrc->is_event, 885 verbose == 2); 886 } else 887 db_printf("IRQ %u ???\n", irq); 888 } 889 } 890 } 891 892 static void 893 dump_mask(const char *prefix, uint32_t v, int base) 894 { 895 int i, first; 896 897 first = 1; 898 for (i = 0; i < 32; i++) 899 if (v & (1 << i)) { 900 if (first) { 901 db_printf("%s:", prefix); 902 first = 0; 903 } 904 db_printf(" %02x", base + i); 905 } 906 if (!first) 907 db_printf("\n"); 908 } 909 910 /* Show info from the lapic regs for this CPU. */ 911 DB_SHOW_COMMAND(lapic, db_show_lapic) 912 { 913 uint32_t v; 914 915 db_printf("lapic ID = %d\n", lapic_id()); 916 v = lapic->version; 917 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 918 v & 0xf); 919 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 920 v = lapic->svr; 921 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 922 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 923 db_printf("TPR = %02x\n", lapic->tpr); 924 925 #define dump_field(prefix, index) \ 926 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 927 index * 32) 928 929 db_printf("In-service Interrupts:\n"); 930 dump_field(isr, 0); 931 dump_field(isr, 1); 932 dump_field(isr, 2); 933 dump_field(isr, 3); 934 dump_field(isr, 4); 935 dump_field(isr, 5); 936 dump_field(isr, 6); 937 dump_field(isr, 7); 938 939 db_printf("TMR Interrupts:\n"); 940 dump_field(tmr, 0); 941 dump_field(tmr, 1); 942 dump_field(tmr, 2); 943 dump_field(tmr, 3); 944 dump_field(tmr, 4); 945 dump_field(tmr, 5); 946 dump_field(tmr, 6); 947 dump_field(tmr, 7); 948 949 db_printf("IRR Interrupts:\n"); 950 dump_field(irr, 0); 951 dump_field(irr, 1); 952 dump_field(irr, 2); 953 dump_field(irr, 3); 954 dump_field(irr, 4); 955 dump_field(irr, 5); 956 dump_field(irr, 6); 957 dump_field(irr, 7); 958 959 #undef dump_field 960 } 961 #endif 962 963 /* 964 * APIC probing support code. This includes code to manage enumerators. 965 */ 966 967 static SLIST_HEAD(, apic_enumerator) enumerators = 968 SLIST_HEAD_INITIALIZER(enumerators); 969 static struct apic_enumerator *best_enum; 970 971 void 972 apic_register_enumerator(struct apic_enumerator *enumerator) 973 { 974 #ifdef INVARIANTS 975 struct apic_enumerator *apic_enum; 976 977 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 978 if (apic_enum == enumerator) 979 panic("%s: Duplicate register of %s", __func__, 980 enumerator->apic_name); 981 } 982 #endif 983 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 984 } 985 986 /* 987 * Probe the APIC enumerators, enumerate CPUs, and initialize the 988 * local APIC. 989 */ 990 static void 991 apic_init(void *dummy __unused) 992 { 993 struct apic_enumerator *enumerator; 994 uint64_t apic_base; 995 int retval, best; 996 997 /* We only support built in local APICs. */ 998 if (!(cpu_feature & CPUID_APIC)) 999 return; 1000 1001 /* Don't probe if APIC mode is disabled. */ 1002 if (resource_disabled("apic", 0)) 1003 return; 1004 1005 /* First, probe all the enumerators to find the best match. */ 1006 best_enum = NULL; 1007 best = 0; 1008 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1009 retval = enumerator->apic_probe(); 1010 if (retval > 0) 1011 continue; 1012 if (best_enum == NULL || best < retval) { 1013 best_enum = enumerator; 1014 best = retval; 1015 } 1016 } 1017 if (best_enum == NULL) { 1018 if (bootverbose) 1019 printf("APIC: Could not find any APICs.\n"); 1020 return; 1021 } 1022 1023 if (bootverbose) 1024 printf("APIC: Using the %s enumerator.\n", 1025 best_enum->apic_name); 1026 1027 /* 1028 * To work around an errata, we disable the local APIC on some 1029 * CPUs during early startup. We need to turn the local APIC back 1030 * on on such CPUs now. 1031 */ 1032 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 1033 (cpu_id & 0xff0) == 0x610) { 1034 apic_base = rdmsr(MSR_APICBASE); 1035 apic_base |= APICBASE_ENABLED; 1036 wrmsr(MSR_APICBASE, apic_base); 1037 } 1038 1039 /* Second, probe the CPU's in the system. */ 1040 retval = best_enum->apic_probe_cpus(); 1041 if (retval != 0) 1042 printf("%s: Failed to probe CPUs: returned %d\n", 1043 best_enum->apic_name, retval); 1044 1045 /* Third, initialize the local APIC. */ 1046 retval = best_enum->apic_setup_local(); 1047 if (retval != 0) 1048 printf("%s: Failed to setup the local APIC: returned %d\n", 1049 best_enum->apic_name, retval); 1050 #ifdef SMP 1051 /* Last, setup the cpu topology now that we have probed CPUs */ 1052 mp_topology(); 1053 #endif 1054 } 1055 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 1056 1057 /* 1058 * Setup the I/O APICs. 1059 */ 1060 static void 1061 apic_setup_io(void *dummy __unused) 1062 { 1063 int retval; 1064 1065 if (best_enum == NULL) 1066 return; 1067 retval = best_enum->apic_setup_io(); 1068 if (retval != 0) 1069 printf("%s: Failed to setup I/O APICs: returned %d\n", 1070 best_enum->apic_name, retval); 1071 1072 /* 1073 * Finish setting up the local APIC on the BSP once we know how to 1074 * properly program the LINT pins. 1075 */ 1076 lapic_setup(1); 1077 intr_register_pic(&lapic_pic); 1078 if (bootverbose) 1079 lapic_dump("BSP"); 1080 1081 /* Enable the MSI "pic". */ 1082 msi_init(); 1083 } 1084 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 1085 1086 #ifdef SMP 1087 /* 1088 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1089 * private to the sys/i386 code. The public interface for the rest of the 1090 * kernel is defined in mp_machdep.c. 1091 */ 1092 int 1093 lapic_ipi_wait(int delay) 1094 { 1095 int x, incr; 1096 1097 /* 1098 * Wait delay loops for IPI to be sent. This is highly bogus 1099 * since this is sensitive to CPU clock speed. If delay is 1100 * -1, we wait forever. 1101 */ 1102 if (delay == -1) { 1103 incr = 0; 1104 delay = 1; 1105 } else 1106 incr = 1; 1107 for (x = 0; x < delay; x += incr) { 1108 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1109 return (1); 1110 ia32_pause(); 1111 } 1112 return (0); 1113 } 1114 1115 void 1116 lapic_ipi_raw(register_t icrlo, u_int dest) 1117 { 1118 register_t value, eflags; 1119 1120 /* XXX: Need more sanity checking of icrlo? */ 1121 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1122 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1123 ("%s: invalid dest field", __func__)); 1124 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1125 ("%s: reserved bits set in ICR LO register", __func__)); 1126 1127 /* Set destination in ICR HI register if it is being used. */ 1128 eflags = intr_disable(); 1129 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1130 value = lapic->icr_hi; 1131 value &= ~APIC_ID_MASK; 1132 value |= dest << APIC_ID_SHIFT; 1133 lapic->icr_hi = value; 1134 } 1135 1136 /* Program the contents of the IPI and dispatch it. */ 1137 value = lapic->icr_lo; 1138 value &= APIC_ICRLO_RESV_MASK; 1139 value |= icrlo; 1140 lapic->icr_lo = value; 1141 intr_restore(eflags); 1142 } 1143 1144 #define BEFORE_SPIN 1000000 1145 #ifdef DETECT_DEADLOCK 1146 #define AFTER_SPIN 1000 1147 #endif 1148 1149 void 1150 lapic_ipi_vectored(u_int vector, int dest) 1151 { 1152 register_t icrlo, destfield; 1153 1154 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1155 ("%s: invalid vector %d", __func__, vector)); 1156 1157 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1158 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1159 destfield = 0; 1160 switch (dest) { 1161 case APIC_IPI_DEST_SELF: 1162 icrlo |= APIC_DEST_SELF; 1163 break; 1164 case APIC_IPI_DEST_ALL: 1165 icrlo |= APIC_DEST_ALLISELF; 1166 break; 1167 case APIC_IPI_DEST_OTHERS: 1168 icrlo |= APIC_DEST_ALLESELF; 1169 break; 1170 default: 1171 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1172 ("%s: invalid destination 0x%x", __func__, dest)); 1173 destfield = dest; 1174 } 1175 1176 /* Wait for an earlier IPI to finish. */ 1177 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1178 if (panicstr != NULL) 1179 return; 1180 else 1181 panic("APIC: Previous IPI is stuck"); 1182 } 1183 1184 lapic_ipi_raw(icrlo, destfield); 1185 1186 #ifdef DETECT_DEADLOCK 1187 /* Wait for IPI to be delivered. */ 1188 if (!lapic_ipi_wait(AFTER_SPIN)) { 1189 #ifdef needsattention 1190 /* 1191 * XXX FIXME: 1192 * 1193 * The above function waits for the message to actually be 1194 * delivered. It breaks out after an arbitrary timeout 1195 * since the message should eventually be delivered (at 1196 * least in theory) and that if it wasn't we would catch 1197 * the failure with the check above when the next IPI is 1198 * sent. 1199 * 1200 * We could skip this wait entirely, EXCEPT it probably 1201 * protects us from other routines that assume that the 1202 * message was delivered and acted upon when this function 1203 * returns. 1204 */ 1205 printf("APIC: IPI might be stuck\n"); 1206 #else /* !needsattention */ 1207 /* Wait until mesage is sent without a timeout. */ 1208 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1209 ia32_pause(); 1210 #endif /* needsattention */ 1211 } 1212 #endif /* DETECT_DEADLOCK */ 1213 } 1214 #endif /* SMP */
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