1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include "opt_hwpmc_hooks.h"
38
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/pcpu.h>
48 #include <sys/smp.h>
49
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52
53 #include <machine/apicreg.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/apicvar.h>
58 #include <machine/md_var.h>
59 #include <machine/smp.h>
60 #include <machine/specialreg.h>
61
62 #ifdef DDB
63 #include <sys/interrupt.h>
64 #include <ddb/ddb.h>
65 #endif
66
67 /* Sanity checks on IDT vectors. */
68 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
69 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
70 CTASSERT(APIC_LOCAL_INTS == 240);
71 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
72
73 /* Magic IRQ values for the timer and syscalls. */
74 #define IRQ_TIMER (NUM_IO_INTS + 1)
75 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
76
77 /*
78 * Support for local APICs. Local APICs manage interrupts on each
79 * individual processor as opposed to I/O APICs which receive interrupts
80 * from I/O devices and then forward them on to the local APICs.
81 *
82 * Local APICs can also send interrupts to each other thus providing the
83 * mechanism for IPIs.
84 */
85
86 struct lvt {
87 u_int lvt_edgetrigger:1;
88 u_int lvt_activehi:1;
89 u_int lvt_masked:1;
90 u_int lvt_active:1;
91 u_int lvt_mode:16;
92 u_int lvt_vector:8;
93 };
94
95 struct lapic {
96 struct lvt la_lvts[LVT_MAX + 1];
97 u_int la_id:8;
98 u_int la_cluster:4;
99 u_int la_cluster_id:2;
100 u_int la_present:1;
101 u_long *la_timer_count;
102 u_long la_hard_ticks;
103 u_long la_stat_ticks;
104 u_long la_prof_ticks;
105 } static lapics[MAX_APIC_ID + 1];
106
107 /* XXX: should thermal be an NMI? */
108
109 /* Global defaults for local APIC LVT entries. */
110 static struct lvt lvts[LVT_MAX + 1] = {
111 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
112 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
113 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
114 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
115 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
116 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
117 };
118
119 static inthand_t *ioint_handlers[] = {
120 NULL, /* 0 - 31 */
121 IDTVEC(apic_isr1), /* 32 - 63 */
122 IDTVEC(apic_isr2), /* 64 - 95 */
123 IDTVEC(apic_isr3), /* 96 - 127 */
124 IDTVEC(apic_isr4), /* 128 - 159 */
125 IDTVEC(apic_isr5), /* 160 - 191 */
126 IDTVEC(apic_isr6), /* 192 - 223 */
127 IDTVEC(apic_isr7), /* 224 - 255 */
128 };
129
130 /* Include IDT_SYSCALL to make indexing easier. */
131 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
132
133 static u_int32_t lapic_timer_divisors[] = {
134 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
135 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
136 };
137
138 volatile lapic_t *lapic;
139 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
140
141 static void lapic_enable(void);
142 static void lapic_resume(struct pic *pic);
143 static void lapic_timer_enable_intr(void);
144 static void lapic_timer_oneshot(u_int count);
145 static void lapic_timer_periodic(u_int count);
146 static void lapic_timer_set_divisor(u_int divisor);
147 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
148
149 struct pic lapic_pic = { .pic_resume = lapic_resume };
150
151 static uint32_t
152 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
153 {
154 struct lvt *lvt;
155
156 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
157 if (la->la_lvts[pin].lvt_active)
158 lvt = &la->la_lvts[pin];
159 else
160 lvt = &lvts[pin];
161
162 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
163 APIC_LVT_VECTOR);
164 if (lvt->lvt_edgetrigger == 0)
165 value |= APIC_LVT_TM;
166 if (lvt->lvt_activehi == 0)
167 value |= APIC_LVT_IIPP_INTALO;
168 if (lvt->lvt_masked)
169 value |= APIC_LVT_M;
170 value |= lvt->lvt_mode;
171 switch (lvt->lvt_mode) {
172 case APIC_LVT_DM_NMI:
173 case APIC_LVT_DM_SMI:
174 case APIC_LVT_DM_INIT:
175 case APIC_LVT_DM_EXTINT:
176 if (!lvt->lvt_edgetrigger) {
177 printf("lapic%u: Forcing LINT%u to edge trigger\n",
178 la->la_id, pin);
179 value |= APIC_LVT_TM;
180 }
181 /* Use a vector of 0. */
182 break;
183 case APIC_LVT_DM_FIXED:
184 value |= lvt->lvt_vector;
185 break;
186 default:
187 panic("bad APIC LVT delivery mode: %#x\n", value);
188 }
189 return (value);
190 }
191
192 /*
193 * Map the local APIC and setup necessary interrupt vectors.
194 */
195 void
196 lapic_init(uintptr_t addr)
197 {
198
199 /* Map the local APIC and setup the spurious interrupt handler. */
200 KASSERT(trunc_page(addr) == addr,
201 ("local APIC not aligned on a page boundary"));
202 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
203 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
204 GSEL(GCODE_SEL, SEL_KPL));
205
206 /* Perform basic initialization of the BSP's local APIC. */
207 lapic_enable();
208 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
209
210 /* Set BSP's per-CPU local APIC ID. */
211 PCPU_SET(apic_id, lapic_id());
212 intr_add_cpu(PCPU_GET(apic_id));
213
214 /* Local APIC timer interrupt. */
215 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
216 GSEL(GCODE_SEL, SEL_KPL));
217 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
218
219 /* XXX: error/thermal interrupts */
220 }
221
222 /*
223 * Create a local APIC instance.
224 */
225 void
226 lapic_create(u_int apic_id, int boot_cpu)
227 {
228 int i;
229
230 if (apic_id > MAX_APIC_ID) {
231 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
232 if (boot_cpu)
233 panic("Can't ignore BSP");
234 return;
235 }
236 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
237 apic_id));
238
239 /*
240 * Assume no local LVT overrides and a cluster of 0 and
241 * intra-cluster ID of 0.
242 */
243 lapics[apic_id].la_present = 1;
244 lapics[apic_id].la_id = apic_id;
245 for (i = 0; i < LVT_MAX; i++) {
246 lapics[apic_id].la_lvts[i] = lvts[i];
247 lapics[apic_id].la_lvts[i].lvt_active = 0;
248 }
249
250 #ifdef SMP
251 cpu_add(apic_id, boot_cpu);
252 #endif
253 }
254
255 /*
256 * Dump contents of local APIC registers
257 */
258 void
259 lapic_dump(const char* str)
260 {
261
262 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
263 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
264 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
265 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
266 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
267 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
268 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
269 lapic->lvt_pcint);
270 }
271
272 void
273 lapic_setup(int boot)
274 {
275 struct lapic *la;
276 u_int32_t maxlvt;
277 register_t eflags;
278 char buf[MAXCOMLEN + 1];
279
280 la = &lapics[lapic_id()];
281 KASSERT(la->la_present, ("missing APIC structure"));
282 eflags = intr_disable();
283 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
284
285 /* Initialize the TPR to allow all interrupts. */
286 lapic_set_tpr(0);
287
288 /* Setup spurious vector and enable the local APIC. */
289 lapic_enable();
290
291 /* Program LINT[01] LVT entries. */
292 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
293 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
294 #ifdef HWPMC_HOOKS
295 /* Program the PMC LVT entry if present. */
296 if (maxlvt >= LVT_PMC)
297 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
298 #endif
299
300 /* Program timer LVT and setup handler. */
301 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
302 if (boot) {
303 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
304 intrcnt_add(buf, &la->la_timer_count);
305 }
306
307 /* We don't setup the timer during boot on the BSP until later. */
308 if (!(boot && PCPU_GET(cpuid) == 0)) {
309 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
310 lapic_id()));
311 lapic_timer_set_divisor(lapic_timer_divisor);
312 lapic_timer_periodic(lapic_timer_period);
313 lapic_timer_enable_intr();
314 }
315
316 /* XXX: Error and thermal LVTs */
317
318 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
319 /*
320 * Detect the presence of C1E capability mostly on latest
321 * dual-cores (or future) k8 family. This feature renders
322 * the local APIC timer dead, so we disable it by reading
323 * the Interrupt Pending Message register and clearing both
324 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
325 *
326 * Reference:
327 * "BIOS and Kernel Developer's Guide for AMD NPT
328 * Family 0Fh Processors"
329 * #32559 revision 3.00
330 */
331 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
332 (cpu_id & 0x0fff0000) >= 0x00040000) {
333 uint64_t msr;
334
335 msr = rdmsr(0xc0010055);
336 if (msr & 0x18000000)
337 wrmsr(0xc0010055, msr & ~0x18000000ULL);
338 }
339 }
340
341 intr_restore(eflags);
342 }
343
344 /*
345 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
346 * that it can drive hardclock, statclock, and profclock. This function
347 * returns true if it is able to use the local APIC timer to drive the
348 * clocks and false if it is not able.
349 */
350 int
351 lapic_setup_clock(void)
352 {
353 u_long value;
354
355 /* Can't drive the timer without a local APIC. */
356 if (lapic == NULL)
357 return (0);
358
359 /* Start off with a divisor of 2 (power on reset default). */
360 lapic_timer_divisor = 2;
361
362 /* Try to calibrate the local APIC timer. */
363 do {
364 lapic_timer_set_divisor(lapic_timer_divisor);
365 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
366 DELAY(2000000);
367 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
368 if (value != APIC_TIMER_MAX_COUNT)
369 break;
370 lapic_timer_divisor <<= 1;
371 } while (lapic_timer_divisor <= 128);
372 if (lapic_timer_divisor > 128)
373 panic("lapic: Divisor too big");
374 value /= 2;
375 if (bootverbose)
376 printf("lapic: Divisor %lu, Frequency %lu hz\n",
377 lapic_timer_divisor, value);
378
379 /*
380 * We want to run stathz in the neighborhood of 128hz. We would
381 * like profhz to run as often as possible, so we let it run on
382 * each clock tick. We try to honor the requested 'hz' value as
383 * much as possible.
384 *
385 * If 'hz' is above 1500, then we just let the lapic timer
386 * (and profhz) run at hz. If 'hz' is below 1500 but above
387 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
388 * is below 750 then we let the lapic timer run at 4 * 'hz'.
389 */
390 if (hz >= 1500)
391 lapic_timer_hz = hz;
392 else if (hz >= 750)
393 lapic_timer_hz = hz * 2;
394 else
395 lapic_timer_hz = hz * 4;
396 if (lapic_timer_hz < 128)
397 stathz = lapic_timer_hz;
398 else
399 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
400 profhz = lapic_timer_hz;
401 lapic_timer_period = value / lapic_timer_hz;
402
403 /*
404 * Start up the timer on the BSP. The APs will kick off their
405 * timer during lapic_setup().
406 */
407 lapic_timer_periodic(lapic_timer_period);
408 lapic_timer_enable_intr();
409 return (1);
410 }
411
412 void
413 lapic_disable(void)
414 {
415 uint32_t value;
416
417 /* Software disable the local APIC. */
418 value = lapic->svr;
419 value &= ~APIC_SVR_SWEN;
420 lapic->svr = value;
421 }
422
423 static void
424 lapic_enable(void)
425 {
426 u_int32_t value;
427
428 /* Program the spurious vector to enable the local APIC. */
429 value = lapic->svr;
430 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
431 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
432 lapic->svr = value;
433 }
434
435 /* Reset the local APIC on the BSP during resume. */
436 static void
437 lapic_resume(struct pic *pic)
438 {
439
440 lapic_setup(0);
441 }
442
443 int
444 lapic_id(void)
445 {
446
447 KASSERT(lapic != NULL, ("local APIC is not mapped"));
448 return (lapic->id >> APIC_ID_SHIFT);
449 }
450
451 int
452 lapic_intr_pending(u_int vector)
453 {
454 volatile u_int32_t *irr;
455
456 /*
457 * The IRR registers are an array of 128-bit registers each of
458 * which only describes 32 interrupts in the low 32 bits.. Thus,
459 * we divide the vector by 32 to get the 128-bit index. We then
460 * multiply that index by 4 to get the equivalent index from
461 * treating the IRR as an array of 32-bit registers. Finally, we
462 * modulus the vector by 32 to determine the individual bit to
463 * test.
464 */
465 irr = &lapic->irr0;
466 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
467 }
468
469 void
470 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
471 {
472 struct lapic *la;
473
474 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
475 __func__, apic_id));
476 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
477 __func__, cluster));
478 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
479 ("%s: intra cluster id %u too big", __func__, cluster_id));
480 la = &lapics[apic_id];
481 la->la_cluster = cluster;
482 la->la_cluster_id = cluster_id;
483 }
484
485 int
486 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
487 {
488
489 if (pin > LVT_MAX)
490 return (EINVAL);
491 if (apic_id == APIC_ID_ALL) {
492 lvts[pin].lvt_masked = masked;
493 if (bootverbose)
494 printf("lapic:");
495 } else {
496 KASSERT(lapics[apic_id].la_present,
497 ("%s: missing APIC %u", __func__, apic_id));
498 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
499 lapics[apic_id].la_lvts[pin].lvt_active = 1;
500 if (bootverbose)
501 printf("lapic%u:", apic_id);
502 }
503 if (bootverbose)
504 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
505 return (0);
506 }
507
508 int
509 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
510 {
511 struct lvt *lvt;
512
513 if (pin > LVT_MAX)
514 return (EINVAL);
515 if (apic_id == APIC_ID_ALL) {
516 lvt = &lvts[pin];
517 if (bootverbose)
518 printf("lapic:");
519 } else {
520 KASSERT(lapics[apic_id].la_present,
521 ("%s: missing APIC %u", __func__, apic_id));
522 lvt = &lapics[apic_id].la_lvts[pin];
523 lvt->lvt_active = 1;
524 if (bootverbose)
525 printf("lapic%u:", apic_id);
526 }
527 lvt->lvt_mode = mode;
528 switch (mode) {
529 case APIC_LVT_DM_NMI:
530 case APIC_LVT_DM_SMI:
531 case APIC_LVT_DM_INIT:
532 case APIC_LVT_DM_EXTINT:
533 lvt->lvt_edgetrigger = 1;
534 lvt->lvt_activehi = 1;
535 if (mode == APIC_LVT_DM_EXTINT)
536 lvt->lvt_masked = 1;
537 else
538 lvt->lvt_masked = 0;
539 break;
540 default:
541 panic("Unsupported delivery mode: 0x%x\n", mode);
542 }
543 if (bootverbose) {
544 printf(" Routing ");
545 switch (mode) {
546 case APIC_LVT_DM_NMI:
547 printf("NMI");
548 break;
549 case APIC_LVT_DM_SMI:
550 printf("SMI");
551 break;
552 case APIC_LVT_DM_INIT:
553 printf("INIT");
554 break;
555 case APIC_LVT_DM_EXTINT:
556 printf("ExtINT");
557 break;
558 }
559 printf(" -> LINT%u\n", pin);
560 }
561 return (0);
562 }
563
564 int
565 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
566 {
567
568 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
569 return (EINVAL);
570 if (apic_id == APIC_ID_ALL) {
571 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
572 if (bootverbose)
573 printf("lapic:");
574 } else {
575 KASSERT(lapics[apic_id].la_present,
576 ("%s: missing APIC %u", __func__, apic_id));
577 lapics[apic_id].la_lvts[pin].lvt_active = 1;
578 lapics[apic_id].la_lvts[pin].lvt_activehi =
579 (pol == INTR_POLARITY_HIGH);
580 if (bootverbose)
581 printf("lapic%u:", apic_id);
582 }
583 if (bootverbose)
584 printf(" LINT%u polarity: %s\n", pin,
585 pol == INTR_POLARITY_HIGH ? "high" : "low");
586 return (0);
587 }
588
589 int
590 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
591 {
592
593 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
594 return (EINVAL);
595 if (apic_id == APIC_ID_ALL) {
596 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
597 if (bootverbose)
598 printf("lapic:");
599 } else {
600 KASSERT(lapics[apic_id].la_present,
601 ("%s: missing APIC %u", __func__, apic_id));
602 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
603 (trigger == INTR_TRIGGER_EDGE);
604 lapics[apic_id].la_lvts[pin].lvt_active = 1;
605 if (bootverbose)
606 printf("lapic%u:", apic_id);
607 }
608 if (bootverbose)
609 printf(" LINT%u trigger: %s\n", pin,
610 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
611 return (0);
612 }
613
614 /*
615 * Adjust the TPR of the current CPU so that it blocks all interrupts below
616 * the passed in vector.
617 */
618 void
619 lapic_set_tpr(u_int vector)
620 {
621 #ifdef CHEAP_TPR
622 lapic->tpr = vector;
623 #else
624 u_int32_t tpr;
625
626 tpr = lapic->tpr & ~APIC_TPR_PRIO;
627 tpr |= vector;
628 lapic->tpr = tpr;
629 #endif
630 }
631
632 void
633 lapic_eoi(void)
634 {
635
636 lapic->eoi = 0;
637 }
638
639 void
640 lapic_handle_intr(struct intrframe frame)
641 {
642 struct intsrc *isrc;
643
644 if (frame.if_vec == -1)
645 panic("Couldn't get vector from ISR!");
646 isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec));
647 intr_execute_handlers(isrc, &frame);
648 }
649
650 void
651 lapic_handle_timer(struct clockframe frame)
652 {
653 struct lapic *la;
654
655 #if defined(SMP) && !defined(SCHED_ULE)
656 /*
657 * Don't do any accounting for the disabled HTT cores, since it
658 * will provide misleading numbers for the userland.
659 *
660 * No locking is necessary here, since even if we loose the race
661 * when hlt_cpus_mask changes it is not a big deal, really.
662 *
663 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
664 * and unlike other schedulers it actually schedules threads to
665 * those CPUs.
666 */
667 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
668 return;
669 #endif
670
671 la = &lapics[PCPU_GET(apic_id)];
672 (*la->la_timer_count)++;
673 critical_enter();
674
675 /* Fire hardclock at hz. */
676 la->la_hard_ticks += hz;
677 if (la->la_hard_ticks >= lapic_timer_hz) {
678 la->la_hard_ticks -= lapic_timer_hz;
679 if (PCPU_GET(cpuid) == 0)
680 hardclock(&frame);
681 else
682 hardclock_process(&frame);
683 }
684
685 /* Fire statclock at stathz. */
686 la->la_stat_ticks += stathz;
687 if (la->la_stat_ticks >= lapic_timer_hz) {
688 la->la_stat_ticks -= lapic_timer_hz;
689 statclock(&frame);
690 }
691
692 /* Fire profclock at profhz, but only when needed. */
693 la->la_prof_ticks += profhz;
694 if (la->la_prof_ticks >= lapic_timer_hz) {
695 la->la_prof_ticks -= lapic_timer_hz;
696 if (profprocs != 0)
697 profclock(&frame);
698 }
699 critical_exit();
700 }
701
702 static void
703 lapic_timer_set_divisor(u_int divisor)
704 {
705
706 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
707 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
708 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
709 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
710 }
711
712 static void
713 lapic_timer_oneshot(u_int count)
714 {
715 u_int32_t value;
716
717 value = lapic->lvt_timer;
718 value &= ~APIC_LVTT_TM;
719 value |= APIC_LVTT_TM_ONE_SHOT;
720 lapic->lvt_timer = value;
721 lapic->icr_timer = count;
722 }
723
724 static void
725 lapic_timer_periodic(u_int count)
726 {
727 u_int32_t value;
728
729 value = lapic->lvt_timer;
730 value &= ~APIC_LVTT_TM;
731 value |= APIC_LVTT_TM_PERIODIC;
732 lapic->lvt_timer = value;
733 lapic->icr_timer = count;
734 }
735
736 static void
737 lapic_timer_enable_intr(void)
738 {
739 u_int32_t value;
740
741 value = lapic->lvt_timer;
742 value &= ~APIC_LVT_M;
743 lapic->lvt_timer = value;
744 }
745
746 /* Request a free IDT vector to be used by the specified IRQ. */
747 u_int
748 apic_alloc_vector(u_int irq)
749 {
750 u_int vector;
751
752 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
753
754 /*
755 * Search for a free vector. Currently we just use a very simple
756 * algorithm to find the first free vector.
757 */
758 mtx_lock_spin(&icu_lock);
759 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
760 if (ioint_irqs[vector] != 0)
761 continue;
762 ioint_irqs[vector] = irq;
763 mtx_unlock_spin(&icu_lock);
764 return (vector + APIC_IO_INTS);
765 }
766 mtx_unlock_spin(&icu_lock);
767 panic("Couldn't find an APIC vector for IRQ %u", irq);
768 }
769
770 /*
771 * Request 'count' free contiguous IDT vectors to be used by 'count'
772 * IRQs. 'count' must be a power of two and the vectors will be
773 * aligned on a boundary of 'align'. If the request cannot be
774 * satisfied, 0 is returned.
775 */
776 u_int
777 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
778 {
779 u_int first, run, vector;
780
781 KASSERT(powerof2(count), ("bad count"));
782 KASSERT(powerof2(align), ("bad align"));
783 KASSERT(align >= count, ("align < count"));
784 #ifdef INVARIANTS
785 for (run = 0; run < count; run++)
786 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
787 irqs[run], run));
788 #endif
789
790 /*
791 * Search for 'count' free vectors. As with apic_alloc_vector(),
792 * this just uses a simple first fit algorithm.
793 */
794 run = 0;
795 first = 0;
796 mtx_lock_spin(&icu_lock);
797 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
798
799 /* Vector is in use, end run. */
800 if (ioint_irqs[vector] != 0) {
801 run = 0;
802 first = 0;
803 continue;
804 }
805
806 /* Start a new run if run == 0 and vector is aligned. */
807 if (run == 0) {
808 if ((vector & (align - 1)) != 0)
809 continue;
810 first = vector;
811 }
812 run++;
813
814 /* Keep looping if the run isn't long enough yet. */
815 if (run < count)
816 continue;
817
818 /* Found a run, assign IRQs and return the first vector. */
819 for (vector = 0; vector < count; vector++)
820 ioint_irqs[first + vector] = irqs[vector];
821 mtx_unlock_spin(&icu_lock);
822 return (first + APIC_IO_INTS);
823 }
824 mtx_unlock_spin(&icu_lock);
825 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
826 return (0);
827 }
828
829 void
830 apic_enable_vector(u_int vector)
831 {
832
833 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
834 KASSERT(ioint_handlers[vector / 32] != NULL,
835 ("No ISR handler for vector %u", vector));
836 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
837 GSEL(GCODE_SEL, SEL_KPL));
838 }
839
840 /* Release an APIC vector when it's no longer in use. */
841 void
842 apic_free_vector(u_int vector, u_int irq)
843 {
844 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
845 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
846 ("Vector %u does not map to an IRQ line", vector));
847 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
848 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
849 mtx_lock_spin(&icu_lock);
850 ioint_irqs[vector - APIC_IO_INTS] = 0;
851 mtx_unlock_spin(&icu_lock);
852 }
853
854 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
855 u_int
856 apic_idt_to_irq(u_int vector)
857 {
858
859 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
860 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
861 ("Vector %u does not map to an IRQ line", vector));
862 return (ioint_irqs[vector - APIC_IO_INTS]);
863 }
864
865 #ifdef DDB
866 /*
867 * Dump data about APIC IDT vector mappings.
868 */
869 DB_SHOW_COMMAND(apic, db_show_apic)
870 {
871 struct intsrc *isrc;
872 int quit, i, verbose;
873 u_int irq;
874
875 quit = 0;
876 if (strcmp(modif, "vv") == 0)
877 verbose = 2;
878 else if (strcmp(modif, "v") == 0)
879 verbose = 1;
880 else
881 verbose = 0;
882 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
883 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
884 irq = ioint_irqs[i];
885 if (irq != 0 && irq != IRQ_SYSCALL) {
886 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
887 if (irq == IRQ_TIMER)
888 db_printf("lapic timer\n");
889 else if (irq < NUM_IO_INTS) {
890 isrc = intr_lookup_source(irq);
891 if (isrc == NULL || verbose == 0)
892 db_printf("IRQ %u\n", irq);
893 else
894 db_dump_intr_event(isrc->is_event,
895 verbose == 2);
896 } else
897 db_printf("IRQ %u ???\n", irq);
898 }
899 }
900 }
901
902 static void
903 dump_mask(const char *prefix, uint32_t v, int base)
904 {
905 int i, first;
906
907 first = 1;
908 for (i = 0; i < 32; i++)
909 if (v & (1 << i)) {
910 if (first) {
911 db_printf("%s:", prefix);
912 first = 0;
913 }
914 db_printf(" %02x", base + i);
915 }
916 if (!first)
917 db_printf("\n");
918 }
919
920 /* Show info from the lapic regs for this CPU. */
921 DB_SHOW_COMMAND(lapic, db_show_lapic)
922 {
923 uint32_t v;
924
925 db_printf("lapic ID = %d\n", lapic_id());
926 v = lapic->version;
927 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
928 v & 0xf);
929 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
930 v = lapic->svr;
931 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
932 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
933 db_printf("TPR = %02x\n", lapic->tpr);
934
935 #define dump_field(prefix, index) \
936 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
937 index * 32)
938
939 db_printf("In-service Interrupts:\n");
940 dump_field(isr, 0);
941 dump_field(isr, 1);
942 dump_field(isr, 2);
943 dump_field(isr, 3);
944 dump_field(isr, 4);
945 dump_field(isr, 5);
946 dump_field(isr, 6);
947 dump_field(isr, 7);
948
949 db_printf("TMR Interrupts:\n");
950 dump_field(tmr, 0);
951 dump_field(tmr, 1);
952 dump_field(tmr, 2);
953 dump_field(tmr, 3);
954 dump_field(tmr, 4);
955 dump_field(tmr, 5);
956 dump_field(tmr, 6);
957 dump_field(tmr, 7);
958
959 db_printf("IRR Interrupts:\n");
960 dump_field(irr, 0);
961 dump_field(irr, 1);
962 dump_field(irr, 2);
963 dump_field(irr, 3);
964 dump_field(irr, 4);
965 dump_field(irr, 5);
966 dump_field(irr, 6);
967 dump_field(irr, 7);
968
969 #undef dump_field
970 }
971 #endif
972
973 /*
974 * APIC probing support code. This includes code to manage enumerators.
975 */
976
977 static SLIST_HEAD(, apic_enumerator) enumerators =
978 SLIST_HEAD_INITIALIZER(enumerators);
979 static struct apic_enumerator *best_enum;
980
981 void
982 apic_register_enumerator(struct apic_enumerator *enumerator)
983 {
984 #ifdef INVARIANTS
985 struct apic_enumerator *apic_enum;
986
987 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
988 if (apic_enum == enumerator)
989 panic("%s: Duplicate register of %s", __func__,
990 enumerator->apic_name);
991 }
992 #endif
993 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
994 }
995
996 /*
997 * Probe the APIC enumerators, enumerate CPUs, and initialize the
998 * local APIC.
999 */
1000 static void
1001 apic_init(void *dummy __unused)
1002 {
1003 struct apic_enumerator *enumerator;
1004 uint64_t apic_base;
1005 int retval, best;
1006
1007 /* We only support built in local APICs. */
1008 if (!(cpu_feature & CPUID_APIC))
1009 return;
1010
1011 /* Don't probe if APIC mode is disabled. */
1012 if (resource_disabled("apic", 0))
1013 return;
1014
1015 /* First, probe all the enumerators to find the best match. */
1016 best_enum = NULL;
1017 best = 0;
1018 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1019 retval = enumerator->apic_probe();
1020 if (retval > 0)
1021 continue;
1022 if (best_enum == NULL || best < retval) {
1023 best_enum = enumerator;
1024 best = retval;
1025 }
1026 }
1027 if (best_enum == NULL) {
1028 if (bootverbose)
1029 printf("APIC: Could not find any APICs.\n");
1030 return;
1031 }
1032
1033 if (bootverbose)
1034 printf("APIC: Using the %s enumerator.\n",
1035 best_enum->apic_name);
1036
1037 /*
1038 * To work around an errata, we disable the local APIC on some
1039 * CPUs during early startup. We need to turn the local APIC back
1040 * on on such CPUs now.
1041 */
1042 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
1043 (cpu_id & 0xff0) == 0x610) {
1044 apic_base = rdmsr(MSR_APICBASE);
1045 apic_base |= APICBASE_ENABLED;
1046 wrmsr(MSR_APICBASE, apic_base);
1047 }
1048
1049 /* Second, probe the CPU's in the system. */
1050 retval = best_enum->apic_probe_cpus();
1051 if (retval != 0)
1052 printf("%s: Failed to probe CPUs: returned %d\n",
1053 best_enum->apic_name, retval);
1054
1055 /* Third, initialize the local APIC. */
1056 retval = best_enum->apic_setup_local();
1057 if (retval != 0)
1058 printf("%s: Failed to setup the local APIC: returned %d\n",
1059 best_enum->apic_name, retval);
1060 #ifdef SMP
1061 /* Last, setup the cpu topology now that we have probed CPUs */
1062 mp_topology();
1063 #endif
1064 }
1065 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
1066
1067 /*
1068 * Setup the I/O APICs.
1069 */
1070 static void
1071 apic_setup_io(void *dummy __unused)
1072 {
1073 int retval;
1074
1075 if (best_enum == NULL)
1076 return;
1077 retval = best_enum->apic_setup_io();
1078 if (retval != 0)
1079 printf("%s: Failed to setup I/O APICs: returned %d\n",
1080 best_enum->apic_name, retval);
1081
1082 /*
1083 * Finish setting up the local APIC on the BSP once we know how to
1084 * properly program the LINT pins.
1085 */
1086 lapic_setup(1);
1087 intr_register_pic(&lapic_pic);
1088 if (bootverbose)
1089 lapic_dump("BSP");
1090
1091 /* Enable the MSI "pic". */
1092 msi_init();
1093 }
1094 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
1095
1096 #ifdef SMP
1097 /*
1098 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1099 * private to the sys/i386 code. The public interface for the rest of the
1100 * kernel is defined in mp_machdep.c.
1101 */
1102 int
1103 lapic_ipi_wait(int delay)
1104 {
1105 int x, incr;
1106
1107 /*
1108 * Wait delay loops for IPI to be sent. This is highly bogus
1109 * since this is sensitive to CPU clock speed. If delay is
1110 * -1, we wait forever.
1111 */
1112 if (delay == -1) {
1113 incr = 0;
1114 delay = 1;
1115 } else
1116 incr = 1;
1117 for (x = 0; x < delay; x += incr) {
1118 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1119 return (1);
1120 ia32_pause();
1121 }
1122 return (0);
1123 }
1124
1125 void
1126 lapic_ipi_raw(register_t icrlo, u_int dest)
1127 {
1128 register_t value, eflags;
1129
1130 /* XXX: Need more sanity checking of icrlo? */
1131 KASSERT(lapic != NULL, ("%s called too early", __func__));
1132 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1133 ("%s: invalid dest field", __func__));
1134 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1135 ("%s: reserved bits set in ICR LO register", __func__));
1136
1137 /* Set destination in ICR HI register if it is being used. */
1138 eflags = intr_disable();
1139 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1140 value = lapic->icr_hi;
1141 value &= ~APIC_ID_MASK;
1142 value |= dest << APIC_ID_SHIFT;
1143 lapic->icr_hi = value;
1144 }
1145
1146 /* Program the contents of the IPI and dispatch it. */
1147 value = lapic->icr_lo;
1148 value &= APIC_ICRLO_RESV_MASK;
1149 value |= icrlo;
1150 lapic->icr_lo = value;
1151 intr_restore(eflags);
1152 }
1153
1154 #define BEFORE_SPIN 1000000
1155 #ifdef DETECT_DEADLOCK
1156 #define AFTER_SPIN 1000
1157 #endif
1158
1159 void
1160 lapic_ipi_vectored(u_int vector, int dest)
1161 {
1162 register_t icrlo, destfield;
1163
1164 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1165 ("%s: invalid vector %d", __func__, vector));
1166
1167 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1168 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1169 destfield = 0;
1170 switch (dest) {
1171 case APIC_IPI_DEST_SELF:
1172 icrlo |= APIC_DEST_SELF;
1173 break;
1174 case APIC_IPI_DEST_ALL:
1175 icrlo |= APIC_DEST_ALLISELF;
1176 break;
1177 case APIC_IPI_DEST_OTHERS:
1178 icrlo |= APIC_DEST_ALLESELF;
1179 break;
1180 default:
1181 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1182 ("%s: invalid destination 0x%x", __func__, dest));
1183 destfield = dest;
1184 }
1185
1186 /* Wait for an earlier IPI to finish. */
1187 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1188 if (panicstr != NULL)
1189 return;
1190 else
1191 panic("APIC: Previous IPI is stuck");
1192 }
1193
1194 lapic_ipi_raw(icrlo, destfield);
1195
1196 #ifdef DETECT_DEADLOCK
1197 /* Wait for IPI to be delivered. */
1198 if (!lapic_ipi_wait(AFTER_SPIN)) {
1199 #ifdef needsattention
1200 /*
1201 * XXX FIXME:
1202 *
1203 * The above function waits for the message to actually be
1204 * delivered. It breaks out after an arbitrary timeout
1205 * since the message should eventually be delivered (at
1206 * least in theory) and that if it wasn't we would catch
1207 * the failure with the check above when the next IPI is
1208 * sent.
1209 *
1210 * We could skip this wait entirely, EXCEPT it probably
1211 * protects us from other routines that assume that the
1212 * message was delivered and acted upon when this function
1213 * returns.
1214 */
1215 printf("APIC: IPI might be stuck\n");
1216 #else /* !needsattention */
1217 /* Wait until mesage is sent without a timeout. */
1218 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1219 ia32_pause();
1220 #endif /* needsattention */
1221 }
1222 #endif /* DETECT_DEADLOCK */
1223 }
1224 #endif /* SMP */
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