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sys/i386/i386/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/7.3/sys/i386/i386/local_apic.c 196616 2009-08-28 14:22:01Z jhb $"); 36 37 #include "opt_hwpmc_hooks.h" 38 #include "opt_kdtrace.h" 39 40 #include "opt_ddb.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/pcpu.h> 49 #include <sys/smp.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 54 #include <machine/apicreg.h> 55 #include <machine/cpu.h> 56 #include <machine/cputypes.h> 57 #include <machine/frame.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/apicvar.h> 60 #include <machine/md_var.h> 61 #include <machine/smp.h> 62 #include <machine/specialreg.h> 63 64 #ifdef DDB 65 #include <sys/interrupt.h> 66 #include <ddb/ddb.h> 67 #endif 68 69 #ifdef KDTRACE_HOOKS 70 #include <sys/dtrace_bsd.h> 71 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 72 #endif 73 74 /* Sanity checks on IDT vectors. */ 75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 77 CTASSERT(APIC_LOCAL_INTS == 240); 78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 79 80 /* Magic IRQ values for the timer and syscalls. */ 81 #define IRQ_TIMER (NUM_IO_INTS + 1) 82 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 83 84 /* 85 * Support for local APICs. Local APICs manage interrupts on each 86 * individual processor as opposed to I/O APICs which receive interrupts 87 * from I/O devices and then forward them on to the local APICs. 88 * 89 * Local APICs can also send interrupts to each other thus providing the 90 * mechanism for IPIs. 91 */ 92 93 struct lvt { 94 u_int lvt_edgetrigger:1; 95 u_int lvt_activehi:1; 96 u_int lvt_masked:1; 97 u_int lvt_active:1; 98 u_int lvt_mode:16; 99 u_int lvt_vector:8; 100 }; 101 102 struct lapic { 103 struct lvt la_lvts[LVT_MAX + 1]; 104 u_int la_id:8; 105 u_int la_cluster:4; 106 u_int la_cluster_id:2; 107 u_int la_present:1; 108 u_long *la_timer_count; 109 u_long la_hard_ticks; 110 u_long la_stat_ticks; 111 u_long la_prof_ticks; 112 } static lapics[MAX_APIC_ID + 1]; 113 114 /* XXX: should thermal be an NMI? */ 115 116 /* Global defaults for local APIC LVT entries. */ 117 static struct lvt lvts[LVT_MAX + 1] = { 118 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 122 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 124 }; 125 126 static inthand_t *ioint_handlers[] = { 127 NULL, /* 0 - 31 */ 128 IDTVEC(apic_isr1), /* 32 - 63 */ 129 IDTVEC(apic_isr2), /* 64 - 95 */ 130 IDTVEC(apic_isr3), /* 96 - 127 */ 131 IDTVEC(apic_isr4), /* 128 - 159 */ 132 IDTVEC(apic_isr5), /* 160 - 191 */ 133 IDTVEC(apic_isr6), /* 192 - 223 */ 134 IDTVEC(apic_isr7), /* 224 - 255 */ 135 }; 136 137 /* Include IDT_SYSCALL to make indexing easier. */ 138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 139 140 static u_int32_t lapic_timer_divisors[] = { 141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 143 }; 144 145 extern inthand_t IDTVEC(rsvd); 146 147 volatile lapic_t *lapic; 148 vm_paddr_t lapic_paddr; 149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 150 151 static void lapic_enable(void); 152 static void lapic_resume(struct pic *pic); 153 static void lapic_timer_enable_intr(void); 154 static void lapic_timer_oneshot(u_int count); 155 static void lapic_timer_periodic(u_int count); 156 static void lapic_timer_set_divisor(u_int divisor); 157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 158 159 struct pic lapic_pic = { .pic_resume = lapic_resume }; 160 161 static uint32_t 162 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 163 { 164 struct lvt *lvt; 165 166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 167 if (la->la_lvts[pin].lvt_active) 168 lvt = &la->la_lvts[pin]; 169 else 170 lvt = &lvts[pin]; 171 172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 173 APIC_LVT_VECTOR); 174 if (lvt->lvt_edgetrigger == 0) 175 value |= APIC_LVT_TM; 176 if (lvt->lvt_activehi == 0) 177 value |= APIC_LVT_IIPP_INTALO; 178 if (lvt->lvt_masked) 179 value |= APIC_LVT_M; 180 value |= lvt->lvt_mode; 181 switch (lvt->lvt_mode) { 182 case APIC_LVT_DM_NMI: 183 case APIC_LVT_DM_SMI: 184 case APIC_LVT_DM_INIT: 185 case APIC_LVT_DM_EXTINT: 186 if (!lvt->lvt_edgetrigger) { 187 printf("lapic%u: Forcing LINT%u to edge trigger\n", 188 la->la_id, pin); 189 value |= APIC_LVT_TM; 190 } 191 /* Use a vector of 0. */ 192 break; 193 case APIC_LVT_DM_FIXED: 194 value |= lvt->lvt_vector; 195 break; 196 default: 197 panic("bad APIC LVT delivery mode: %#x\n", value); 198 } 199 return (value); 200 } 201 202 /* 203 * Map the local APIC and setup necessary interrupt vectors. 204 */ 205 void 206 lapic_init(vm_paddr_t addr) 207 { 208 209 /* Map the local APIC and setup the spurious interrupt handler. */ 210 KASSERT(trunc_page(addr) == addr, 211 ("local APIC not aligned on a page boundary")); 212 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 213 lapic_paddr = addr; 214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 215 GSEL(GCODE_SEL, SEL_KPL)); 216 217 /* Perform basic initialization of the BSP's local APIC. */ 218 lapic_enable(); 219 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 220 221 /* Set BSP's per-CPU local APIC ID. */ 222 PCPU_SET(apic_id, lapic_id()); 223 224 /* Local APIC timer interrupt. */ 225 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 226 GSEL(GCODE_SEL, SEL_KPL)); 227 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 228 229 /* XXX: error/thermal interrupts */ 230 } 231 232 /* 233 * Create a local APIC instance. 234 */ 235 void 236 lapic_create(u_int apic_id, int boot_cpu) 237 { 238 int i; 239 240 if (apic_id > MAX_APIC_ID) { 241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 242 if (boot_cpu) 243 panic("Can't ignore BSP"); 244 return; 245 } 246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 247 apic_id)); 248 249 /* 250 * Assume no local LVT overrides and a cluster of 0 and 251 * intra-cluster ID of 0. 252 */ 253 lapics[apic_id].la_present = 1; 254 lapics[apic_id].la_id = apic_id; 255 for (i = 0; i < LVT_MAX; i++) { 256 lapics[apic_id].la_lvts[i] = lvts[i]; 257 lapics[apic_id].la_lvts[i].lvt_active = 0; 258 } 259 260 #ifdef SMP 261 cpu_add(apic_id, boot_cpu); 262 #endif 263 } 264 265 /* 266 * Dump contents of local APIC registers 267 */ 268 void 269 lapic_dump(const char* str) 270 { 271 272 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 273 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 274 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 275 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 276 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 277 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 278 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 279 lapic->lvt_pcint); 280 } 281 282 void 283 lapic_setup(int boot) 284 { 285 struct lapic *la; 286 u_int32_t maxlvt; 287 register_t eflags; 288 char buf[MAXCOMLEN + 1]; 289 290 la = &lapics[lapic_id()]; 291 KASSERT(la->la_present, ("missing APIC structure")); 292 eflags = intr_disable(); 293 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 294 295 /* Initialize the TPR to allow all interrupts. */ 296 lapic_set_tpr(0); 297 298 /* Setup spurious vector and enable the local APIC. */ 299 lapic_enable(); 300 301 /* Program LINT[01] LVT entries. */ 302 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 303 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 304 /* Program the PMC LVT entry if present. */ 305 if (maxlvt >= LVT_PMC) 306 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 307 308 /* Program timer LVT and setup handler. */ 309 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 310 if (boot) { 311 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 312 intrcnt_add(buf, &la->la_timer_count); 313 } 314 315 /* We don't setup the timer during boot on the BSP until later. */ 316 if (!(boot && PCPU_GET(cpuid) == 0)) { 317 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 318 lapic_id())); 319 lapic_timer_set_divisor(lapic_timer_divisor); 320 lapic_timer_periodic(lapic_timer_period); 321 lapic_timer_enable_intr(); 322 } 323 324 /* XXX: Error and thermal LVTs */ 325 326 if (cpu_vendor_id == CPU_VENDOR_AMD) { 327 /* 328 * Detect the presence of C1E capability mostly on latest 329 * dual-cores (or future) k8 family. This feature renders 330 * the local APIC timer dead, so we disable it by reading 331 * the Interrupt Pending Message register and clearing both 332 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 333 * 334 * Reference: 335 * "BIOS and Kernel Developer's Guide for AMD NPT 336 * Family 0Fh Processors" 337 * #32559 revision 3.00 338 */ 339 if ((cpu_id & 0x00000f00) == 0x00000f00 && 340 (cpu_id & 0x0fff0000) >= 0x00040000) { 341 uint64_t msr; 342 343 msr = rdmsr(0xc0010055); 344 if (msr & 0x18000000) 345 wrmsr(0xc0010055, msr & ~0x18000000ULL); 346 } 347 } 348 349 intr_restore(eflags); 350 } 351 352 void 353 lapic_reenable_pmc(void) 354 { 355 #ifdef HWPMC_HOOKS 356 uint32_t value; 357 358 value = lapic->lvt_pcint; 359 value &= ~APIC_LVT_M; 360 lapic->lvt_pcint = value; 361 #endif 362 } 363 364 #ifdef HWPMC_HOOKS 365 static void 366 lapic_update_pmc(void *dummy) 367 { 368 struct lapic *la; 369 370 la = &lapics[lapic_id()]; 371 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 372 } 373 #endif 374 375 int 376 lapic_enable_pmc(void) 377 { 378 #ifdef HWPMC_HOOKS 379 u_int32_t maxlvt; 380 381 /* Fail if the local APIC is not present. */ 382 if (lapic == NULL) 383 return (0); 384 385 /* Fail if the PMC LVT is not present. */ 386 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 387 if (maxlvt < LVT_PMC) 388 return (0); 389 390 lvts[LVT_PMC].lvt_masked = 0; 391 392 #ifdef SMP 393 /* 394 * If hwpmc was loaded at boot time then the APs may not be 395 * started yet. In that case, don't forward the request to 396 * them as they will program the lvt when they start. 397 */ 398 if (smp_started) 399 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 400 else 401 #endif 402 lapic_update_pmc(NULL); 403 return (1); 404 #else 405 return (0); 406 #endif 407 } 408 409 void 410 lapic_disable_pmc(void) 411 { 412 #ifdef HWPMC_HOOKS 413 u_int32_t maxlvt; 414 415 /* Fail if the local APIC is not present. */ 416 if (lapic == NULL) 417 return; 418 419 /* Fail if the PMC LVT is not present. */ 420 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 421 if (maxlvt < LVT_PMC) 422 return; 423 424 lvts[LVT_PMC].lvt_masked = 1; 425 426 #ifdef SMP 427 /* The APs should always be started when hwpmc is unloaded. */ 428 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 429 #endif 430 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 431 #endif 432 } 433 434 /* 435 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 436 * that it can drive hardclock, statclock, and profclock. This function 437 * returns true if it is able to use the local APIC timer to drive the 438 * clocks and false if it is not able. 439 */ 440 int 441 lapic_setup_clock(void) 442 { 443 u_long value; 444 445 /* Can't drive the timer without a local APIC. */ 446 if (lapic == NULL) 447 return (0); 448 449 /* Start off with a divisor of 2 (power on reset default). */ 450 lapic_timer_divisor = 2; 451 452 /* Try to calibrate the local APIC timer. */ 453 do { 454 lapic_timer_set_divisor(lapic_timer_divisor); 455 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 456 DELAY(2000000); 457 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 458 if (value != APIC_TIMER_MAX_COUNT) 459 break; 460 lapic_timer_divisor <<= 1; 461 } while (lapic_timer_divisor <= 128); 462 if (lapic_timer_divisor > 128) 463 panic("lapic: Divisor too big"); 464 value /= 2; 465 if (bootverbose) 466 printf("lapic: Divisor %lu, Frequency %lu hz\n", 467 lapic_timer_divisor, value); 468 469 /* 470 * We want to run stathz in the neighborhood of 128hz. We would 471 * like profhz to run as often as possible, so we let it run on 472 * each clock tick. We try to honor the requested 'hz' value as 473 * much as possible. 474 * 475 * If 'hz' is above 1500, then we just let the lapic timer 476 * (and profhz) run at hz. If 'hz' is below 1500 but above 477 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 478 * is below 750 then we let the lapic timer run at 4 * 'hz'. 479 */ 480 if (hz >= 1500) 481 lapic_timer_hz = hz; 482 else if (hz >= 750) 483 lapic_timer_hz = hz * 2; 484 else 485 lapic_timer_hz = hz * 4; 486 if (lapic_timer_hz < 128) 487 stathz = lapic_timer_hz; 488 else 489 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 490 profhz = lapic_timer_hz; 491 lapic_timer_period = value / lapic_timer_hz; 492 493 /* 494 * Start up the timer on the BSP. The APs will kick off their 495 * timer during lapic_setup(). 496 */ 497 lapic_timer_periodic(lapic_timer_period); 498 lapic_timer_enable_intr(); 499 return (1); 500 } 501 502 void 503 lapic_disable(void) 504 { 505 uint32_t value; 506 507 /* Software disable the local APIC. */ 508 value = lapic->svr; 509 value &= ~APIC_SVR_SWEN; 510 lapic->svr = value; 511 } 512 513 static void 514 lapic_enable(void) 515 { 516 u_int32_t value; 517 518 /* Program the spurious vector to enable the local APIC. */ 519 value = lapic->svr; 520 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 521 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 522 lapic->svr = value; 523 } 524 525 /* Reset the local APIC on the BSP during resume. */ 526 static void 527 lapic_resume(struct pic *pic) 528 { 529 530 lapic_setup(0); 531 } 532 533 int 534 lapic_id(void) 535 { 536 537 KASSERT(lapic != NULL, ("local APIC is not mapped")); 538 return (lapic->id >> APIC_ID_SHIFT); 539 } 540 541 int 542 lapic_intr_pending(u_int vector) 543 { 544 volatile u_int32_t *irr; 545 546 /* 547 * The IRR registers are an array of 128-bit registers each of 548 * which only describes 32 interrupts in the low 32 bits.. Thus, 549 * we divide the vector by 32 to get the 128-bit index. We then 550 * multiply that index by 4 to get the equivalent index from 551 * treating the IRR as an array of 32-bit registers. Finally, we 552 * modulus the vector by 32 to determine the individual bit to 553 * test. 554 */ 555 irr = &lapic->irr0; 556 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 557 } 558 559 void 560 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 561 { 562 struct lapic *la; 563 564 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 565 __func__, apic_id)); 566 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 567 __func__, cluster)); 568 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 569 ("%s: intra cluster id %u too big", __func__, cluster_id)); 570 la = &lapics[apic_id]; 571 la->la_cluster = cluster; 572 la->la_cluster_id = cluster_id; 573 } 574 575 int 576 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 577 { 578 579 if (pin > LVT_MAX) 580 return (EINVAL); 581 if (apic_id == APIC_ID_ALL) { 582 lvts[pin].lvt_masked = masked; 583 if (bootverbose) 584 printf("lapic:"); 585 } else { 586 KASSERT(lapics[apic_id].la_present, 587 ("%s: missing APIC %u", __func__, apic_id)); 588 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 589 lapics[apic_id].la_lvts[pin].lvt_active = 1; 590 if (bootverbose) 591 printf("lapic%u:", apic_id); 592 } 593 if (bootverbose) 594 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 595 return (0); 596 } 597 598 int 599 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 600 { 601 struct lvt *lvt; 602 603 if (pin > LVT_MAX) 604 return (EINVAL); 605 if (apic_id == APIC_ID_ALL) { 606 lvt = &lvts[pin]; 607 if (bootverbose) 608 printf("lapic:"); 609 } else { 610 KASSERT(lapics[apic_id].la_present, 611 ("%s: missing APIC %u", __func__, apic_id)); 612 lvt = &lapics[apic_id].la_lvts[pin]; 613 lvt->lvt_active = 1; 614 if (bootverbose) 615 printf("lapic%u:", apic_id); 616 } 617 lvt->lvt_mode = mode; 618 switch (mode) { 619 case APIC_LVT_DM_NMI: 620 case APIC_LVT_DM_SMI: 621 case APIC_LVT_DM_INIT: 622 case APIC_LVT_DM_EXTINT: 623 lvt->lvt_edgetrigger = 1; 624 lvt->lvt_activehi = 1; 625 if (mode == APIC_LVT_DM_EXTINT) 626 lvt->lvt_masked = 1; 627 else 628 lvt->lvt_masked = 0; 629 break; 630 default: 631 panic("Unsupported delivery mode: 0x%x\n", mode); 632 } 633 if (bootverbose) { 634 printf(" Routing "); 635 switch (mode) { 636 case APIC_LVT_DM_NMI: 637 printf("NMI"); 638 break; 639 case APIC_LVT_DM_SMI: 640 printf("SMI"); 641 break; 642 case APIC_LVT_DM_INIT: 643 printf("INIT"); 644 break; 645 case APIC_LVT_DM_EXTINT: 646 printf("ExtINT"); 647 break; 648 } 649 printf(" -> LINT%u\n", pin); 650 } 651 return (0); 652 } 653 654 int 655 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 656 { 657 658 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 659 return (EINVAL); 660 if (apic_id == APIC_ID_ALL) { 661 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 662 if (bootverbose) 663 printf("lapic:"); 664 } else { 665 KASSERT(lapics[apic_id].la_present, 666 ("%s: missing APIC %u", __func__, apic_id)); 667 lapics[apic_id].la_lvts[pin].lvt_active = 1; 668 lapics[apic_id].la_lvts[pin].lvt_activehi = 669 (pol == INTR_POLARITY_HIGH); 670 if (bootverbose) 671 printf("lapic%u:", apic_id); 672 } 673 if (bootverbose) 674 printf(" LINT%u polarity: %s\n", pin, 675 pol == INTR_POLARITY_HIGH ? "high" : "low"); 676 return (0); 677 } 678 679 int 680 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 681 { 682 683 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 684 return (EINVAL); 685 if (apic_id == APIC_ID_ALL) { 686 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 687 if (bootverbose) 688 printf("lapic:"); 689 } else { 690 KASSERT(lapics[apic_id].la_present, 691 ("%s: missing APIC %u", __func__, apic_id)); 692 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 693 (trigger == INTR_TRIGGER_EDGE); 694 lapics[apic_id].la_lvts[pin].lvt_active = 1; 695 if (bootverbose) 696 printf("lapic%u:", apic_id); 697 } 698 if (bootverbose) 699 printf(" LINT%u trigger: %s\n", pin, 700 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 701 return (0); 702 } 703 704 /* 705 * Adjust the TPR of the current CPU so that it blocks all interrupts below 706 * the passed in vector. 707 */ 708 void 709 lapic_set_tpr(u_int vector) 710 { 711 #ifdef CHEAP_TPR 712 lapic->tpr = vector; 713 #else 714 u_int32_t tpr; 715 716 tpr = lapic->tpr & ~APIC_TPR_PRIO; 717 tpr |= vector; 718 lapic->tpr = tpr; 719 #endif 720 } 721 722 void 723 lapic_eoi(void) 724 { 725 726 lapic->eoi = 0; 727 } 728 729 void 730 lapic_handle_intr(int vector, struct trapframe *frame) 731 { 732 struct intsrc *isrc; 733 734 if (vector == -1) 735 panic("Couldn't get vector from ISR!"); 736 isrc = intr_lookup_source(apic_idt_to_irq(vector)); 737 intr_execute_handlers(isrc, frame); 738 } 739 740 void 741 lapic_handle_timer(struct trapframe *frame) 742 { 743 struct lapic *la; 744 745 /* Send EOI first thing. */ 746 lapic_eoi(); 747 748 #if defined(SMP) && !defined(SCHED_ULE) 749 /* 750 * Don't do any accounting for the disabled HTT cores, since it 751 * will provide misleading numbers for the userland. 752 * 753 * No locking is necessary here, since even if we loose the race 754 * when hlt_cpus_mask changes it is not a big deal, really. 755 * 756 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 757 * and unlike other schedulers it actually schedules threads to 758 * those CPUs. 759 */ 760 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 761 return; 762 #endif 763 764 /* Look up our local APIC structure for the tick counters. */ 765 la = &lapics[PCPU_GET(apic_id)]; 766 (*la->la_timer_count)++; 767 critical_enter(); 768 769 #ifdef KDTRACE_HOOKS 770 /* 771 * If the DTrace hooks are configured and a callback function 772 * has been registered, then call it to process the high speed 773 * timers. 774 */ 775 int cpu = PCPU_GET(cpuid); 776 if (lapic_cyclic_clock_func[cpu] != NULL) 777 (*lapic_cyclic_clock_func[cpu])(frame); 778 #endif 779 780 /* Fire hardclock at hz. */ 781 la->la_hard_ticks += hz; 782 if (la->la_hard_ticks >= lapic_timer_hz) { 783 la->la_hard_ticks -= lapic_timer_hz; 784 if (PCPU_GET(cpuid) == 0) 785 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 786 else 787 hardclock_cpu(TRAPF_USERMODE(frame)); 788 } 789 790 /* Fire statclock at stathz. */ 791 la->la_stat_ticks += stathz; 792 if (la->la_stat_ticks >= lapic_timer_hz) { 793 la->la_stat_ticks -= lapic_timer_hz; 794 statclock(TRAPF_USERMODE(frame)); 795 } 796 797 /* Fire profclock at profhz, but only when needed. */ 798 la->la_prof_ticks += profhz; 799 if (la->la_prof_ticks >= lapic_timer_hz) { 800 la->la_prof_ticks -= lapic_timer_hz; 801 if (profprocs != 0) 802 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 803 } 804 critical_exit(); 805 } 806 807 static void 808 lapic_timer_set_divisor(u_int divisor) 809 { 810 811 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 812 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 813 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 814 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 815 } 816 817 static void 818 lapic_timer_oneshot(u_int count) 819 { 820 u_int32_t value; 821 822 value = lapic->lvt_timer; 823 value &= ~APIC_LVTT_TM; 824 value |= APIC_LVTT_TM_ONE_SHOT; 825 lapic->lvt_timer = value; 826 lapic->icr_timer = count; 827 } 828 829 static void 830 lapic_timer_periodic(u_int count) 831 { 832 u_int32_t value; 833 834 value = lapic->lvt_timer; 835 value &= ~APIC_LVTT_TM; 836 value |= APIC_LVTT_TM_PERIODIC; 837 lapic->lvt_timer = value; 838 lapic->icr_timer = count; 839 } 840 841 static void 842 lapic_timer_enable_intr(void) 843 { 844 u_int32_t value; 845 846 value = lapic->lvt_timer; 847 value &= ~APIC_LVT_M; 848 lapic->lvt_timer = value; 849 } 850 851 /* Request a free IDT vector to be used by the specified IRQ. */ 852 u_int 853 apic_alloc_vector(u_int irq) 854 { 855 u_int vector; 856 857 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 858 859 /* 860 * Search for a free vector. Currently we just use a very simple 861 * algorithm to find the first free vector. 862 */ 863 mtx_lock_spin(&icu_lock); 864 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 865 if (ioint_irqs[vector] != 0) 866 continue; 867 ioint_irqs[vector] = irq; 868 mtx_unlock_spin(&icu_lock); 869 return (vector + APIC_IO_INTS); 870 } 871 mtx_unlock_spin(&icu_lock); 872 panic("Couldn't find an APIC vector for IRQ %u", irq); 873 } 874 875 /* 876 * Request 'count' free contiguous IDT vectors to be used by 'count' 877 * IRQs. 'count' must be a power of two and the vectors will be 878 * aligned on a boundary of 'align'. If the request cannot be 879 * satisfied, 0 is returned. 880 */ 881 u_int 882 apic_alloc_vectors(u_int *irqs, u_int count, u_int align) 883 { 884 u_int first, run, vector; 885 886 KASSERT(powerof2(count), ("bad count")); 887 KASSERT(powerof2(align), ("bad align")); 888 KASSERT(align >= count, ("align < count")); 889 #ifdef INVARIANTS 890 for (run = 0; run < count; run++) 891 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 892 irqs[run], run)); 893 #endif 894 895 /* 896 * Search for 'count' free vectors. As with apic_alloc_vector(), 897 * this just uses a simple first fit algorithm. 898 */ 899 run = 0; 900 first = 0; 901 mtx_lock_spin(&icu_lock); 902 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 903 904 /* Vector is in use, end run. */ 905 if (ioint_irqs[vector] != 0) { 906 run = 0; 907 first = 0; 908 continue; 909 } 910 911 /* Start a new run if run == 0 and vector is aligned. */ 912 if (run == 0) { 913 if ((vector & (align - 1)) != 0) 914 continue; 915 first = vector; 916 } 917 run++; 918 919 /* Keep looping if the run isn't long enough yet. */ 920 if (run < count) 921 continue; 922 923 /* Found a run, assign IRQs and return the first vector. */ 924 for (vector = 0; vector < count; vector++) 925 ioint_irqs[first + vector] = irqs[vector]; 926 mtx_unlock_spin(&icu_lock); 927 return (first + APIC_IO_INTS); 928 } 929 mtx_unlock_spin(&icu_lock); 930 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 931 return (0); 932 } 933 934 void 935 apic_enable_vector(u_int vector) 936 { 937 938 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 939 KASSERT(ioint_handlers[vector / 32] != NULL, 940 ("No ISR handler for vector %u", vector)); 941 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 942 GSEL(GCODE_SEL, SEL_KPL)); 943 } 944 945 void 946 apic_disable_vector(u_int vector) 947 { 948 949 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 950 KASSERT(ioint_handlers[vector / 32] != NULL, 951 ("No ISR handler for vector %u", vector)); 952 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 953 GSEL(GCODE_SEL, SEL_KPL)); 954 } 955 956 /* Release an APIC vector when it's no longer in use. */ 957 void 958 apic_free_vector(u_int vector, u_int irq) 959 { 960 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 961 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 962 ("Vector %u does not map to an IRQ line", vector)); 963 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 964 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 965 mtx_lock_spin(&icu_lock); 966 ioint_irqs[vector - APIC_IO_INTS] = 0; 967 mtx_unlock_spin(&icu_lock); 968 } 969 970 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 971 u_int 972 apic_idt_to_irq(u_int vector) 973 { 974 975 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 976 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 977 ("Vector %u does not map to an IRQ line", vector)); 978 return (ioint_irqs[vector - APIC_IO_INTS]); 979 } 980 981 #ifdef DDB 982 /* 983 * Dump data about APIC IDT vector mappings. 984 */ 985 DB_SHOW_COMMAND(apic, db_show_apic) 986 { 987 struct intsrc *isrc; 988 int i, verbose; 989 u_int irq; 990 991 if (strcmp(modif, "vv") == 0) 992 verbose = 2; 993 else if (strcmp(modif, "v") == 0) 994 verbose = 1; 995 else 996 verbose = 0; 997 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 998 irq = ioint_irqs[i]; 999 if (irq != 0 && irq != IRQ_SYSCALL) { 1000 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1001 if (irq == IRQ_TIMER) 1002 db_printf("lapic timer\n"); 1003 else if (irq < NUM_IO_INTS) { 1004 isrc = intr_lookup_source(irq); 1005 if (isrc == NULL || verbose == 0) 1006 db_printf("IRQ %u\n", irq); 1007 else 1008 db_dump_intr_event(isrc->is_event, 1009 verbose == 2); 1010 } else 1011 db_printf("IRQ %u ???\n", irq); 1012 } 1013 } 1014 } 1015 1016 static void 1017 dump_mask(const char *prefix, uint32_t v, int base) 1018 { 1019 int i, first; 1020 1021 first = 1; 1022 for (i = 0; i < 32; i++) 1023 if (v & (1 << i)) { 1024 if (first) { 1025 db_printf("%s:", prefix); 1026 first = 0; 1027 } 1028 db_printf(" %02x", base + i); 1029 } 1030 if (!first) 1031 db_printf("\n"); 1032 } 1033 1034 /* Show info from the lapic regs for this CPU. */ 1035 DB_SHOW_COMMAND(lapic, db_show_lapic) 1036 { 1037 uint32_t v; 1038 1039 db_printf("lapic ID = %d\n", lapic_id()); 1040 v = lapic->version; 1041 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1042 v & 0xf); 1043 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1044 v = lapic->svr; 1045 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1046 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1047 db_printf("TPR = %02x\n", lapic->tpr); 1048 1049 #define dump_field(prefix, index) \ 1050 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1051 index * 32) 1052 1053 db_printf("In-service Interrupts:\n"); 1054 dump_field(isr, 0); 1055 dump_field(isr, 1); 1056 dump_field(isr, 2); 1057 dump_field(isr, 3); 1058 dump_field(isr, 4); 1059 dump_field(isr, 5); 1060 dump_field(isr, 6); 1061 dump_field(isr, 7); 1062 1063 db_printf("TMR Interrupts:\n"); 1064 dump_field(tmr, 0); 1065 dump_field(tmr, 1); 1066 dump_field(tmr, 2); 1067 dump_field(tmr, 3); 1068 dump_field(tmr, 4); 1069 dump_field(tmr, 5); 1070 dump_field(tmr, 6); 1071 dump_field(tmr, 7); 1072 1073 db_printf("IRR Interrupts:\n"); 1074 dump_field(irr, 0); 1075 dump_field(irr, 1); 1076 dump_field(irr, 2); 1077 dump_field(irr, 3); 1078 dump_field(irr, 4); 1079 dump_field(irr, 5); 1080 dump_field(irr, 6); 1081 dump_field(irr, 7); 1082 1083 #undef dump_field 1084 } 1085 #endif 1086 1087 /* 1088 * APIC probing support code. This includes code to manage enumerators. 1089 */ 1090 1091 static SLIST_HEAD(, apic_enumerator) enumerators = 1092 SLIST_HEAD_INITIALIZER(enumerators); 1093 static struct apic_enumerator *best_enum; 1094 1095 void 1096 apic_register_enumerator(struct apic_enumerator *enumerator) 1097 { 1098 #ifdef INVARIANTS 1099 struct apic_enumerator *apic_enum; 1100 1101 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1102 if (apic_enum == enumerator) 1103 panic("%s: Duplicate register of %s", __func__, 1104 enumerator->apic_name); 1105 } 1106 #endif 1107 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1108 } 1109 1110 /* 1111 * Probe the APIC enumerators, enumerate CPUs, and initialize the 1112 * local APIC. 1113 */ 1114 static void 1115 apic_init(void *dummy __unused) 1116 { 1117 struct apic_enumerator *enumerator; 1118 uint64_t apic_base; 1119 int retval, best; 1120 1121 /* We only support built in local APICs. */ 1122 if (!(cpu_feature & CPUID_APIC)) 1123 return; 1124 1125 /* Don't probe if APIC mode is disabled. */ 1126 if (resource_disabled("apic", 0)) 1127 return; 1128 1129 /* First, probe all the enumerators to find the best match. */ 1130 best_enum = NULL; 1131 best = 0; 1132 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1133 retval = enumerator->apic_probe(); 1134 if (retval > 0) 1135 continue; 1136 if (best_enum == NULL || best < retval) { 1137 best_enum = enumerator; 1138 best = retval; 1139 } 1140 } 1141 if (best_enum == NULL) { 1142 if (bootverbose) 1143 printf("APIC: Could not find any APICs.\n"); 1144 return; 1145 } 1146 1147 if (bootverbose) 1148 printf("APIC: Using the %s enumerator.\n", 1149 best_enum->apic_name); 1150 1151 /* 1152 * To work around an errata, we disable the local APIC on some 1153 * CPUs during early startup. We need to turn the local APIC back 1154 * on on such CPUs now. 1155 */ 1156 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1157 (cpu_id & 0xff0) == 0x610) { 1158 apic_base = rdmsr(MSR_APICBASE); 1159 apic_base |= APICBASE_ENABLED; 1160 wrmsr(MSR_APICBASE, apic_base); 1161 } 1162 1163 /* Second, probe the CPU's in the system. */ 1164 retval = best_enum->apic_probe_cpus(); 1165 if (retval != 0) 1166 printf("%s: Failed to probe CPUs: returned %d\n", 1167 best_enum->apic_name, retval); 1168 1169 /* Third, initialize the local APIC. */ 1170 retval = best_enum->apic_setup_local(); 1171 if (retval != 0) 1172 printf("%s: Failed to setup the local APIC: returned %d\n", 1173 best_enum->apic_name, retval); 1174 } 1175 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1176 1177 /* 1178 * Setup the I/O APICs. 1179 */ 1180 static void 1181 apic_setup_io(void *dummy __unused) 1182 { 1183 int retval; 1184 1185 if (best_enum == NULL) 1186 return; 1187 retval = best_enum->apic_setup_io(); 1188 if (retval != 0) 1189 printf("%s: Failed to setup I/O APICs: returned %d\n", 1190 best_enum->apic_name, retval); 1191 1192 /* 1193 * Finish setting up the local APIC on the BSP once we know how to 1194 * properly program the LINT pins. 1195 */ 1196 lapic_setup(1); 1197 intr_register_pic(&lapic_pic); 1198 if (bootverbose) 1199 lapic_dump("BSP"); 1200 1201 /* Enable the MSI "pic". */ 1202 msi_init(); 1203 } 1204 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1205 1206 #ifdef SMP 1207 /* 1208 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1209 * private to the sys/i386 code. The public interface for the rest of the 1210 * kernel is defined in mp_machdep.c. 1211 */ 1212 int 1213 lapic_ipi_wait(int delay) 1214 { 1215 int x, incr; 1216 1217 /* 1218 * Wait delay loops for IPI to be sent. This is highly bogus 1219 * since this is sensitive to CPU clock speed. If delay is 1220 * -1, we wait forever. 1221 */ 1222 if (delay == -1) { 1223 incr = 0; 1224 delay = 1; 1225 } else 1226 incr = 1; 1227 for (x = 0; x < delay; x += incr) { 1228 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1229 return (1); 1230 ia32_pause(); 1231 } 1232 return (0); 1233 } 1234 1235 void 1236 lapic_ipi_raw(register_t icrlo, u_int dest) 1237 { 1238 register_t value, eflags; 1239 1240 /* XXX: Need more sanity checking of icrlo? */ 1241 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1242 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1243 ("%s: invalid dest field", __func__)); 1244 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1245 ("%s: reserved bits set in ICR LO register", __func__)); 1246 1247 /* Set destination in ICR HI register if it is being used. */ 1248 eflags = intr_disable(); 1249 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1250 value = lapic->icr_hi; 1251 value &= ~APIC_ID_MASK; 1252 value |= dest << APIC_ID_SHIFT; 1253 lapic->icr_hi = value; 1254 } 1255 1256 /* Program the contents of the IPI and dispatch it. */ 1257 value = lapic->icr_lo; 1258 value &= APIC_ICRLO_RESV_MASK; 1259 value |= icrlo; 1260 lapic->icr_lo = value; 1261 intr_restore(eflags); 1262 } 1263 1264 #define BEFORE_SPIN 1000000 1265 #ifdef DETECT_DEADLOCK 1266 #define AFTER_SPIN 1000 1267 #endif 1268 1269 void 1270 lapic_ipi_vectored(u_int vector, int dest) 1271 { 1272 register_t icrlo, destfield; 1273 1274 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1275 ("%s: invalid vector %d", __func__, vector)); 1276 1277 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1278 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1279 destfield = 0; 1280 switch (dest) { 1281 case APIC_IPI_DEST_SELF: 1282 icrlo |= APIC_DEST_SELF; 1283 break; 1284 case APIC_IPI_DEST_ALL: 1285 icrlo |= APIC_DEST_ALLISELF; 1286 break; 1287 case APIC_IPI_DEST_OTHERS: 1288 icrlo |= APIC_DEST_ALLESELF; 1289 break; 1290 default: 1291 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1292 ("%s: invalid destination 0x%x", __func__, dest)); 1293 destfield = dest; 1294 } 1295 1296 /* Wait for an earlier IPI to finish. */ 1297 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1298 if (panicstr != NULL) 1299 return; 1300 else 1301 panic("APIC: Previous IPI is stuck"); 1302 } 1303 1304 lapic_ipi_raw(icrlo, destfield); 1305 1306 #ifdef DETECT_DEADLOCK 1307 /* Wait for IPI to be delivered. */ 1308 if (!lapic_ipi_wait(AFTER_SPIN)) { 1309 #ifdef needsattention 1310 /* 1311 * XXX FIXME: 1312 * 1313 * The above function waits for the message to actually be 1314 * delivered. It breaks out after an arbitrary timeout 1315 * since the message should eventually be delivered (at 1316 * least in theory) and that if it wasn't we would catch 1317 * the failure with the check above when the next IPI is 1318 * sent. 1319 * 1320 * We could skip this wait entirely, EXCEPT it probably 1321 * protects us from other routines that assume that the 1322 * message was delivered and acted upon when this function 1323 * returns. 1324 */ 1325 printf("APIC: IPI might be stuck\n"); 1326 #else /* !needsattention */ 1327 /* Wait until mesage is sent without a timeout. */ 1328 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1329 ia32_pause(); 1330 #endif /* needsattention */ 1331 } 1332 #endif /* DETECT_DEADLOCK */ 1333 } 1334 #endif /* SMP */
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