1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/7.4/sys/i386/i386/local_apic.c 215528 2010-11-19 16:26:51Z jhb $");
36
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
39
40 #include "opt_ddb.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/pcpu.h>
49 #include <sys/smp.h>
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53
54 #include <machine/apicreg.h>
55 #include <machine/cpu.h>
56 #include <machine/cputypes.h>
57 #include <machine/frame.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/apicvar.h>
60 #include <machine/mca.h>
61 #include <machine/md_var.h>
62 #include <machine/smp.h>
63 #include <machine/specialreg.h>
64
65 #ifdef DDB
66 #include <sys/interrupt.h>
67 #include <ddb/ddb.h>
68 #endif
69
70 #ifdef KDTRACE_HOOKS
71 #include <sys/dtrace_bsd.h>
72 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
73 #endif
74
75 /* Sanity checks on IDT vectors. */
76 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
77 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
78 CTASSERT(APIC_LOCAL_INTS == 240);
79 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
80
81 /* Magic IRQ values for the timer and syscalls. */
82 #define IRQ_TIMER (NUM_IO_INTS + 1)
83 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
84
85 /*
86 * Support for local APICs. Local APICs manage interrupts on each
87 * individual processor as opposed to I/O APICs which receive interrupts
88 * from I/O devices and then forward them on to the local APICs.
89 *
90 * Local APICs can also send interrupts to each other thus providing the
91 * mechanism for IPIs.
92 */
93
94 struct lvt {
95 u_int lvt_edgetrigger:1;
96 u_int lvt_activehi:1;
97 u_int lvt_masked:1;
98 u_int lvt_active:1;
99 u_int lvt_mode:16;
100 u_int lvt_vector:8;
101 };
102
103 struct lapic {
104 struct lvt la_lvts[LVT_MAX + 1];
105 u_int la_id:8;
106 u_int la_cluster:4;
107 u_int la_cluster_id:2;
108 u_int la_present:1;
109 u_long *la_timer_count;
110 u_long la_hard_ticks;
111 u_long la_stat_ticks;
112 u_long la_prof_ticks;
113 } static lapics[MAX_APIC_ID + 1];
114
115 /* Global defaults for local APIC LVT entries. */
116 static struct lvt lvts[LVT_MAX + 1] = {
117 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
118 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
119 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
120 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
121 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
122 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
124 };
125
126 static inthand_t *ioint_handlers[] = {
127 NULL, /* 0 - 31 */
128 IDTVEC(apic_isr1), /* 32 - 63 */
129 IDTVEC(apic_isr2), /* 64 - 95 */
130 IDTVEC(apic_isr3), /* 96 - 127 */
131 IDTVEC(apic_isr4), /* 128 - 159 */
132 IDTVEC(apic_isr5), /* 160 - 191 */
133 IDTVEC(apic_isr6), /* 192 - 223 */
134 IDTVEC(apic_isr7), /* 224 - 255 */
135 };
136
137 /* Include IDT_SYSCALL to make indexing easier. */
138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
139
140 static u_int32_t lapic_timer_divisors[] = {
141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
143 };
144
145 extern inthand_t IDTVEC(rsvd);
146
147 volatile lapic_t *lapic;
148 vm_paddr_t lapic_paddr;
149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
150
151 static void lapic_enable(void);
152 static void lapic_resume(struct pic *pic);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
158
159 struct pic lapic_pic = { .pic_resume = lapic_resume };
160
161 static uint32_t
162 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
163 {
164 struct lvt *lvt;
165
166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
167 if (la->la_lvts[pin].lvt_active)
168 lvt = &la->la_lvts[pin];
169 else
170 lvt = &lvts[pin];
171
172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
173 APIC_LVT_VECTOR);
174 if (lvt->lvt_edgetrigger == 0)
175 value |= APIC_LVT_TM;
176 if (lvt->lvt_activehi == 0)
177 value |= APIC_LVT_IIPP_INTALO;
178 if (lvt->lvt_masked)
179 value |= APIC_LVT_M;
180 value |= lvt->lvt_mode;
181 switch (lvt->lvt_mode) {
182 case APIC_LVT_DM_NMI:
183 case APIC_LVT_DM_SMI:
184 case APIC_LVT_DM_INIT:
185 case APIC_LVT_DM_EXTINT:
186 if (!lvt->lvt_edgetrigger) {
187 printf("lapic%u: Forcing LINT%u to edge trigger\n",
188 la->la_id, pin);
189 value |= APIC_LVT_TM;
190 }
191 /* Use a vector of 0. */
192 break;
193 case APIC_LVT_DM_FIXED:
194 value |= lvt->lvt_vector;
195 break;
196 default:
197 panic("bad APIC LVT delivery mode: %#x\n", value);
198 }
199 return (value);
200 }
201
202 /*
203 * Map the local APIC and setup necessary interrupt vectors.
204 */
205 void
206 lapic_init(vm_paddr_t addr)
207 {
208
209 /* Map the local APIC and setup the spurious interrupt handler. */
210 KASSERT(trunc_page(addr) == addr,
211 ("local APIC not aligned on a page boundary"));
212 lapic = pmap_mapdev(addr, sizeof(lapic_t));
213 lapic_paddr = addr;
214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
215 GSEL(GCODE_SEL, SEL_KPL));
216
217 /* Perform basic initialization of the BSP's local APIC. */
218 lapic_enable();
219 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
220
221 /* Set BSP's per-CPU local APIC ID. */
222 PCPU_SET(apic_id, lapic_id());
223
224 /* Local APIC timer interrupt. */
225 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
226 GSEL(GCODE_SEL, SEL_KPL));
227 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
228
229 /* Local APIC error interrupt. */
230 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_SYS386IGT, SEL_KPL,
231 GSEL(GCODE_SEL, SEL_KPL));
232
233 /* XXX: Thermal interrupt */
234
235 /* Local APIC CMCI. */
236 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_SYS386TGT, SEL_KPL,
237 GSEL(GCODE_SEL, SEL_KPL));
238 }
239
240 /*
241 * Create a local APIC instance.
242 */
243 void
244 lapic_create(u_int apic_id, int boot_cpu)
245 {
246 int i;
247
248 if (apic_id > MAX_APIC_ID) {
249 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
250 if (boot_cpu)
251 panic("Can't ignore BSP");
252 return;
253 }
254 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
255 apic_id));
256
257 /*
258 * Assume no local LVT overrides and a cluster of 0 and
259 * intra-cluster ID of 0.
260 */
261 lapics[apic_id].la_present = 1;
262 lapics[apic_id].la_id = apic_id;
263 for (i = 0; i <= LVT_MAX; i++) {
264 lapics[apic_id].la_lvts[i] = lvts[i];
265 lapics[apic_id].la_lvts[i].lvt_active = 0;
266 }
267
268 #ifdef SMP
269 cpu_add(apic_id, boot_cpu);
270 #endif
271 }
272
273 /*
274 * Dump contents of local APIC registers
275 */
276 void
277 lapic_dump(const char* str)
278 {
279 uint32_t maxlvt;
280
281 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
282 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
283 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
284 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
285 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
286 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
287 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
288 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error);
289 if (maxlvt >= LVT_PMC)
290 printf(" pmc: 0x%08x", lapic->lvt_pcint);
291 printf("\n");
292 if (maxlvt >= LVT_CMCI)
293 printf(" cmci: 0x%08x\n", lapic->lvt_cmci);
294 }
295
296 void
297 lapic_setup(int boot)
298 {
299 struct lapic *la;
300 u_int32_t maxlvt;
301 register_t eflags;
302 char buf[MAXCOMLEN + 1];
303
304 la = &lapics[lapic_id()];
305 KASSERT(la->la_present, ("missing APIC structure"));
306 eflags = intr_disable();
307 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
308
309 /* Initialize the TPR to allow all interrupts. */
310 lapic_set_tpr(0);
311
312 /* Setup spurious vector and enable the local APIC. */
313 lapic_enable();
314
315 /* Program LINT[01] LVT entries. */
316 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
317 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
318
319 /* Program the PMC LVT entry if present. */
320 if (maxlvt >= LVT_PMC)
321 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
322
323 /* Program timer LVT and setup handler. */
324 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
325 if (boot) {
326 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
327 intrcnt_add(buf, &la->la_timer_count);
328 }
329
330 /* We don't setup the timer during boot on the BSP until later. */
331 if (!(boot && PCPU_GET(cpuid) == 0)) {
332 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
333 lapic_id()));
334 lapic_timer_set_divisor(lapic_timer_divisor);
335 lapic_timer_periodic(lapic_timer_period);
336 lapic_timer_enable_intr();
337 }
338
339 /* Program error LVT and clear any existing errors. */
340 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error);
341 lapic->esr = 0;
342
343 /* XXX: Thermal LVT */
344
345 if (cpu_vendor_id == CPU_VENDOR_AMD) {
346 /*
347 * Detect the presence of C1E capability mostly on latest
348 * dual-cores (or future) k8 family. This feature renders
349 * the local APIC timer dead, so we disable it by reading
350 * the Interrupt Pending Message register and clearing both
351 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
352 *
353 * Reference:
354 * "BIOS and Kernel Developer's Guide for AMD NPT
355 * Family 0Fh Processors"
356 * #32559 revision 3.00
357 */
358 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
359 (cpu_id & 0x0fff0000) >= 0x00040000) {
360 uint64_t msr;
361
362 msr = rdmsr(0xc0010055);
363 if (msr & 0x18000000)
364 wrmsr(0xc0010055, msr & ~0x18000000ULL);
365 }
366 }
367
368 /* Program the CMCI LVT entry if present. */
369 if (maxlvt >= LVT_CMCI)
370 lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
371
372 intr_restore(eflags);
373 }
374
375 void
376 lapic_reenable_pmc(void)
377 {
378 #ifdef HWPMC_HOOKS
379 uint32_t value;
380
381 value = lapic->lvt_pcint;
382 value &= ~APIC_LVT_M;
383 lapic->lvt_pcint = value;
384 #endif
385 }
386
387 #ifdef HWPMC_HOOKS
388 static void
389 lapic_update_pmc(void *dummy)
390 {
391 struct lapic *la;
392
393 la = &lapics[lapic_id()];
394 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
395 }
396 #endif
397
398 int
399 lapic_enable_pmc(void)
400 {
401 #ifdef HWPMC_HOOKS
402 u_int32_t maxlvt;
403
404 /* Fail if the local APIC is not present. */
405 if (lapic == NULL)
406 return (0);
407
408 /* Fail if the PMC LVT is not present. */
409 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
410 if (maxlvt < LVT_PMC)
411 return (0);
412
413 lvts[LVT_PMC].lvt_masked = 0;
414
415 #ifdef SMP
416 /*
417 * If hwpmc was loaded at boot time then the APs may not be
418 * started yet. In that case, don't forward the request to
419 * them as they will program the lvt when they start.
420 */
421 if (smp_started)
422 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
423 else
424 #endif
425 lapic_update_pmc(NULL);
426 return (1);
427 #else
428 return (0);
429 #endif
430 }
431
432 void
433 lapic_disable_pmc(void)
434 {
435 #ifdef HWPMC_HOOKS
436 u_int32_t maxlvt;
437
438 /* Fail if the local APIC is not present. */
439 if (lapic == NULL)
440 return;
441
442 /* Fail if the PMC LVT is not present. */
443 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
444 if (maxlvt < LVT_PMC)
445 return;
446
447 lvts[LVT_PMC].lvt_masked = 1;
448
449 #ifdef SMP
450 /* The APs should always be started when hwpmc is unloaded. */
451 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
452 #endif
453 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
454 #endif
455 }
456
457 /*
458 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
459 * that it can drive hardclock, statclock, and profclock. This function
460 * returns true if it is able to use the local APIC timer to drive the
461 * clocks and false if it is not able.
462 */
463 int
464 lapic_setup_clock(void)
465 {
466 u_long value;
467
468 /* Can't drive the timer without a local APIC. */
469 if (lapic == NULL)
470 return (0);
471
472 /* Start off with a divisor of 2 (power on reset default). */
473 lapic_timer_divisor = 2;
474
475 /* Try to calibrate the local APIC timer. */
476 do {
477 lapic_timer_set_divisor(lapic_timer_divisor);
478 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
479 DELAY(2000000);
480 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
481 if (value != APIC_TIMER_MAX_COUNT)
482 break;
483 lapic_timer_divisor <<= 1;
484 } while (lapic_timer_divisor <= 128);
485 if (lapic_timer_divisor > 128)
486 panic("lapic: Divisor too big");
487 value /= 2;
488 if (bootverbose)
489 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
490 lapic_timer_divisor, value);
491
492 /*
493 * We want to run stathz in the neighborhood of 128hz. We would
494 * like profhz to run as often as possible, so we let it run on
495 * each clock tick. We try to honor the requested 'hz' value as
496 * much as possible.
497 *
498 * If 'hz' is above 1500, then we just let the lapic timer
499 * (and profhz) run at hz. If 'hz' is below 1500 but above
500 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
501 * is below 750 then we let the lapic timer run at 4 * 'hz'.
502 */
503 if (hz >= 1500)
504 lapic_timer_hz = hz;
505 else if (hz >= 750)
506 lapic_timer_hz = hz * 2;
507 else
508 lapic_timer_hz = hz * 4;
509 if (lapic_timer_hz < 128)
510 stathz = lapic_timer_hz;
511 else
512 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
513 profhz = lapic_timer_hz;
514 lapic_timer_period = value / lapic_timer_hz;
515
516 /*
517 * Start up the timer on the BSP. The APs will kick off their
518 * timer during lapic_setup().
519 */
520 lapic_timer_periodic(lapic_timer_period);
521 lapic_timer_enable_intr();
522 return (1);
523 }
524
525 void
526 lapic_disable(void)
527 {
528 uint32_t value;
529
530 /* Software disable the local APIC. */
531 value = lapic->svr;
532 value &= ~APIC_SVR_SWEN;
533 lapic->svr = value;
534 }
535
536 static void
537 lapic_enable(void)
538 {
539 u_int32_t value;
540
541 /* Program the spurious vector to enable the local APIC. */
542 value = lapic->svr;
543 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
544 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
545 lapic->svr = value;
546 }
547
548 /* Reset the local APIC on the BSP during resume. */
549 static void
550 lapic_resume(struct pic *pic)
551 {
552
553 lapic_setup(0);
554 }
555
556 int
557 lapic_id(void)
558 {
559
560 KASSERT(lapic != NULL, ("local APIC is not mapped"));
561 return (lapic->id >> APIC_ID_SHIFT);
562 }
563
564 int
565 lapic_intr_pending(u_int vector)
566 {
567 volatile u_int32_t *irr;
568
569 /*
570 * The IRR registers are an array of 128-bit registers each of
571 * which only describes 32 interrupts in the low 32 bits.. Thus,
572 * we divide the vector by 32 to get the 128-bit index. We then
573 * multiply that index by 4 to get the equivalent index from
574 * treating the IRR as an array of 32-bit registers. Finally, we
575 * modulus the vector by 32 to determine the individual bit to
576 * test.
577 */
578 irr = &lapic->irr0;
579 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
580 }
581
582 void
583 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
584 {
585 struct lapic *la;
586
587 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
588 __func__, apic_id));
589 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
590 __func__, cluster));
591 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
592 ("%s: intra cluster id %u too big", __func__, cluster_id));
593 la = &lapics[apic_id];
594 la->la_cluster = cluster;
595 la->la_cluster_id = cluster_id;
596 }
597
598 int
599 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
600 {
601
602 if (pin > LVT_MAX)
603 return (EINVAL);
604 if (apic_id == APIC_ID_ALL) {
605 lvts[pin].lvt_masked = masked;
606 if (bootverbose)
607 printf("lapic:");
608 } else {
609 KASSERT(lapics[apic_id].la_present,
610 ("%s: missing APIC %u", __func__, apic_id));
611 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
612 lapics[apic_id].la_lvts[pin].lvt_active = 1;
613 if (bootverbose)
614 printf("lapic%u:", apic_id);
615 }
616 if (bootverbose)
617 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
618 return (0);
619 }
620
621 int
622 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
623 {
624 struct lvt *lvt;
625
626 if (pin > LVT_MAX)
627 return (EINVAL);
628 if (apic_id == APIC_ID_ALL) {
629 lvt = &lvts[pin];
630 if (bootverbose)
631 printf("lapic:");
632 } else {
633 KASSERT(lapics[apic_id].la_present,
634 ("%s: missing APIC %u", __func__, apic_id));
635 lvt = &lapics[apic_id].la_lvts[pin];
636 lvt->lvt_active = 1;
637 if (bootverbose)
638 printf("lapic%u:", apic_id);
639 }
640 lvt->lvt_mode = mode;
641 switch (mode) {
642 case APIC_LVT_DM_NMI:
643 case APIC_LVT_DM_SMI:
644 case APIC_LVT_DM_INIT:
645 case APIC_LVT_DM_EXTINT:
646 lvt->lvt_edgetrigger = 1;
647 lvt->lvt_activehi = 1;
648 if (mode == APIC_LVT_DM_EXTINT)
649 lvt->lvt_masked = 1;
650 else
651 lvt->lvt_masked = 0;
652 break;
653 default:
654 panic("Unsupported delivery mode: 0x%x\n", mode);
655 }
656 if (bootverbose) {
657 printf(" Routing ");
658 switch (mode) {
659 case APIC_LVT_DM_NMI:
660 printf("NMI");
661 break;
662 case APIC_LVT_DM_SMI:
663 printf("SMI");
664 break;
665 case APIC_LVT_DM_INIT:
666 printf("INIT");
667 break;
668 case APIC_LVT_DM_EXTINT:
669 printf("ExtINT");
670 break;
671 }
672 printf(" -> LINT%u\n", pin);
673 }
674 return (0);
675 }
676
677 int
678 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
679 {
680
681 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
682 return (EINVAL);
683 if (apic_id == APIC_ID_ALL) {
684 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
685 if (bootverbose)
686 printf("lapic:");
687 } else {
688 KASSERT(lapics[apic_id].la_present,
689 ("%s: missing APIC %u", __func__, apic_id));
690 lapics[apic_id].la_lvts[pin].lvt_active = 1;
691 lapics[apic_id].la_lvts[pin].lvt_activehi =
692 (pol == INTR_POLARITY_HIGH);
693 if (bootverbose)
694 printf("lapic%u:", apic_id);
695 }
696 if (bootverbose)
697 printf(" LINT%u polarity: %s\n", pin,
698 pol == INTR_POLARITY_HIGH ? "high" : "low");
699 return (0);
700 }
701
702 int
703 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
704 {
705
706 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
707 return (EINVAL);
708 if (apic_id == APIC_ID_ALL) {
709 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
710 if (bootverbose)
711 printf("lapic:");
712 } else {
713 KASSERT(lapics[apic_id].la_present,
714 ("%s: missing APIC %u", __func__, apic_id));
715 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
716 (trigger == INTR_TRIGGER_EDGE);
717 lapics[apic_id].la_lvts[pin].lvt_active = 1;
718 if (bootverbose)
719 printf("lapic%u:", apic_id);
720 }
721 if (bootverbose)
722 printf(" LINT%u trigger: %s\n", pin,
723 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
724 return (0);
725 }
726
727 /*
728 * Adjust the TPR of the current CPU so that it blocks all interrupts below
729 * the passed in vector.
730 */
731 void
732 lapic_set_tpr(u_int vector)
733 {
734 #ifdef CHEAP_TPR
735 lapic->tpr = vector;
736 #else
737 u_int32_t tpr;
738
739 tpr = lapic->tpr & ~APIC_TPR_PRIO;
740 tpr |= vector;
741 lapic->tpr = tpr;
742 #endif
743 }
744
745 void
746 lapic_eoi(void)
747 {
748
749 lapic->eoi = 0;
750 }
751
752 void
753 lapic_handle_intr(int vector, struct trapframe *frame)
754 {
755 struct intsrc *isrc;
756
757 if (vector == -1)
758 panic("Couldn't get vector from ISR!");
759 isrc = intr_lookup_source(apic_idt_to_irq(vector));
760 intr_execute_handlers(isrc, frame);
761 }
762
763 void
764 lapic_handle_timer(struct trapframe *frame)
765 {
766 struct lapic *la;
767
768 /* Send EOI first thing. */
769 lapic_eoi();
770
771 #if defined(SMP) && !defined(SCHED_ULE)
772 /*
773 * Don't do any accounting for the disabled HTT cores, since it
774 * will provide misleading numbers for the userland.
775 *
776 * No locking is necessary here, since even if we loose the race
777 * when hlt_cpus_mask changes it is not a big deal, really.
778 *
779 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
780 * and unlike other schedulers it actually schedules threads to
781 * those CPUs.
782 */
783 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
784 return;
785 #endif
786
787 /* Look up our local APIC structure for the tick counters. */
788 la = &lapics[PCPU_GET(apic_id)];
789 (*la->la_timer_count)++;
790 critical_enter();
791
792 #ifdef KDTRACE_HOOKS
793 /*
794 * If the DTrace hooks are configured and a callback function
795 * has been registered, then call it to process the high speed
796 * timers.
797 */
798 int cpu = PCPU_GET(cpuid);
799 if (lapic_cyclic_clock_func[cpu] != NULL)
800 (*lapic_cyclic_clock_func[cpu])(frame);
801 #endif
802
803 /* Fire hardclock at hz. */
804 la->la_hard_ticks += hz;
805 if (la->la_hard_ticks >= lapic_timer_hz) {
806 la->la_hard_ticks -= lapic_timer_hz;
807 if (PCPU_GET(cpuid) == 0)
808 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
809 else
810 hardclock_cpu(TRAPF_USERMODE(frame));
811 }
812
813 /* Fire statclock at stathz. */
814 la->la_stat_ticks += stathz;
815 if (la->la_stat_ticks >= lapic_timer_hz) {
816 la->la_stat_ticks -= lapic_timer_hz;
817 statclock(TRAPF_USERMODE(frame));
818 }
819
820 /* Fire profclock at profhz, but only when needed. */
821 la->la_prof_ticks += profhz;
822 if (la->la_prof_ticks >= lapic_timer_hz) {
823 la->la_prof_ticks -= lapic_timer_hz;
824 if (profprocs != 0)
825 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
826 }
827 critical_exit();
828 }
829
830 static void
831 lapic_timer_set_divisor(u_int divisor)
832 {
833
834 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
835 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
836 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
837 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
838 }
839
840 static void
841 lapic_timer_oneshot(u_int count)
842 {
843 u_int32_t value;
844
845 value = lapic->lvt_timer;
846 value &= ~APIC_LVTT_TM;
847 value |= APIC_LVTT_TM_ONE_SHOT;
848 lapic->lvt_timer = value;
849 lapic->icr_timer = count;
850 }
851
852 static void
853 lapic_timer_periodic(u_int count)
854 {
855 u_int32_t value;
856
857 value = lapic->lvt_timer;
858 value &= ~APIC_LVTT_TM;
859 value |= APIC_LVTT_TM_PERIODIC;
860 lapic->lvt_timer = value;
861 lapic->icr_timer = count;
862 }
863
864 static void
865 lapic_timer_enable_intr(void)
866 {
867 u_int32_t value;
868
869 value = lapic->lvt_timer;
870 value &= ~APIC_LVT_M;
871 lapic->lvt_timer = value;
872 }
873
874 void
875 lapic_handle_cmc(void)
876 {
877
878 lapic_eoi();
879 cmc_intr();
880 }
881
882 /*
883 * Called from the mca_init() to activate the CMC interrupt if this CPU is
884 * responsible for monitoring any MC banks for CMC events. Since mca_init()
885 * is called prior to lapic_setup() during boot, this just needs to unmask
886 * this CPU's LVT_CMCI entry.
887 */
888 void
889 lapic_enable_cmc(void)
890 {
891 u_int apic_id;
892
893 apic_id = PCPU_GET(apic_id);
894 KASSERT(lapics[apic_id].la_present,
895 ("%s: missing APIC %u", __func__, apic_id));
896 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0;
897 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1;
898 if (bootverbose)
899 printf("lapic%u: CMCI unmasked\n", apic_id);
900 }
901
902 void
903 lapic_handle_error(void)
904 {
905 u_int32_t esr;
906
907 /*
908 * Read the contents of the error status register. Write to
909 * the register first before reading from it to force the APIC
910 * to update its value to indicate any errors that have
911 * occurred since the previous write to the register.
912 */
913 lapic->esr = 0;
914 esr = lapic->esr;
915
916 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
917 lapic_eoi();
918 }
919
920 /* Request a free IDT vector to be used by the specified IRQ. */
921 u_int
922 apic_alloc_vector(u_int irq)
923 {
924 u_int vector;
925
926 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
927
928 /*
929 * Search for a free vector. Currently we just use a very simple
930 * algorithm to find the first free vector.
931 */
932 mtx_lock_spin(&icu_lock);
933 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
934 if (ioint_irqs[vector] != 0)
935 continue;
936 ioint_irqs[vector] = irq;
937 mtx_unlock_spin(&icu_lock);
938 return (vector + APIC_IO_INTS);
939 }
940 mtx_unlock_spin(&icu_lock);
941 panic("Couldn't find an APIC vector for IRQ %u", irq);
942 }
943
944 /*
945 * Request 'count' free contiguous IDT vectors to be used by 'count'
946 * IRQs. 'count' must be a power of two and the vectors will be
947 * aligned on a boundary of 'align'. If the request cannot be
948 * satisfied, 0 is returned.
949 */
950 u_int
951 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
952 {
953 u_int first, run, vector;
954
955 KASSERT(powerof2(count), ("bad count"));
956 KASSERT(powerof2(align), ("bad align"));
957 KASSERT(align >= count, ("align < count"));
958 #ifdef INVARIANTS
959 for (run = 0; run < count; run++)
960 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
961 irqs[run], run));
962 #endif
963
964 /*
965 * Search for 'count' free vectors. As with apic_alloc_vector(),
966 * this just uses a simple first fit algorithm.
967 */
968 run = 0;
969 first = 0;
970 mtx_lock_spin(&icu_lock);
971 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
972
973 /* Vector is in use, end run. */
974 if (ioint_irqs[vector] != 0) {
975 run = 0;
976 first = 0;
977 continue;
978 }
979
980 /* Start a new run if run == 0 and vector is aligned. */
981 if (run == 0) {
982 if ((vector & (align - 1)) != 0)
983 continue;
984 first = vector;
985 }
986 run++;
987
988 /* Keep looping if the run isn't long enough yet. */
989 if (run < count)
990 continue;
991
992 /* Found a run, assign IRQs and return the first vector. */
993 for (vector = 0; vector < count; vector++)
994 ioint_irqs[first + vector] = irqs[vector];
995 mtx_unlock_spin(&icu_lock);
996 return (first + APIC_IO_INTS);
997 }
998 mtx_unlock_spin(&icu_lock);
999 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1000 return (0);
1001 }
1002
1003 void
1004 apic_enable_vector(u_int vector)
1005 {
1006
1007 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1008 KASSERT(ioint_handlers[vector / 32] != NULL,
1009 ("No ISR handler for vector %u", vector));
1010 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
1011 GSEL(GCODE_SEL, SEL_KPL));
1012 }
1013
1014 void
1015 apic_disable_vector(u_int vector)
1016 {
1017
1018 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1019 KASSERT(ioint_handlers[vector / 32] != NULL,
1020 ("No ISR handler for vector %u", vector));
1021 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL,
1022 GSEL(GCODE_SEL, SEL_KPL));
1023 }
1024
1025 /* Release an APIC vector when it's no longer in use. */
1026 void
1027 apic_free_vector(u_int vector, u_int irq)
1028 {
1029 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1030 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1031 ("Vector %u does not map to an IRQ line", vector));
1032 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1033 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
1034 mtx_lock_spin(&icu_lock);
1035 ioint_irqs[vector - APIC_IO_INTS] = 0;
1036 mtx_unlock_spin(&icu_lock);
1037 }
1038
1039 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1040 u_int
1041 apic_idt_to_irq(u_int vector)
1042 {
1043
1044 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1045 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1046 ("Vector %u does not map to an IRQ line", vector));
1047 return (ioint_irqs[vector - APIC_IO_INTS]);
1048 }
1049
1050 #ifdef DDB
1051 /*
1052 * Dump data about APIC IDT vector mappings.
1053 */
1054 DB_SHOW_COMMAND(apic, db_show_apic)
1055 {
1056 struct intsrc *isrc;
1057 int i, verbose;
1058 u_int irq;
1059
1060 if (strcmp(modif, "vv") == 0)
1061 verbose = 2;
1062 else if (strcmp(modif, "v") == 0)
1063 verbose = 1;
1064 else
1065 verbose = 0;
1066 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1067 irq = ioint_irqs[i];
1068 if (irq != 0 && irq != IRQ_SYSCALL) {
1069 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1070 if (irq == IRQ_TIMER)
1071 db_printf("lapic timer\n");
1072 else if (irq < NUM_IO_INTS) {
1073 isrc = intr_lookup_source(irq);
1074 if (isrc == NULL || verbose == 0)
1075 db_printf("IRQ %u\n", irq);
1076 else
1077 db_dump_intr_event(isrc->is_event,
1078 verbose == 2);
1079 } else
1080 db_printf("IRQ %u ???\n", irq);
1081 }
1082 }
1083 }
1084
1085 static void
1086 dump_mask(const char *prefix, uint32_t v, int base)
1087 {
1088 int i, first;
1089
1090 first = 1;
1091 for (i = 0; i < 32; i++)
1092 if (v & (1 << i)) {
1093 if (first) {
1094 db_printf("%s:", prefix);
1095 first = 0;
1096 }
1097 db_printf(" %02x", base + i);
1098 }
1099 if (!first)
1100 db_printf("\n");
1101 }
1102
1103 /* Show info from the lapic regs for this CPU. */
1104 DB_SHOW_COMMAND(lapic, db_show_lapic)
1105 {
1106 uint32_t v;
1107
1108 db_printf("lapic ID = %d\n", lapic_id());
1109 v = lapic->version;
1110 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1111 v & 0xf);
1112 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1113 v = lapic->svr;
1114 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1115 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1116 db_printf("TPR = %02x\n", lapic->tpr);
1117
1118 #define dump_field(prefix, index) \
1119 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1120 index * 32)
1121
1122 db_printf("In-service Interrupts:\n");
1123 dump_field(isr, 0);
1124 dump_field(isr, 1);
1125 dump_field(isr, 2);
1126 dump_field(isr, 3);
1127 dump_field(isr, 4);
1128 dump_field(isr, 5);
1129 dump_field(isr, 6);
1130 dump_field(isr, 7);
1131
1132 db_printf("TMR Interrupts:\n");
1133 dump_field(tmr, 0);
1134 dump_field(tmr, 1);
1135 dump_field(tmr, 2);
1136 dump_field(tmr, 3);
1137 dump_field(tmr, 4);
1138 dump_field(tmr, 5);
1139 dump_field(tmr, 6);
1140 dump_field(tmr, 7);
1141
1142 db_printf("IRR Interrupts:\n");
1143 dump_field(irr, 0);
1144 dump_field(irr, 1);
1145 dump_field(irr, 2);
1146 dump_field(irr, 3);
1147 dump_field(irr, 4);
1148 dump_field(irr, 5);
1149 dump_field(irr, 6);
1150 dump_field(irr, 7);
1151
1152 #undef dump_field
1153 }
1154 #endif
1155
1156 /*
1157 * APIC probing support code. This includes code to manage enumerators.
1158 */
1159
1160 static SLIST_HEAD(, apic_enumerator) enumerators =
1161 SLIST_HEAD_INITIALIZER(enumerators);
1162 static struct apic_enumerator *best_enum;
1163
1164 void
1165 apic_register_enumerator(struct apic_enumerator *enumerator)
1166 {
1167 #ifdef INVARIANTS
1168 struct apic_enumerator *apic_enum;
1169
1170 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1171 if (apic_enum == enumerator)
1172 panic("%s: Duplicate register of %s", __func__,
1173 enumerator->apic_name);
1174 }
1175 #endif
1176 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1177 }
1178
1179 /*
1180 * Probe the APIC enumerators, enumerate CPUs, and initialize the
1181 * local APIC.
1182 */
1183 static void
1184 apic_init(void *dummy __unused)
1185 {
1186 struct apic_enumerator *enumerator;
1187 uint64_t apic_base;
1188 int retval, best;
1189
1190 /* We only support built in local APICs. */
1191 if (!(cpu_feature & CPUID_APIC))
1192 return;
1193
1194 /* Don't probe if APIC mode is disabled. */
1195 if (resource_disabled("apic", 0))
1196 return;
1197
1198 /* First, probe all the enumerators to find the best match. */
1199 best_enum = NULL;
1200 best = 0;
1201 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1202 retval = enumerator->apic_probe();
1203 if (retval > 0)
1204 continue;
1205 if (best_enum == NULL || best < retval) {
1206 best_enum = enumerator;
1207 best = retval;
1208 }
1209 }
1210 if (best_enum == NULL) {
1211 if (bootverbose)
1212 printf("APIC: Could not find any APICs.\n");
1213 return;
1214 }
1215
1216 if (bootverbose)
1217 printf("APIC: Using the %s enumerator.\n",
1218 best_enum->apic_name);
1219
1220 /*
1221 * To work around an errata, we disable the local APIC on some
1222 * CPUs during early startup. We need to turn the local APIC back
1223 * on on such CPUs now.
1224 */
1225 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
1226 (cpu_id & 0xff0) == 0x610) {
1227 apic_base = rdmsr(MSR_APICBASE);
1228 apic_base |= APICBASE_ENABLED;
1229 wrmsr(MSR_APICBASE, apic_base);
1230 }
1231
1232 /* Second, probe the CPU's in the system. */
1233 retval = best_enum->apic_probe_cpus();
1234 if (retval != 0)
1235 printf("%s: Failed to probe CPUs: returned %d\n",
1236 best_enum->apic_name, retval);
1237
1238 /* Third, initialize the local APIC. */
1239 retval = best_enum->apic_setup_local();
1240 if (retval != 0)
1241 printf("%s: Failed to setup the local APIC: returned %d\n",
1242 best_enum->apic_name, retval);
1243 }
1244 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL);
1245
1246 /*
1247 * Setup the I/O APICs.
1248 */
1249 static void
1250 apic_setup_io(void *dummy __unused)
1251 {
1252 int retval;
1253
1254 if (best_enum == NULL)
1255 return;
1256 retval = best_enum->apic_setup_io();
1257 if (retval != 0)
1258 printf("%s: Failed to setup I/O APICs: returned %d\n",
1259 best_enum->apic_name, retval);
1260
1261 /*
1262 * Finish setting up the local APIC on the BSP once we know how to
1263 * properly program the LINT pins.
1264 */
1265 lapic_setup(1);
1266 intr_register_pic(&lapic_pic);
1267 if (bootverbose)
1268 lapic_dump("BSP");
1269
1270 /* Enable the MSI "pic". */
1271 msi_init();
1272 }
1273 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1274
1275 #ifdef SMP
1276 /*
1277 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1278 * private to the sys/i386 code. The public interface for the rest of the
1279 * kernel is defined in mp_machdep.c.
1280 */
1281 int
1282 lapic_ipi_wait(int delay)
1283 {
1284 int x, incr;
1285
1286 /*
1287 * Wait delay loops for IPI to be sent. This is highly bogus
1288 * since this is sensitive to CPU clock speed. If delay is
1289 * -1, we wait forever.
1290 */
1291 if (delay == -1) {
1292 incr = 0;
1293 delay = 1;
1294 } else
1295 incr = 1;
1296 for (x = 0; x < delay; x += incr) {
1297 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1298 return (1);
1299 ia32_pause();
1300 }
1301 return (0);
1302 }
1303
1304 void
1305 lapic_ipi_raw(register_t icrlo, u_int dest)
1306 {
1307 register_t value, eflags;
1308
1309 /* XXX: Need more sanity checking of icrlo? */
1310 KASSERT(lapic != NULL, ("%s called too early", __func__));
1311 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1312 ("%s: invalid dest field", __func__));
1313 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1314 ("%s: reserved bits set in ICR LO register", __func__));
1315
1316 /* Set destination in ICR HI register if it is being used. */
1317 eflags = intr_disable();
1318 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1319 value = lapic->icr_hi;
1320 value &= ~APIC_ID_MASK;
1321 value |= dest << APIC_ID_SHIFT;
1322 lapic->icr_hi = value;
1323 }
1324
1325 /* Program the contents of the IPI and dispatch it. */
1326 value = lapic->icr_lo;
1327 value &= APIC_ICRLO_RESV_MASK;
1328 value |= icrlo;
1329 lapic->icr_lo = value;
1330 intr_restore(eflags);
1331 }
1332
1333 #define BEFORE_SPIN 1000000
1334 #ifdef DETECT_DEADLOCK
1335 #define AFTER_SPIN 1000
1336 #endif
1337
1338 void
1339 lapic_ipi_vectored(u_int vector, int dest)
1340 {
1341 register_t icrlo, destfield;
1342
1343 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1344 ("%s: invalid vector %d", __func__, vector));
1345
1346 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1347 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1348 destfield = 0;
1349 switch (dest) {
1350 case APIC_IPI_DEST_SELF:
1351 icrlo |= APIC_DEST_SELF;
1352 break;
1353 case APIC_IPI_DEST_ALL:
1354 icrlo |= APIC_DEST_ALLISELF;
1355 break;
1356 case APIC_IPI_DEST_OTHERS:
1357 icrlo |= APIC_DEST_ALLESELF;
1358 break;
1359 default:
1360 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1361 ("%s: invalid destination 0x%x", __func__, dest));
1362 destfield = dest;
1363 }
1364
1365 /* Wait for an earlier IPI to finish. */
1366 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1367 if (panicstr != NULL)
1368 return;
1369 else
1370 panic("APIC: Previous IPI is stuck");
1371 }
1372
1373 lapic_ipi_raw(icrlo, destfield);
1374
1375 #ifdef DETECT_DEADLOCK
1376 /* Wait for IPI to be delivered. */
1377 if (!lapic_ipi_wait(AFTER_SPIN)) {
1378 #ifdef needsattention
1379 /*
1380 * XXX FIXME:
1381 *
1382 * The above function waits for the message to actually be
1383 * delivered. It breaks out after an arbitrary timeout
1384 * since the message should eventually be delivered (at
1385 * least in theory) and that if it wasn't we would catch
1386 * the failure with the check above when the next IPI is
1387 * sent.
1388 *
1389 * We could skip this wait entirely, EXCEPT it probably
1390 * protects us from other routines that assume that the
1391 * message was delivered and acted upon when this function
1392 * returns.
1393 */
1394 printf("APIC: IPI might be stuck\n");
1395 #else /* !needsattention */
1396 /* Wait until mesage is sent without a timeout. */
1397 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1398 ia32_pause();
1399 #endif /* needsattention */
1400 }
1401 #endif /* DETECT_DEADLOCK */
1402 }
1403 #endif /* SMP */
Cache object: 4f4ae9e61c77b4f39cf73e6238be21f7
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