Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/local_apic.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/8.0/sys/i386/i386/local_apic.c 196996 2009-09-08 21:50:34Z jhb $"); 36 37 #include "opt_hwpmc_hooks.h" 38 #include "opt_kdtrace.h" 39 40 #include "opt_ddb.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/pcpu.h> 49 #include <sys/proc.h> 50 #include <sys/sched.h> 51 #include <sys/smp.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 56 #include <machine/apicreg.h> 57 #include <machine/cpu.h> 58 #include <machine/cputypes.h> 59 #include <machine/frame.h> 60 #include <machine/intr_machdep.h> 61 #include <machine/apicvar.h> 62 #include <machine/md_var.h> 63 #include <machine/smp.h> 64 #include <machine/specialreg.h> 65 66 #ifdef DDB 67 #include <sys/interrupt.h> 68 #include <ddb/ddb.h> 69 #endif 70 71 #ifdef KDTRACE_HOOKS 72 #include <sys/dtrace_bsd.h> 73 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 74 #endif 75 76 /* Sanity checks on IDT vectors. */ 77 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 78 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 79 CTASSERT(APIC_LOCAL_INTS == 240); 80 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 81 82 /* Magic IRQ values for the timer and syscalls. */ 83 #define IRQ_TIMER (NUM_IO_INTS + 1) 84 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 85 86 /* 87 * Support for local APICs. Local APICs manage interrupts on each 88 * individual processor as opposed to I/O APICs which receive interrupts 89 * from I/O devices and then forward them on to the local APICs. 90 * 91 * Local APICs can also send interrupts to each other thus providing the 92 * mechanism for IPIs. 93 */ 94 95 struct lvt { 96 u_int lvt_edgetrigger:1; 97 u_int lvt_activehi:1; 98 u_int lvt_masked:1; 99 u_int lvt_active:1; 100 u_int lvt_mode:16; 101 u_int lvt_vector:8; 102 }; 103 104 struct lapic { 105 struct lvt la_lvts[LVT_MAX + 1]; 106 u_int la_id:8; 107 u_int la_cluster:4; 108 u_int la_cluster_id:2; 109 u_int la_present:1; 110 u_long *la_timer_count; 111 u_long la_hard_ticks; 112 u_long la_stat_ticks; 113 u_long la_prof_ticks; 114 /* Include IDT_SYSCALL to make indexing easier. */ 115 int la_ioint_irqs[APIC_NUM_IOINTS + 1]; 116 } static lapics[MAX_APIC_ID + 1]; 117 118 /* XXX: should thermal be an NMI? */ 119 120 /* Global defaults for local APIC LVT entries. */ 121 static struct lvt lvts[LVT_MAX + 1] = { 122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 126 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 128 }; 129 130 static inthand_t *ioint_handlers[] = { 131 NULL, /* 0 - 31 */ 132 IDTVEC(apic_isr1), /* 32 - 63 */ 133 IDTVEC(apic_isr2), /* 64 - 95 */ 134 IDTVEC(apic_isr3), /* 96 - 127 */ 135 IDTVEC(apic_isr4), /* 128 - 159 */ 136 IDTVEC(apic_isr5), /* 160 - 191 */ 137 IDTVEC(apic_isr6), /* 192 - 223 */ 138 IDTVEC(apic_isr7), /* 224 - 255 */ 139 }; 140 141 142 static u_int32_t lapic_timer_divisors[] = { 143 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 144 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 145 }; 146 147 extern inthand_t IDTVEC(rsvd); 148 149 volatile lapic_t *lapic; 150 vm_paddr_t lapic_paddr; 151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 152 153 static void lapic_enable(void); 154 static void lapic_resume(struct pic *pic); 155 static void lapic_timer_enable_intr(void); 156 static void lapic_timer_oneshot(u_int count); 157 static void lapic_timer_periodic(u_int count); 158 static void lapic_timer_set_divisor(u_int divisor); 159 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 160 161 struct pic lapic_pic = { .pic_resume = lapic_resume }; 162 163 static uint32_t 164 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 165 { 166 struct lvt *lvt; 167 168 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 169 if (la->la_lvts[pin].lvt_active) 170 lvt = &la->la_lvts[pin]; 171 else 172 lvt = &lvts[pin]; 173 174 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 175 APIC_LVT_VECTOR); 176 if (lvt->lvt_edgetrigger == 0) 177 value |= APIC_LVT_TM; 178 if (lvt->lvt_activehi == 0) 179 value |= APIC_LVT_IIPP_INTALO; 180 if (lvt->lvt_masked) 181 value |= APIC_LVT_M; 182 value |= lvt->lvt_mode; 183 switch (lvt->lvt_mode) { 184 case APIC_LVT_DM_NMI: 185 case APIC_LVT_DM_SMI: 186 case APIC_LVT_DM_INIT: 187 case APIC_LVT_DM_EXTINT: 188 if (!lvt->lvt_edgetrigger) { 189 printf("lapic%u: Forcing LINT%u to edge trigger\n", 190 la->la_id, pin); 191 value |= APIC_LVT_TM; 192 } 193 /* Use a vector of 0. */ 194 break; 195 case APIC_LVT_DM_FIXED: 196 value |= lvt->lvt_vector; 197 break; 198 default: 199 panic("bad APIC LVT delivery mode: %#x\n", value); 200 } 201 return (value); 202 } 203 204 /* 205 * Map the local APIC and setup necessary interrupt vectors. 206 */ 207 void 208 lapic_init(vm_paddr_t addr) 209 { 210 211 /* Map the local APIC and setup the spurious interrupt handler. */ 212 KASSERT(trunc_page(addr) == addr, 213 ("local APIC not aligned on a page boundary")); 214 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 215 lapic_paddr = addr; 216 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 217 GSEL(GCODE_SEL, SEL_KPL)); 218 219 /* Perform basic initialization of the BSP's local APIC. */ 220 lapic_enable(); 221 222 /* Set BSP's per-CPU local APIC ID. */ 223 PCPU_SET(apic_id, lapic_id()); 224 225 /* Local APIC timer interrupt. */ 226 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 227 GSEL(GCODE_SEL, SEL_KPL)); 228 229 /* XXX: error/thermal interrupts */ 230 } 231 232 /* 233 * Create a local APIC instance. 234 */ 235 void 236 lapic_create(u_int apic_id, int boot_cpu) 237 { 238 int i; 239 240 if (apic_id > MAX_APIC_ID) { 241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 242 if (boot_cpu) 243 panic("Can't ignore BSP"); 244 return; 245 } 246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 247 apic_id)); 248 249 /* 250 * Assume no local LVT overrides and a cluster of 0 and 251 * intra-cluster ID of 0. 252 */ 253 lapics[apic_id].la_present = 1; 254 lapics[apic_id].la_id = apic_id; 255 for (i = 0; i < LVT_MAX; i++) { 256 lapics[apic_id].la_lvts[i] = lvts[i]; 257 lapics[apic_id].la_lvts[i].lvt_active = 0; 258 } 259 for (i = 0; i <= APIC_NUM_IOINTS; i++) 260 lapics[apic_id].la_ioint_irqs[i] = -1; 261 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 262 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = 263 IRQ_TIMER; 264 265 #ifdef SMP 266 cpu_add(apic_id, boot_cpu); 267 #endif 268 } 269 270 /* 271 * Dump contents of local APIC registers 272 */ 273 void 274 lapic_dump(const char* str) 275 { 276 277 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 278 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 279 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 280 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 281 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 282 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 283 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 284 lapic->lvt_pcint); 285 } 286 287 void 288 lapic_setup(int boot) 289 { 290 struct lapic *la; 291 u_int32_t maxlvt; 292 register_t eflags; 293 char buf[MAXCOMLEN + 1]; 294 295 la = &lapics[lapic_id()]; 296 KASSERT(la->la_present, ("missing APIC structure")); 297 eflags = intr_disable(); 298 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 299 300 /* Initialize the TPR to allow all interrupts. */ 301 lapic_set_tpr(0); 302 303 /* Setup spurious vector and enable the local APIC. */ 304 lapic_enable(); 305 306 /* Program LINT[01] LVT entries. */ 307 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 308 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 309 310 /* Program the PMC LVT entry if present. */ 311 if (maxlvt >= LVT_PMC) 312 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 313 314 /* Program timer LVT and setup handler. */ 315 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 316 if (boot) { 317 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 318 intrcnt_add(buf, &la->la_timer_count); 319 } 320 321 /* We don't setup the timer during boot on the BSP until later. */ 322 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) { 323 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 324 lapic_id())); 325 lapic_timer_set_divisor(lapic_timer_divisor); 326 lapic_timer_periodic(lapic_timer_period); 327 lapic_timer_enable_intr(); 328 } 329 330 /* XXX: Error and thermal LVTs */ 331 332 intr_restore(eflags); 333 } 334 335 void 336 lapic_reenable_pmc(void) 337 { 338 #ifdef HWPMC_HOOKS 339 uint32_t value; 340 341 value = lapic->lvt_pcint; 342 value &= ~APIC_LVT_M; 343 lapic->lvt_pcint = value; 344 #endif 345 } 346 347 #ifdef HWPMC_HOOKS 348 static void 349 lapic_update_pmc(void *dummy) 350 { 351 struct lapic *la; 352 353 la = &lapics[lapic_id()]; 354 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 355 } 356 #endif 357 358 int 359 lapic_enable_pmc(void) 360 { 361 #ifdef HWPMC_HOOKS 362 u_int32_t maxlvt; 363 364 /* Fail if the local APIC is not present. */ 365 if (lapic == NULL) 366 return (0); 367 368 /* Fail if the PMC LVT is not present. */ 369 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 370 if (maxlvt < LVT_PMC) 371 return (0); 372 373 lvts[LVT_PMC].lvt_masked = 0; 374 375 #ifdef SMP 376 /* 377 * If hwpmc was loaded at boot time then the APs may not be 378 * started yet. In that case, don't forward the request to 379 * them as they will program the lvt when they start. 380 */ 381 if (smp_started) 382 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 383 else 384 #endif 385 lapic_update_pmc(NULL); 386 return (1); 387 #else 388 return (0); 389 #endif 390 } 391 392 void 393 lapic_disable_pmc(void) 394 { 395 #ifdef HWPMC_HOOKS 396 u_int32_t maxlvt; 397 398 /* Fail if the local APIC is not present. */ 399 if (lapic == NULL) 400 return; 401 402 /* Fail if the PMC LVT is not present. */ 403 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 404 if (maxlvt < LVT_PMC) 405 return; 406 407 lvts[LVT_PMC].lvt_masked = 1; 408 409 #ifdef SMP 410 /* The APs should always be started when hwpmc is unloaded. */ 411 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 412 #endif 413 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 414 #endif 415 } 416 417 /* 418 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 419 * that it can drive hardclock, statclock, and profclock. This function 420 * returns true if it is able to use the local APIC timer to drive the 421 * clocks and false if it is not able. 422 */ 423 int 424 lapic_setup_clock(void) 425 { 426 u_long value; 427 int i; 428 429 /* Can't drive the timer without a local APIC. */ 430 if (lapic == NULL) 431 return (0); 432 433 if (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0) 434 return (0); 435 436 /* Start off with a divisor of 2 (power on reset default). */ 437 lapic_timer_divisor = 2; 438 439 /* Try to calibrate the local APIC timer. */ 440 do { 441 lapic_timer_set_divisor(lapic_timer_divisor); 442 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 443 DELAY(2000000); 444 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 445 if (value != APIC_TIMER_MAX_COUNT) 446 break; 447 lapic_timer_divisor <<= 1; 448 } while (lapic_timer_divisor <= 128); 449 if (lapic_timer_divisor > 128) 450 panic("lapic: Divisor too big"); 451 value /= 2; 452 if (bootverbose) 453 printf("lapic: Divisor %lu, Frequency %lu hz\n", 454 lapic_timer_divisor, value); 455 456 /* 457 * We want to run stathz in the neighborhood of 128hz. We would 458 * like profhz to run as often as possible, so we let it run on 459 * each clock tick. We try to honor the requested 'hz' value as 460 * much as possible. 461 * 462 * If 'hz' is above 1500, then we just let the lapic timer 463 * (and profhz) run at hz. If 'hz' is below 1500 but above 464 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 465 * is below 750 then we let the lapic timer run at 4 * 'hz'. 466 */ 467 if (hz >= 1500) 468 lapic_timer_hz = hz; 469 else if (hz >= 750) 470 lapic_timer_hz = hz * 2; 471 else 472 lapic_timer_hz = hz * 4; 473 if (lapic_timer_hz < 128) 474 stathz = lapic_timer_hz; 475 else 476 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 477 profhz = lapic_timer_hz; 478 lapic_timer_period = value / lapic_timer_hz; 479 480 /* 481 * Start up the timer on the BSP. The APs will kick off their 482 * timer during lapic_setup(). 483 */ 484 lapic_timer_periodic(lapic_timer_period); 485 lapic_timer_enable_intr(); 486 return (1); 487 } 488 489 void 490 lapic_disable(void) 491 { 492 uint32_t value; 493 494 /* Software disable the local APIC. */ 495 value = lapic->svr; 496 value &= ~APIC_SVR_SWEN; 497 lapic->svr = value; 498 } 499 500 static void 501 lapic_enable(void) 502 { 503 u_int32_t value; 504 505 /* Program the spurious vector to enable the local APIC. */ 506 value = lapic->svr; 507 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 508 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 509 lapic->svr = value; 510 } 511 512 /* Reset the local APIC on the BSP during resume. */ 513 static void 514 lapic_resume(struct pic *pic) 515 { 516 517 lapic_setup(0); 518 } 519 520 int 521 lapic_id(void) 522 { 523 524 KASSERT(lapic != NULL, ("local APIC is not mapped")); 525 return (lapic->id >> APIC_ID_SHIFT); 526 } 527 528 int 529 lapic_intr_pending(u_int vector) 530 { 531 volatile u_int32_t *irr; 532 533 /* 534 * The IRR registers are an array of 128-bit registers each of 535 * which only describes 32 interrupts in the low 32 bits.. Thus, 536 * we divide the vector by 32 to get the 128-bit index. We then 537 * multiply that index by 4 to get the equivalent index from 538 * treating the IRR as an array of 32-bit registers. Finally, we 539 * modulus the vector by 32 to determine the individual bit to 540 * test. 541 */ 542 irr = &lapic->irr0; 543 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 544 } 545 546 void 547 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 548 { 549 struct lapic *la; 550 551 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 552 __func__, apic_id)); 553 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 554 __func__, cluster)); 555 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 556 ("%s: intra cluster id %u too big", __func__, cluster_id)); 557 la = &lapics[apic_id]; 558 la->la_cluster = cluster; 559 la->la_cluster_id = cluster_id; 560 } 561 562 int 563 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 564 { 565 566 if (pin > LVT_MAX) 567 return (EINVAL); 568 if (apic_id == APIC_ID_ALL) { 569 lvts[pin].lvt_masked = masked; 570 if (bootverbose) 571 printf("lapic:"); 572 } else { 573 KASSERT(lapics[apic_id].la_present, 574 ("%s: missing APIC %u", __func__, apic_id)); 575 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 576 lapics[apic_id].la_lvts[pin].lvt_active = 1; 577 if (bootverbose) 578 printf("lapic%u:", apic_id); 579 } 580 if (bootverbose) 581 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 582 return (0); 583 } 584 585 int 586 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 587 { 588 struct lvt *lvt; 589 590 if (pin > LVT_MAX) 591 return (EINVAL); 592 if (apic_id == APIC_ID_ALL) { 593 lvt = &lvts[pin]; 594 if (bootverbose) 595 printf("lapic:"); 596 } else { 597 KASSERT(lapics[apic_id].la_present, 598 ("%s: missing APIC %u", __func__, apic_id)); 599 lvt = &lapics[apic_id].la_lvts[pin]; 600 lvt->lvt_active = 1; 601 if (bootverbose) 602 printf("lapic%u:", apic_id); 603 } 604 lvt->lvt_mode = mode; 605 switch (mode) { 606 case APIC_LVT_DM_NMI: 607 case APIC_LVT_DM_SMI: 608 case APIC_LVT_DM_INIT: 609 case APIC_LVT_DM_EXTINT: 610 lvt->lvt_edgetrigger = 1; 611 lvt->lvt_activehi = 1; 612 if (mode == APIC_LVT_DM_EXTINT) 613 lvt->lvt_masked = 1; 614 else 615 lvt->lvt_masked = 0; 616 break; 617 default: 618 panic("Unsupported delivery mode: 0x%x\n", mode); 619 } 620 if (bootverbose) { 621 printf(" Routing "); 622 switch (mode) { 623 case APIC_LVT_DM_NMI: 624 printf("NMI"); 625 break; 626 case APIC_LVT_DM_SMI: 627 printf("SMI"); 628 break; 629 case APIC_LVT_DM_INIT: 630 printf("INIT"); 631 break; 632 case APIC_LVT_DM_EXTINT: 633 printf("ExtINT"); 634 break; 635 } 636 printf(" -> LINT%u\n", pin); 637 } 638 return (0); 639 } 640 641 int 642 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 643 { 644 645 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 646 return (EINVAL); 647 if (apic_id == APIC_ID_ALL) { 648 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 649 if (bootverbose) 650 printf("lapic:"); 651 } else { 652 KASSERT(lapics[apic_id].la_present, 653 ("%s: missing APIC %u", __func__, apic_id)); 654 lapics[apic_id].la_lvts[pin].lvt_active = 1; 655 lapics[apic_id].la_lvts[pin].lvt_activehi = 656 (pol == INTR_POLARITY_HIGH); 657 if (bootverbose) 658 printf("lapic%u:", apic_id); 659 } 660 if (bootverbose) 661 printf(" LINT%u polarity: %s\n", pin, 662 pol == INTR_POLARITY_HIGH ? "high" : "low"); 663 return (0); 664 } 665 666 int 667 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 668 { 669 670 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 671 return (EINVAL); 672 if (apic_id == APIC_ID_ALL) { 673 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 674 if (bootverbose) 675 printf("lapic:"); 676 } else { 677 KASSERT(lapics[apic_id].la_present, 678 ("%s: missing APIC %u", __func__, apic_id)); 679 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 680 (trigger == INTR_TRIGGER_EDGE); 681 lapics[apic_id].la_lvts[pin].lvt_active = 1; 682 if (bootverbose) 683 printf("lapic%u:", apic_id); 684 } 685 if (bootverbose) 686 printf(" LINT%u trigger: %s\n", pin, 687 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 688 return (0); 689 } 690 691 /* 692 * Adjust the TPR of the current CPU so that it blocks all interrupts below 693 * the passed in vector. 694 */ 695 void 696 lapic_set_tpr(u_int vector) 697 { 698 #ifdef CHEAP_TPR 699 lapic->tpr = vector; 700 #else 701 u_int32_t tpr; 702 703 tpr = lapic->tpr & ~APIC_TPR_PRIO; 704 tpr |= vector; 705 lapic->tpr = tpr; 706 #endif 707 } 708 709 void 710 lapic_eoi(void) 711 { 712 713 lapic->eoi = 0; 714 } 715 716 /* 717 * Read the contents of the error status register. We have to write 718 * to the register first before reading from it. 719 */ 720 u_int 721 lapic_error(void) 722 { 723 724 lapic->esr = 0; 725 return (lapic->esr); 726 } 727 728 void 729 lapic_handle_intr(int vector, struct trapframe *frame) 730 { 731 struct intsrc *isrc; 732 733 if (vector == -1) 734 panic("Couldn't get vector from ISR!"); 735 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id), 736 vector)); 737 intr_execute_handlers(isrc, frame); 738 } 739 740 void 741 lapic_handle_timer(struct trapframe *frame) 742 { 743 struct lapic *la; 744 745 /* Send EOI first thing. */ 746 lapic_eoi(); 747 748 #if defined(SMP) && !defined(SCHED_ULE) 749 /* 750 * Don't do any accounting for the disabled HTT cores, since it 751 * will provide misleading numbers for the userland. 752 * 753 * No locking is necessary here, since even if we loose the race 754 * when hlt_cpus_mask changes it is not a big deal, really. 755 * 756 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 757 * and unlike other schedulers it actually schedules threads to 758 * those CPUs. 759 */ 760 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 761 return; 762 #endif 763 764 /* Look up our local APIC structure for the tick counters. */ 765 la = &lapics[PCPU_GET(apic_id)]; 766 (*la->la_timer_count)++; 767 critical_enter(); 768 769 #ifdef KDTRACE_HOOKS 770 /* 771 * If the DTrace hooks are configured and a callback function 772 * has been registered, then call it to process the high speed 773 * timers. 774 */ 775 int cpu = PCPU_GET(cpuid); 776 if (lapic_cyclic_clock_func[cpu] != NULL) 777 (*lapic_cyclic_clock_func[cpu])(frame); 778 #endif 779 780 /* Fire hardclock at hz. */ 781 la->la_hard_ticks += hz; 782 if (la->la_hard_ticks >= lapic_timer_hz) { 783 la->la_hard_ticks -= lapic_timer_hz; 784 if (PCPU_GET(cpuid) == 0) 785 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 786 else 787 hardclock_cpu(TRAPF_USERMODE(frame)); 788 } 789 790 /* Fire statclock at stathz. */ 791 la->la_stat_ticks += stathz; 792 if (la->la_stat_ticks >= lapic_timer_hz) { 793 la->la_stat_ticks -= lapic_timer_hz; 794 statclock(TRAPF_USERMODE(frame)); 795 } 796 797 /* Fire profclock at profhz, but only when needed. */ 798 la->la_prof_ticks += profhz; 799 if (la->la_prof_ticks >= lapic_timer_hz) { 800 la->la_prof_ticks -= lapic_timer_hz; 801 if (profprocs != 0) 802 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 803 } 804 critical_exit(); 805 } 806 807 static void 808 lapic_timer_set_divisor(u_int divisor) 809 { 810 811 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 812 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 813 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 814 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 815 } 816 817 static void 818 lapic_timer_oneshot(u_int count) 819 { 820 u_int32_t value; 821 822 value = lapic->lvt_timer; 823 value &= ~APIC_LVTT_TM; 824 value |= APIC_LVTT_TM_ONE_SHOT; 825 lapic->lvt_timer = value; 826 lapic->icr_timer = count; 827 } 828 829 static void 830 lapic_timer_periodic(u_int count) 831 { 832 u_int32_t value; 833 834 value = lapic->lvt_timer; 835 value &= ~APIC_LVTT_TM; 836 value |= APIC_LVTT_TM_PERIODIC; 837 lapic->lvt_timer = value; 838 lapic->icr_timer = count; 839 } 840 841 static void 842 lapic_timer_enable_intr(void) 843 { 844 u_int32_t value; 845 846 value = lapic->lvt_timer; 847 value &= ~APIC_LVT_M; 848 lapic->lvt_timer = value; 849 } 850 851 u_int 852 apic_cpuid(u_int apic_id) 853 { 854 #ifdef SMP 855 return apic_cpuids[apic_id]; 856 #else 857 return 0; 858 #endif 859 } 860 861 /* Request a free IDT vector to be used by the specified IRQ. */ 862 u_int 863 apic_alloc_vector(u_int apic_id, u_int irq) 864 { 865 u_int vector; 866 867 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 868 869 /* 870 * Search for a free vector. Currently we just use a very simple 871 * algorithm to find the first free vector. 872 */ 873 mtx_lock_spin(&icu_lock); 874 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 875 if (lapics[apic_id].la_ioint_irqs[vector] != -1) 876 continue; 877 lapics[apic_id].la_ioint_irqs[vector] = irq; 878 mtx_unlock_spin(&icu_lock); 879 return (vector + APIC_IO_INTS); 880 } 881 mtx_unlock_spin(&icu_lock); 882 return (0); 883 } 884 885 /* 886 * Request 'count' free contiguous IDT vectors to be used by 'count' 887 * IRQs. 'count' must be a power of two and the vectors will be 888 * aligned on a boundary of 'align'. If the request cannot be 889 * satisfied, 0 is returned. 890 */ 891 u_int 892 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 893 { 894 u_int first, run, vector; 895 896 KASSERT(powerof2(count), ("bad count")); 897 KASSERT(powerof2(align), ("bad align")); 898 KASSERT(align >= count, ("align < count")); 899 #ifdef INVARIANTS 900 for (run = 0; run < count; run++) 901 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 902 irqs[run], run)); 903 #endif 904 905 /* 906 * Search for 'count' free vectors. As with apic_alloc_vector(), 907 * this just uses a simple first fit algorithm. 908 */ 909 run = 0; 910 first = 0; 911 mtx_lock_spin(&icu_lock); 912 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 913 914 /* Vector is in use, end run. */ 915 if (lapics[apic_id].la_ioint_irqs[vector] != -1) { 916 run = 0; 917 first = 0; 918 continue; 919 } 920 921 /* Start a new run if run == 0 and vector is aligned. */ 922 if (run == 0) { 923 if ((vector & (align - 1)) != 0) 924 continue; 925 first = vector; 926 } 927 run++; 928 929 /* Keep looping if the run isn't long enough yet. */ 930 if (run < count) 931 continue; 932 933 /* Found a run, assign IRQs and return the first vector. */ 934 for (vector = 0; vector < count; vector++) 935 lapics[apic_id].la_ioint_irqs[first + vector] = 936 irqs[vector]; 937 mtx_unlock_spin(&icu_lock); 938 return (first + APIC_IO_INTS); 939 } 940 mtx_unlock_spin(&icu_lock); 941 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 942 return (0); 943 } 944 945 /* 946 * Enable a vector for a particular apic_id. Since all lapics share idt 947 * entries and ioint_handlers this enables the vector on all lapics. lapics 948 * which do not have the vector configured would report spurious interrupts 949 * should it fire. 950 */ 951 void 952 apic_enable_vector(u_int apic_id, u_int vector) 953 { 954 955 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 956 KASSERT(ioint_handlers[vector / 32] != NULL, 957 ("No ISR handler for vector %u", vector)); 958 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 959 GSEL(GCODE_SEL, SEL_KPL)); 960 } 961 962 void 963 apic_disable_vector(u_int apic_id, u_int vector) 964 { 965 966 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 967 KASSERT(ioint_handlers[vector / 32] != NULL, 968 ("No ISR handler for vector %u", vector)); 969 #ifdef notyet 970 /* 971 * We can not currently clear the idt entry because other cpus 972 * may have a valid vector at this offset. 973 */ 974 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 975 GSEL(GCODE_SEL, SEL_KPL)); 976 #endif 977 } 978 979 /* Release an APIC vector when it's no longer in use. */ 980 void 981 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 982 { 983 struct thread *td; 984 985 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 986 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 987 ("Vector %u does not map to an IRQ line", vector)); 988 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 989 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] == 990 irq, ("IRQ mismatch")); 991 992 /* 993 * Bind us to the cpu that owned the vector before freeing it so 994 * we don't lose an interrupt delivery race. 995 */ 996 td = curthread; 997 if (!rebooting) { 998 thread_lock(td); 999 if (sched_is_bound(td)) 1000 panic("apic_free_vector: Thread already bound.\n"); 1001 sched_bind(td, apic_cpuid(apic_id)); 1002 thread_unlock(td); 1003 } 1004 mtx_lock_spin(&icu_lock); 1005 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1; 1006 mtx_unlock_spin(&icu_lock); 1007 if (!rebooting) { 1008 thread_lock(td); 1009 sched_unbind(td); 1010 thread_unlock(td); 1011 } 1012 } 1013 1014 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1015 u_int 1016 apic_idt_to_irq(u_int apic_id, u_int vector) 1017 { 1018 int irq; 1019 1020 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1021 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1022 ("Vector %u does not map to an IRQ line", vector)); 1023 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS]; 1024 if (irq < 0) 1025 irq = 0; 1026 return (irq); 1027 } 1028 1029 #ifdef DDB 1030 /* 1031 * Dump data about APIC IDT vector mappings. 1032 */ 1033 DB_SHOW_COMMAND(apic, db_show_apic) 1034 { 1035 struct intsrc *isrc; 1036 int i, verbose; 1037 u_int apic_id; 1038 u_int irq; 1039 1040 if (strcmp(modif, "vv") == 0) 1041 verbose = 2; 1042 else if (strcmp(modif, "v") == 0) 1043 verbose = 1; 1044 else 1045 verbose = 0; 1046 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) { 1047 if (lapics[apic_id].la_present == 0) 1048 continue; 1049 db_printf("Interrupts bound to lapic %u\n", apic_id); 1050 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1051 irq = lapics[apic_id].la_ioint_irqs[i]; 1052 if (irq == -1 || irq == IRQ_SYSCALL) 1053 continue; 1054 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1055 if (irq == IRQ_TIMER) 1056 db_printf("lapic timer\n"); 1057 else if (irq < NUM_IO_INTS) { 1058 isrc = intr_lookup_source(irq); 1059 if (isrc == NULL || verbose == 0) 1060 db_printf("IRQ %u\n", irq); 1061 else 1062 db_dump_intr_event(isrc->is_event, 1063 verbose == 2); 1064 } else 1065 db_printf("IRQ %u ???\n", irq); 1066 } 1067 } 1068 } 1069 1070 static void 1071 dump_mask(const char *prefix, uint32_t v, int base) 1072 { 1073 int i, first; 1074 1075 first = 1; 1076 for (i = 0; i < 32; i++) 1077 if (v & (1 << i)) { 1078 if (first) { 1079 db_printf("%s:", prefix); 1080 first = 0; 1081 } 1082 db_printf(" %02x", base + i); 1083 } 1084 if (!first) 1085 db_printf("\n"); 1086 } 1087 1088 /* Show info from the lapic regs for this CPU. */ 1089 DB_SHOW_COMMAND(lapic, db_show_lapic) 1090 { 1091 uint32_t v; 1092 1093 db_printf("lapic ID = %d\n", lapic_id()); 1094 v = lapic->version; 1095 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1096 v & 0xf); 1097 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1098 v = lapic->svr; 1099 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1100 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1101 db_printf("TPR = %02x\n", lapic->tpr); 1102 1103 #define dump_field(prefix, index) \ 1104 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1105 index * 32) 1106 1107 db_printf("In-service Interrupts:\n"); 1108 dump_field(isr, 0); 1109 dump_field(isr, 1); 1110 dump_field(isr, 2); 1111 dump_field(isr, 3); 1112 dump_field(isr, 4); 1113 dump_field(isr, 5); 1114 dump_field(isr, 6); 1115 dump_field(isr, 7); 1116 1117 db_printf("TMR Interrupts:\n"); 1118 dump_field(tmr, 0); 1119 dump_field(tmr, 1); 1120 dump_field(tmr, 2); 1121 dump_field(tmr, 3); 1122 dump_field(tmr, 4); 1123 dump_field(tmr, 5); 1124 dump_field(tmr, 6); 1125 dump_field(tmr, 7); 1126 1127 db_printf("IRR Interrupts:\n"); 1128 dump_field(irr, 0); 1129 dump_field(irr, 1); 1130 dump_field(irr, 2); 1131 dump_field(irr, 3); 1132 dump_field(irr, 4); 1133 dump_field(irr, 5); 1134 dump_field(irr, 6); 1135 dump_field(irr, 7); 1136 1137 #undef dump_field 1138 } 1139 #endif 1140 1141 /* 1142 * APIC probing support code. This includes code to manage enumerators. 1143 */ 1144 1145 static SLIST_HEAD(, apic_enumerator) enumerators = 1146 SLIST_HEAD_INITIALIZER(enumerators); 1147 static struct apic_enumerator *best_enum; 1148 1149 void 1150 apic_register_enumerator(struct apic_enumerator *enumerator) 1151 { 1152 #ifdef INVARIANTS 1153 struct apic_enumerator *apic_enum; 1154 1155 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1156 if (apic_enum == enumerator) 1157 panic("%s: Duplicate register of %s", __func__, 1158 enumerator->apic_name); 1159 } 1160 #endif 1161 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1162 } 1163 1164 /* 1165 * Probe the APIC enumerators, enumerate CPUs, and initialize the 1166 * local APIC. 1167 */ 1168 static void 1169 apic_init(void *dummy __unused) 1170 { 1171 struct apic_enumerator *enumerator; 1172 uint64_t apic_base; 1173 int retval, best; 1174 1175 /* We only support built in local APICs. */ 1176 if (!(cpu_feature & CPUID_APIC)) 1177 return; 1178 1179 /* Don't probe if APIC mode is disabled. */ 1180 if (resource_disabled("apic", 0)) 1181 return; 1182 1183 /* First, probe all the enumerators to find the best match. */ 1184 best_enum = NULL; 1185 best = 0; 1186 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1187 retval = enumerator->apic_probe(); 1188 if (retval > 0) 1189 continue; 1190 if (best_enum == NULL || best < retval) { 1191 best_enum = enumerator; 1192 best = retval; 1193 } 1194 } 1195 if (best_enum == NULL) { 1196 if (bootverbose) 1197 printf("APIC: Could not find any APICs.\n"); 1198 return; 1199 } 1200 1201 if (bootverbose) 1202 printf("APIC: Using the %s enumerator.\n", 1203 best_enum->apic_name); 1204 1205 /* 1206 * To work around an errata, we disable the local APIC on some 1207 * CPUs during early startup. We need to turn the local APIC back 1208 * on on such CPUs now. 1209 */ 1210 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1211 (cpu_id & 0xff0) == 0x610) { 1212 apic_base = rdmsr(MSR_APICBASE); 1213 apic_base |= APICBASE_ENABLED; 1214 wrmsr(MSR_APICBASE, apic_base); 1215 } 1216 1217 /* Second, probe the CPU's in the system. */ 1218 retval = best_enum->apic_probe_cpus(); 1219 if (retval != 0) 1220 printf("%s: Failed to probe CPUs: returned %d\n", 1221 best_enum->apic_name, retval); 1222 1223 /* Third, initialize the local APIC. */ 1224 retval = best_enum->apic_setup_local(); 1225 if (retval != 0) 1226 printf("%s: Failed to setup the local APIC: returned %d\n", 1227 best_enum->apic_name, retval); 1228 } 1229 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1230 1231 /* 1232 * Setup the I/O APICs. 1233 */ 1234 static void 1235 apic_setup_io(void *dummy __unused) 1236 { 1237 int retval; 1238 1239 if (best_enum == NULL) 1240 return; 1241 retval = best_enum->apic_setup_io(); 1242 if (retval != 0) 1243 printf("%s: Failed to setup I/O APICs: returned %d\n", 1244 best_enum->apic_name, retval); 1245 1246 #ifdef XEN 1247 return; 1248 #endif 1249 /* 1250 * Finish setting up the local APIC on the BSP once we know how to 1251 * properly program the LINT pins. 1252 */ 1253 lapic_setup(1); 1254 intr_register_pic(&lapic_pic); 1255 if (bootverbose) 1256 lapic_dump("BSP"); 1257 1258 /* Enable the MSI "pic". */ 1259 msi_init(); 1260 } 1261 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1262 1263 #ifdef SMP 1264 /* 1265 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1266 * private to the sys/i386 code. The public interface for the rest of the 1267 * kernel is defined in mp_machdep.c. 1268 */ 1269 int 1270 lapic_ipi_wait(int delay) 1271 { 1272 int x, incr; 1273 1274 /* 1275 * Wait delay loops for IPI to be sent. This is highly bogus 1276 * since this is sensitive to CPU clock speed. If delay is 1277 * -1, we wait forever. 1278 */ 1279 if (delay == -1) { 1280 incr = 0; 1281 delay = 1; 1282 } else 1283 incr = 1; 1284 for (x = 0; x < delay; x += incr) { 1285 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1286 return (1); 1287 ia32_pause(); 1288 } 1289 return (0); 1290 } 1291 1292 void 1293 lapic_ipi_raw(register_t icrlo, u_int dest) 1294 { 1295 register_t value, eflags; 1296 1297 /* XXX: Need more sanity checking of icrlo? */ 1298 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1299 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1300 ("%s: invalid dest field", __func__)); 1301 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1302 ("%s: reserved bits set in ICR LO register", __func__)); 1303 1304 /* Set destination in ICR HI register if it is being used. */ 1305 eflags = intr_disable(); 1306 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1307 value = lapic->icr_hi; 1308 value &= ~APIC_ID_MASK; 1309 value |= dest << APIC_ID_SHIFT; 1310 lapic->icr_hi = value; 1311 } 1312 1313 /* Program the contents of the IPI and dispatch it. */ 1314 value = lapic->icr_lo; 1315 value &= APIC_ICRLO_RESV_MASK; 1316 value |= icrlo; 1317 lapic->icr_lo = value; 1318 intr_restore(eflags); 1319 } 1320 1321 #define BEFORE_SPIN 1000000 1322 #ifdef DETECT_DEADLOCK 1323 #define AFTER_SPIN 1000 1324 #endif 1325 1326 void 1327 lapic_ipi_vectored(u_int vector, int dest) 1328 { 1329 register_t icrlo, destfield; 1330 1331 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1332 ("%s: invalid vector %d", __func__, vector)); 1333 1334 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE; 1335 1336 /* 1337 * IPI_STOP_HARD is just a "fake" vector used to send a NMI. 1338 * Use special rules regard NMI if passed, otherwise specify 1339 * the vector. 1340 */ 1341 if (vector == IPI_STOP_HARD) 1342 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT; 1343 else 1344 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT; 1345 destfield = 0; 1346 switch (dest) { 1347 case APIC_IPI_DEST_SELF: 1348 icrlo |= APIC_DEST_SELF; 1349 break; 1350 case APIC_IPI_DEST_ALL: 1351 icrlo |= APIC_DEST_ALLISELF; 1352 break; 1353 case APIC_IPI_DEST_OTHERS: 1354 icrlo |= APIC_DEST_ALLESELF; 1355 break; 1356 default: 1357 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1358 ("%s: invalid destination 0x%x", __func__, dest)); 1359 destfield = dest; 1360 } 1361 1362 /* Wait for an earlier IPI to finish. */ 1363 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1364 if (panicstr != NULL) 1365 return; 1366 else 1367 panic("APIC: Previous IPI is stuck"); 1368 } 1369 1370 lapic_ipi_raw(icrlo, destfield); 1371 1372 #ifdef DETECT_DEADLOCK 1373 /* Wait for IPI to be delivered. */ 1374 if (!lapic_ipi_wait(AFTER_SPIN)) { 1375 #ifdef needsattention 1376 /* 1377 * XXX FIXME: 1378 * 1379 * The above function waits for the message to actually be 1380 * delivered. It breaks out after an arbitrary timeout 1381 * since the message should eventually be delivered (at 1382 * least in theory) and that if it wasn't we would catch 1383 * the failure with the check above when the next IPI is 1384 * sent. 1385 * 1386 * We could skip this wait entirely, EXCEPT it probably 1387 * protects us from other routines that assume that the 1388 * message was delivered and acted upon when this function 1389 * returns. 1390 */ 1391 printf("APIC: IPI might be stuck\n"); 1392 #else /* !needsattention */ 1393 /* Wait until mesage is sent without a timeout. */ 1394 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1395 ia32_pause(); 1396 #endif /* needsattention */ 1397 } 1398 #endif /* DETECT_DEADLOCK */ 1399 } 1400 #endif /* SMP */
Cache object: 560f69c3254aab9ffbd086b1bd652520
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]