Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/local_apic.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/8.1/sys/i386/i386/local_apic.c 206598 2010-04-14 15:00:46Z jhb $"); 36 37 #include "opt_atpic.h" 38 #include "opt_hwpmc_hooks.h" 39 #include "opt_kdtrace.h" 40 41 #include "opt_ddb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/mutex.h> 49 #include <sys/pcpu.h> 50 #include <sys/proc.h> 51 #include <sys/sched.h> 52 #include <sys/smp.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <machine/apicreg.h> 58 #include <machine/cpu.h> 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/intr_machdep.h> 62 #include <machine/apicvar.h> 63 #include <machine/md_var.h> 64 #include <machine/smp.h> 65 #include <machine/specialreg.h> 66 67 #ifdef DDB 68 #include <sys/interrupt.h> 69 #include <ddb/ddb.h> 70 #endif 71 72 #ifdef KDTRACE_HOOKS 73 #include <sys/dtrace_bsd.h> 74 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 75 #endif 76 77 /* Sanity checks on IDT vectors. */ 78 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 79 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 80 CTASSERT(APIC_LOCAL_INTS == 240); 81 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 82 83 /* Magic IRQ values for the timer and syscalls. */ 84 #define IRQ_TIMER (NUM_IO_INTS + 1) 85 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 86 87 /* 88 * Support for local APICs. Local APICs manage interrupts on each 89 * individual processor as opposed to I/O APICs which receive interrupts 90 * from I/O devices and then forward them on to the local APICs. 91 * 92 * Local APICs can also send interrupts to each other thus providing the 93 * mechanism for IPIs. 94 */ 95 96 struct lvt { 97 u_int lvt_edgetrigger:1; 98 u_int lvt_activehi:1; 99 u_int lvt_masked:1; 100 u_int lvt_active:1; 101 u_int lvt_mode:16; 102 u_int lvt_vector:8; 103 }; 104 105 struct lapic { 106 struct lvt la_lvts[LVT_MAX + 1]; 107 u_int la_id:8; 108 u_int la_cluster:4; 109 u_int la_cluster_id:2; 110 u_int la_present:1; 111 u_long *la_timer_count; 112 u_long la_hard_ticks; 113 u_long la_stat_ticks; 114 u_long la_prof_ticks; 115 /* Include IDT_SYSCALL to make indexing easier. */ 116 int la_ioint_irqs[APIC_NUM_IOINTS + 1]; 117 } static lapics[MAX_APIC_ID + 1]; 118 119 /* Global defaults for local APIC LVT entries. */ 120 static struct lvt lvts[LVT_MAX + 1] = { 121 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 122 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 124 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 125 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 126 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 127 }; 128 129 static inthand_t *ioint_handlers[] = { 130 NULL, /* 0 - 31 */ 131 IDTVEC(apic_isr1), /* 32 - 63 */ 132 IDTVEC(apic_isr2), /* 64 - 95 */ 133 IDTVEC(apic_isr3), /* 96 - 127 */ 134 IDTVEC(apic_isr4), /* 128 - 159 */ 135 IDTVEC(apic_isr5), /* 160 - 191 */ 136 IDTVEC(apic_isr6), /* 192 - 223 */ 137 IDTVEC(apic_isr7), /* 224 - 255 */ 138 }; 139 140 141 static u_int32_t lapic_timer_divisors[] = { 142 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 143 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 144 }; 145 146 extern inthand_t IDTVEC(rsvd); 147 148 volatile lapic_t *lapic; 149 vm_paddr_t lapic_paddr; 150 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 151 static enum lapic_clock clockcoverage; 152 153 static void lapic_enable(void); 154 static void lapic_resume(struct pic *pic); 155 static void lapic_timer_enable_intr(void); 156 static void lapic_timer_oneshot(u_int count); 157 static void lapic_timer_periodic(u_int count); 158 static void lapic_timer_set_divisor(u_int divisor); 159 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 160 161 struct pic lapic_pic = { .pic_resume = lapic_resume }; 162 163 static uint32_t 164 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 165 { 166 struct lvt *lvt; 167 168 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 169 if (la->la_lvts[pin].lvt_active) 170 lvt = &la->la_lvts[pin]; 171 else 172 lvt = &lvts[pin]; 173 174 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 175 APIC_LVT_VECTOR); 176 if (lvt->lvt_edgetrigger == 0) 177 value |= APIC_LVT_TM; 178 if (lvt->lvt_activehi == 0) 179 value |= APIC_LVT_IIPP_INTALO; 180 if (lvt->lvt_masked) 181 value |= APIC_LVT_M; 182 value |= lvt->lvt_mode; 183 switch (lvt->lvt_mode) { 184 case APIC_LVT_DM_NMI: 185 case APIC_LVT_DM_SMI: 186 case APIC_LVT_DM_INIT: 187 case APIC_LVT_DM_EXTINT: 188 if (!lvt->lvt_edgetrigger) { 189 printf("lapic%u: Forcing LINT%u to edge trigger\n", 190 la->la_id, pin); 191 value |= APIC_LVT_TM; 192 } 193 /* Use a vector of 0. */ 194 break; 195 case APIC_LVT_DM_FIXED: 196 value |= lvt->lvt_vector; 197 break; 198 default: 199 panic("bad APIC LVT delivery mode: %#x\n", value); 200 } 201 return (value); 202 } 203 204 /* 205 * Map the local APIC and setup necessary interrupt vectors. 206 */ 207 void 208 lapic_init(vm_paddr_t addr) 209 { 210 211 /* Map the local APIC and setup the spurious interrupt handler. */ 212 KASSERT(trunc_page(addr) == addr, 213 ("local APIC not aligned on a page boundary")); 214 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 215 lapic_paddr = addr; 216 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 217 GSEL(GCODE_SEL, SEL_KPL)); 218 219 /* Perform basic initialization of the BSP's local APIC. */ 220 lapic_enable(); 221 222 /* Set BSP's per-CPU local APIC ID. */ 223 PCPU_SET(apic_id, lapic_id()); 224 225 /* Local APIC timer interrupt. */ 226 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 227 GSEL(GCODE_SEL, SEL_KPL)); 228 229 /* Local APIC error interrupt. */ 230 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_SYS386IGT, SEL_KPL, 231 GSEL(GCODE_SEL, SEL_KPL)); 232 233 /* XXX: Thermal interrupt */ 234 } 235 236 /* 237 * Create a local APIC instance. 238 */ 239 void 240 lapic_create(u_int apic_id, int boot_cpu) 241 { 242 int i; 243 244 if (apic_id > MAX_APIC_ID) { 245 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 246 if (boot_cpu) 247 panic("Can't ignore BSP"); 248 return; 249 } 250 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 251 apic_id)); 252 253 /* 254 * Assume no local LVT overrides and a cluster of 0 and 255 * intra-cluster ID of 0. 256 */ 257 lapics[apic_id].la_present = 1; 258 lapics[apic_id].la_id = apic_id; 259 for (i = 0; i < LVT_MAX; i++) { 260 lapics[apic_id].la_lvts[i] = lvts[i]; 261 lapics[apic_id].la_lvts[i].lvt_active = 0; 262 } 263 for (i = 0; i <= APIC_NUM_IOINTS; i++) 264 lapics[apic_id].la_ioint_irqs[i] = -1; 265 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 266 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = 267 IRQ_TIMER; 268 269 #ifdef SMP 270 cpu_add(apic_id, boot_cpu); 271 #endif 272 } 273 274 /* 275 * Dump contents of local APIC registers 276 */ 277 void 278 lapic_dump(const char* str) 279 { 280 281 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 282 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 283 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 284 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 285 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 286 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pmc: 0x%08x\n", 287 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 288 lapic->lvt_pcint); 289 } 290 291 void 292 lapic_setup(int boot) 293 { 294 struct lapic *la; 295 u_int32_t maxlvt; 296 register_t eflags; 297 char buf[MAXCOMLEN + 1]; 298 299 la = &lapics[lapic_id()]; 300 KASSERT(la->la_present, ("missing APIC structure")); 301 eflags = intr_disable(); 302 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 303 304 /* Initialize the TPR to allow all interrupts. */ 305 lapic_set_tpr(0); 306 307 /* Setup spurious vector and enable the local APIC. */ 308 lapic_enable(); 309 310 /* Program LINT[01] LVT entries. */ 311 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 312 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 313 314 /* Program the PMC LVT entry if present. */ 315 if (maxlvt >= LVT_PMC) 316 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 317 318 /* Program timer LVT and setup handler. */ 319 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 320 if (boot) { 321 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 322 intrcnt_add(buf, &la->la_timer_count); 323 } 324 325 /* We don't setup the timer during boot on the BSP until later. */ 326 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) { 327 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 328 lapic_id())); 329 lapic_timer_set_divisor(lapic_timer_divisor); 330 lapic_timer_periodic(lapic_timer_period); 331 lapic_timer_enable_intr(); 332 } 333 334 /* Program error LVT and clear any existing errors. */ 335 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error); 336 lapic->esr = 0; 337 338 /* XXX: Thermal LVT */ 339 340 intr_restore(eflags); 341 } 342 343 void 344 lapic_reenable_pmc(void) 345 { 346 #ifdef HWPMC_HOOKS 347 uint32_t value; 348 349 value = lapic->lvt_pcint; 350 value &= ~APIC_LVT_M; 351 lapic->lvt_pcint = value; 352 #endif 353 } 354 355 #ifdef HWPMC_HOOKS 356 static void 357 lapic_update_pmc(void *dummy) 358 { 359 struct lapic *la; 360 361 la = &lapics[lapic_id()]; 362 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 363 } 364 #endif 365 366 int 367 lapic_enable_pmc(void) 368 { 369 #ifdef HWPMC_HOOKS 370 u_int32_t maxlvt; 371 372 /* Fail if the local APIC is not present. */ 373 if (lapic == NULL) 374 return (0); 375 376 /* Fail if the PMC LVT is not present. */ 377 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 378 if (maxlvt < LVT_PMC) 379 return (0); 380 381 lvts[LVT_PMC].lvt_masked = 0; 382 383 #ifdef SMP 384 /* 385 * If hwpmc was loaded at boot time then the APs may not be 386 * started yet. In that case, don't forward the request to 387 * them as they will program the lvt when they start. 388 */ 389 if (smp_started) 390 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 391 else 392 #endif 393 lapic_update_pmc(NULL); 394 return (1); 395 #else 396 return (0); 397 #endif 398 } 399 400 void 401 lapic_disable_pmc(void) 402 { 403 #ifdef HWPMC_HOOKS 404 u_int32_t maxlvt; 405 406 /* Fail if the local APIC is not present. */ 407 if (lapic == NULL) 408 return; 409 410 /* Fail if the PMC LVT is not present. */ 411 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 412 if (maxlvt < LVT_PMC) 413 return; 414 415 lvts[LVT_PMC].lvt_masked = 1; 416 417 #ifdef SMP 418 /* The APs should always be started when hwpmc is unloaded. */ 419 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 420 #endif 421 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 422 #endif 423 } 424 425 /* 426 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 427 * that it can drive hardclock, statclock, and profclock. 428 */ 429 enum lapic_clock 430 lapic_setup_clock(enum lapic_clock srcsdes) 431 { 432 u_long value; 433 int i; 434 435 /* lapic_setup_clock() should not be called with LAPIC_CLOCK_NONE. */ 436 MPASS(srcsdes != LAPIC_CLOCK_NONE); 437 438 /* Can't drive the timer without a local APIC. */ 439 if (lapic == NULL || 440 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) { 441 clockcoverage = LAPIC_CLOCK_NONE; 442 return (clockcoverage); 443 } 444 445 /* Start off with a divisor of 2 (power on reset default). */ 446 lapic_timer_divisor = 2; 447 448 /* Try to calibrate the local APIC timer. */ 449 do { 450 lapic_timer_set_divisor(lapic_timer_divisor); 451 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 452 DELAY(2000000); 453 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 454 if (value != APIC_TIMER_MAX_COUNT) 455 break; 456 lapic_timer_divisor <<= 1; 457 } while (lapic_timer_divisor <= 128); 458 if (lapic_timer_divisor > 128) 459 panic("lapic: Divisor too big"); 460 value /= 2; 461 if (bootverbose) 462 printf("lapic: Divisor %lu, Frequency %lu Hz\n", 463 lapic_timer_divisor, value); 464 465 /* 466 * We want to run stathz in the neighborhood of 128hz. We would 467 * like profhz to run as often as possible, so we let it run on 468 * each clock tick. We try to honor the requested 'hz' value as 469 * much as possible. 470 * 471 * If 'hz' is above 1500, then we just let the lapic timer 472 * (and profhz) run at hz. If 'hz' is below 1500 but above 473 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 474 * is below 750 then we let the lapic timer run at 4 * 'hz'. 475 * 476 * Please note that stathz and profhz are set only if all the 477 * clocks are handled through the local APIC. 478 */ 479 if (srcsdes == LAPIC_CLOCK_ALL) { 480 if (hz >= 1500) 481 lapic_timer_hz = hz; 482 else if (hz >= 750) 483 lapic_timer_hz = hz * 2; 484 else 485 lapic_timer_hz = hz * 4; 486 } else 487 lapic_timer_hz = hz; 488 lapic_timer_period = value / lapic_timer_hz; 489 if (srcsdes == LAPIC_CLOCK_ALL) { 490 if (lapic_timer_hz < 128) 491 stathz = lapic_timer_hz; 492 else 493 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 494 profhz = lapic_timer_hz; 495 } 496 497 /* 498 * Start up the timer on the BSP. The APs will kick off their 499 * timer during lapic_setup(). 500 */ 501 lapic_timer_periodic(lapic_timer_period); 502 lapic_timer_enable_intr(); 503 clockcoverage = srcsdes; 504 return (srcsdes); 505 } 506 507 void 508 lapic_disable(void) 509 { 510 uint32_t value; 511 512 /* Software disable the local APIC. */ 513 value = lapic->svr; 514 value &= ~APIC_SVR_SWEN; 515 lapic->svr = value; 516 } 517 518 static void 519 lapic_enable(void) 520 { 521 u_int32_t value; 522 523 /* Program the spurious vector to enable the local APIC. */ 524 value = lapic->svr; 525 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 526 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 527 lapic->svr = value; 528 } 529 530 /* Reset the local APIC on the BSP during resume. */ 531 static void 532 lapic_resume(struct pic *pic) 533 { 534 535 lapic_setup(0); 536 } 537 538 int 539 lapic_id(void) 540 { 541 542 KASSERT(lapic != NULL, ("local APIC is not mapped")); 543 return (lapic->id >> APIC_ID_SHIFT); 544 } 545 546 int 547 lapic_intr_pending(u_int vector) 548 { 549 volatile u_int32_t *irr; 550 551 /* 552 * The IRR registers are an array of 128-bit registers each of 553 * which only describes 32 interrupts in the low 32 bits.. Thus, 554 * we divide the vector by 32 to get the 128-bit index. We then 555 * multiply that index by 4 to get the equivalent index from 556 * treating the IRR as an array of 32-bit registers. Finally, we 557 * modulus the vector by 32 to determine the individual bit to 558 * test. 559 */ 560 irr = &lapic->irr0; 561 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 562 } 563 564 void 565 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 566 { 567 struct lapic *la; 568 569 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 570 __func__, apic_id)); 571 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 572 __func__, cluster)); 573 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 574 ("%s: intra cluster id %u too big", __func__, cluster_id)); 575 la = &lapics[apic_id]; 576 la->la_cluster = cluster; 577 la->la_cluster_id = cluster_id; 578 } 579 580 int 581 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 582 { 583 584 if (pin > LVT_MAX) 585 return (EINVAL); 586 if (apic_id == APIC_ID_ALL) { 587 lvts[pin].lvt_masked = masked; 588 if (bootverbose) 589 printf("lapic:"); 590 } else { 591 KASSERT(lapics[apic_id].la_present, 592 ("%s: missing APIC %u", __func__, apic_id)); 593 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 594 lapics[apic_id].la_lvts[pin].lvt_active = 1; 595 if (bootverbose) 596 printf("lapic%u:", apic_id); 597 } 598 if (bootverbose) 599 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 600 return (0); 601 } 602 603 int 604 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 605 { 606 struct lvt *lvt; 607 608 if (pin > LVT_MAX) 609 return (EINVAL); 610 if (apic_id == APIC_ID_ALL) { 611 lvt = &lvts[pin]; 612 if (bootverbose) 613 printf("lapic:"); 614 } else { 615 KASSERT(lapics[apic_id].la_present, 616 ("%s: missing APIC %u", __func__, apic_id)); 617 lvt = &lapics[apic_id].la_lvts[pin]; 618 lvt->lvt_active = 1; 619 if (bootverbose) 620 printf("lapic%u:", apic_id); 621 } 622 lvt->lvt_mode = mode; 623 switch (mode) { 624 case APIC_LVT_DM_NMI: 625 case APIC_LVT_DM_SMI: 626 case APIC_LVT_DM_INIT: 627 case APIC_LVT_DM_EXTINT: 628 lvt->lvt_edgetrigger = 1; 629 lvt->lvt_activehi = 1; 630 if (mode == APIC_LVT_DM_EXTINT) 631 lvt->lvt_masked = 1; 632 else 633 lvt->lvt_masked = 0; 634 break; 635 default: 636 panic("Unsupported delivery mode: 0x%x\n", mode); 637 } 638 if (bootverbose) { 639 printf(" Routing "); 640 switch (mode) { 641 case APIC_LVT_DM_NMI: 642 printf("NMI"); 643 break; 644 case APIC_LVT_DM_SMI: 645 printf("SMI"); 646 break; 647 case APIC_LVT_DM_INIT: 648 printf("INIT"); 649 break; 650 case APIC_LVT_DM_EXTINT: 651 printf("ExtINT"); 652 break; 653 } 654 printf(" -> LINT%u\n", pin); 655 } 656 return (0); 657 } 658 659 int 660 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 661 { 662 663 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 664 return (EINVAL); 665 if (apic_id == APIC_ID_ALL) { 666 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 667 if (bootverbose) 668 printf("lapic:"); 669 } else { 670 KASSERT(lapics[apic_id].la_present, 671 ("%s: missing APIC %u", __func__, apic_id)); 672 lapics[apic_id].la_lvts[pin].lvt_active = 1; 673 lapics[apic_id].la_lvts[pin].lvt_activehi = 674 (pol == INTR_POLARITY_HIGH); 675 if (bootverbose) 676 printf("lapic%u:", apic_id); 677 } 678 if (bootverbose) 679 printf(" LINT%u polarity: %s\n", pin, 680 pol == INTR_POLARITY_HIGH ? "high" : "low"); 681 return (0); 682 } 683 684 int 685 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 686 { 687 688 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 689 return (EINVAL); 690 if (apic_id == APIC_ID_ALL) { 691 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 692 if (bootverbose) 693 printf("lapic:"); 694 } else { 695 KASSERT(lapics[apic_id].la_present, 696 ("%s: missing APIC %u", __func__, apic_id)); 697 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 698 (trigger == INTR_TRIGGER_EDGE); 699 lapics[apic_id].la_lvts[pin].lvt_active = 1; 700 if (bootverbose) 701 printf("lapic%u:", apic_id); 702 } 703 if (bootverbose) 704 printf(" LINT%u trigger: %s\n", pin, 705 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 706 return (0); 707 } 708 709 /* 710 * Adjust the TPR of the current CPU so that it blocks all interrupts below 711 * the passed in vector. 712 */ 713 void 714 lapic_set_tpr(u_int vector) 715 { 716 #ifdef CHEAP_TPR 717 lapic->tpr = vector; 718 #else 719 u_int32_t tpr; 720 721 tpr = lapic->tpr & ~APIC_TPR_PRIO; 722 tpr |= vector; 723 lapic->tpr = tpr; 724 #endif 725 } 726 727 void 728 lapic_eoi(void) 729 { 730 731 lapic->eoi = 0; 732 } 733 734 void 735 lapic_handle_intr(int vector, struct trapframe *frame) 736 { 737 struct intsrc *isrc; 738 739 if (vector == -1) 740 panic("Couldn't get vector from ISR!"); 741 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id), 742 vector)); 743 intr_execute_handlers(isrc, frame); 744 } 745 746 void 747 lapic_handle_timer(struct trapframe *frame) 748 { 749 struct lapic *la; 750 751 /* Send EOI first thing. */ 752 lapic_eoi(); 753 754 #if defined(SMP) && !defined(SCHED_ULE) 755 /* 756 * Don't do any accounting for the disabled HTT cores, since it 757 * will provide misleading numbers for the userland. 758 * 759 * No locking is necessary here, since even if we loose the race 760 * when hlt_cpus_mask changes it is not a big deal, really. 761 * 762 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 763 * and unlike other schedulers it actually schedules threads to 764 * those CPUs. 765 */ 766 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 767 return; 768 #endif 769 770 /* Look up our local APIC structure for the tick counters. */ 771 la = &lapics[PCPU_GET(apic_id)]; 772 (*la->la_timer_count)++; 773 critical_enter(); 774 775 #ifdef KDTRACE_HOOKS 776 /* 777 * If the DTrace hooks are configured and a callback function 778 * has been registered, then call it to process the high speed 779 * timers. 780 */ 781 int cpu = PCPU_GET(cpuid); 782 if (lapic_cyclic_clock_func[cpu] != NULL) 783 (*lapic_cyclic_clock_func[cpu])(frame); 784 #endif 785 786 /* Fire hardclock at hz. */ 787 la->la_hard_ticks += hz; 788 if (la->la_hard_ticks >= lapic_timer_hz) { 789 la->la_hard_ticks -= lapic_timer_hz; 790 if (PCPU_GET(cpuid) == 0) 791 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 792 else 793 hardclock_cpu(TRAPF_USERMODE(frame)); 794 } 795 if (clockcoverage == LAPIC_CLOCK_ALL) { 796 797 /* Fire statclock at stathz. */ 798 la->la_stat_ticks += stathz; 799 if (la->la_stat_ticks >= lapic_timer_hz) { 800 la->la_stat_ticks -= lapic_timer_hz; 801 statclock(TRAPF_USERMODE(frame)); 802 } 803 804 /* Fire profclock at profhz, but only when needed. */ 805 la->la_prof_ticks += profhz; 806 if (la->la_prof_ticks >= lapic_timer_hz) { 807 la->la_prof_ticks -= lapic_timer_hz; 808 if (profprocs != 0) 809 profclock(TRAPF_USERMODE(frame), 810 TRAPF_PC(frame)); 811 } 812 } 813 critical_exit(); 814 } 815 816 static void 817 lapic_timer_set_divisor(u_int divisor) 818 { 819 820 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 821 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 822 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 823 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 824 } 825 826 static void 827 lapic_timer_oneshot(u_int count) 828 { 829 u_int32_t value; 830 831 value = lapic->lvt_timer; 832 value &= ~APIC_LVTT_TM; 833 value |= APIC_LVTT_TM_ONE_SHOT; 834 lapic->lvt_timer = value; 835 lapic->icr_timer = count; 836 } 837 838 static void 839 lapic_timer_periodic(u_int count) 840 { 841 u_int32_t value; 842 843 value = lapic->lvt_timer; 844 value &= ~APIC_LVTT_TM; 845 value |= APIC_LVTT_TM_PERIODIC; 846 lapic->lvt_timer = value; 847 lapic->icr_timer = count; 848 } 849 850 static void 851 lapic_timer_enable_intr(void) 852 { 853 u_int32_t value; 854 855 value = lapic->lvt_timer; 856 value &= ~APIC_LVT_M; 857 lapic->lvt_timer = value; 858 } 859 860 void 861 lapic_handle_error(void) 862 { 863 u_int32_t esr; 864 865 /* 866 * Read the contents of the error status register. Write to 867 * the register first before reading from it to force the APIC 868 * to update its value to indicate any errors that have 869 * occurred since the previous write to the register. 870 */ 871 lapic->esr = 0; 872 esr = lapic->esr; 873 874 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr); 875 lapic_eoi(); 876 } 877 878 u_int 879 apic_cpuid(u_int apic_id) 880 { 881 #ifdef SMP 882 return apic_cpuids[apic_id]; 883 #else 884 return 0; 885 #endif 886 } 887 888 /* Request a free IDT vector to be used by the specified IRQ. */ 889 u_int 890 apic_alloc_vector(u_int apic_id, u_int irq) 891 { 892 u_int vector; 893 894 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 895 896 /* 897 * Search for a free vector. Currently we just use a very simple 898 * algorithm to find the first free vector. 899 */ 900 mtx_lock_spin(&icu_lock); 901 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 902 if (lapics[apic_id].la_ioint_irqs[vector] != -1) 903 continue; 904 lapics[apic_id].la_ioint_irqs[vector] = irq; 905 mtx_unlock_spin(&icu_lock); 906 return (vector + APIC_IO_INTS); 907 } 908 mtx_unlock_spin(&icu_lock); 909 return (0); 910 } 911 912 /* 913 * Request 'count' free contiguous IDT vectors to be used by 'count' 914 * IRQs. 'count' must be a power of two and the vectors will be 915 * aligned on a boundary of 'align'. If the request cannot be 916 * satisfied, 0 is returned. 917 */ 918 u_int 919 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 920 { 921 u_int first, run, vector; 922 923 KASSERT(powerof2(count), ("bad count")); 924 KASSERT(powerof2(align), ("bad align")); 925 KASSERT(align >= count, ("align < count")); 926 #ifdef INVARIANTS 927 for (run = 0; run < count; run++) 928 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 929 irqs[run], run)); 930 #endif 931 932 /* 933 * Search for 'count' free vectors. As with apic_alloc_vector(), 934 * this just uses a simple first fit algorithm. 935 */ 936 run = 0; 937 first = 0; 938 mtx_lock_spin(&icu_lock); 939 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 940 941 /* Vector is in use, end run. */ 942 if (lapics[apic_id].la_ioint_irqs[vector] != -1) { 943 run = 0; 944 first = 0; 945 continue; 946 } 947 948 /* Start a new run if run == 0 and vector is aligned. */ 949 if (run == 0) { 950 if ((vector & (align - 1)) != 0) 951 continue; 952 first = vector; 953 } 954 run++; 955 956 /* Keep looping if the run isn't long enough yet. */ 957 if (run < count) 958 continue; 959 960 /* Found a run, assign IRQs and return the first vector. */ 961 for (vector = 0; vector < count; vector++) 962 lapics[apic_id].la_ioint_irqs[first + vector] = 963 irqs[vector]; 964 mtx_unlock_spin(&icu_lock); 965 return (first + APIC_IO_INTS); 966 } 967 mtx_unlock_spin(&icu_lock); 968 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 969 return (0); 970 } 971 972 /* 973 * Enable a vector for a particular apic_id. Since all lapics share idt 974 * entries and ioint_handlers this enables the vector on all lapics. lapics 975 * which do not have the vector configured would report spurious interrupts 976 * should it fire. 977 */ 978 void 979 apic_enable_vector(u_int apic_id, u_int vector) 980 { 981 982 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 983 KASSERT(ioint_handlers[vector / 32] != NULL, 984 ("No ISR handler for vector %u", vector)); 985 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 986 GSEL(GCODE_SEL, SEL_KPL)); 987 } 988 989 void 990 apic_disable_vector(u_int apic_id, u_int vector) 991 { 992 993 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 994 KASSERT(ioint_handlers[vector / 32] != NULL, 995 ("No ISR handler for vector %u", vector)); 996 #ifdef notyet 997 /* 998 * We can not currently clear the idt entry because other cpus 999 * may have a valid vector at this offset. 1000 */ 1001 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 1002 GSEL(GCODE_SEL, SEL_KPL)); 1003 #endif 1004 } 1005 1006 /* Release an APIC vector when it's no longer in use. */ 1007 void 1008 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 1009 { 1010 struct thread *td; 1011 1012 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1013 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1014 ("Vector %u does not map to an IRQ line", vector)); 1015 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 1016 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] == 1017 irq, ("IRQ mismatch")); 1018 1019 /* 1020 * Bind us to the cpu that owned the vector before freeing it so 1021 * we don't lose an interrupt delivery race. 1022 */ 1023 td = curthread; 1024 if (!rebooting) { 1025 thread_lock(td); 1026 if (sched_is_bound(td)) 1027 panic("apic_free_vector: Thread already bound.\n"); 1028 sched_bind(td, apic_cpuid(apic_id)); 1029 thread_unlock(td); 1030 } 1031 mtx_lock_spin(&icu_lock); 1032 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1; 1033 mtx_unlock_spin(&icu_lock); 1034 if (!rebooting) { 1035 thread_lock(td); 1036 sched_unbind(td); 1037 thread_unlock(td); 1038 } 1039 } 1040 1041 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1042 u_int 1043 apic_idt_to_irq(u_int apic_id, u_int vector) 1044 { 1045 int irq; 1046 1047 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1048 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1049 ("Vector %u does not map to an IRQ line", vector)); 1050 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS]; 1051 if (irq < 0) 1052 irq = 0; 1053 return (irq); 1054 } 1055 1056 #ifdef DDB 1057 /* 1058 * Dump data about APIC IDT vector mappings. 1059 */ 1060 DB_SHOW_COMMAND(apic, db_show_apic) 1061 { 1062 struct intsrc *isrc; 1063 int i, verbose; 1064 u_int apic_id; 1065 u_int irq; 1066 1067 if (strcmp(modif, "vv") == 0) 1068 verbose = 2; 1069 else if (strcmp(modif, "v") == 0) 1070 verbose = 1; 1071 else 1072 verbose = 0; 1073 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) { 1074 if (lapics[apic_id].la_present == 0) 1075 continue; 1076 db_printf("Interrupts bound to lapic %u\n", apic_id); 1077 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1078 irq = lapics[apic_id].la_ioint_irqs[i]; 1079 if (irq == -1 || irq == IRQ_SYSCALL) 1080 continue; 1081 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1082 if (irq == IRQ_TIMER) 1083 db_printf("lapic timer\n"); 1084 else if (irq < NUM_IO_INTS) { 1085 isrc = intr_lookup_source(irq); 1086 if (isrc == NULL || verbose == 0) 1087 db_printf("IRQ %u\n", irq); 1088 else 1089 db_dump_intr_event(isrc->is_event, 1090 verbose == 2); 1091 } else 1092 db_printf("IRQ %u ???\n", irq); 1093 } 1094 } 1095 } 1096 1097 static void 1098 dump_mask(const char *prefix, uint32_t v, int base) 1099 { 1100 int i, first; 1101 1102 first = 1; 1103 for (i = 0; i < 32; i++) 1104 if (v & (1 << i)) { 1105 if (first) { 1106 db_printf("%s:", prefix); 1107 first = 0; 1108 } 1109 db_printf(" %02x", base + i); 1110 } 1111 if (!first) 1112 db_printf("\n"); 1113 } 1114 1115 /* Show info from the lapic regs for this CPU. */ 1116 DB_SHOW_COMMAND(lapic, db_show_lapic) 1117 { 1118 uint32_t v; 1119 1120 db_printf("lapic ID = %d\n", lapic_id()); 1121 v = lapic->version; 1122 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1123 v & 0xf); 1124 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1125 v = lapic->svr; 1126 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1127 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1128 db_printf("TPR = %02x\n", lapic->tpr); 1129 1130 #define dump_field(prefix, index) \ 1131 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1132 index * 32) 1133 1134 db_printf("In-service Interrupts:\n"); 1135 dump_field(isr, 0); 1136 dump_field(isr, 1); 1137 dump_field(isr, 2); 1138 dump_field(isr, 3); 1139 dump_field(isr, 4); 1140 dump_field(isr, 5); 1141 dump_field(isr, 6); 1142 dump_field(isr, 7); 1143 1144 db_printf("TMR Interrupts:\n"); 1145 dump_field(tmr, 0); 1146 dump_field(tmr, 1); 1147 dump_field(tmr, 2); 1148 dump_field(tmr, 3); 1149 dump_field(tmr, 4); 1150 dump_field(tmr, 5); 1151 dump_field(tmr, 6); 1152 dump_field(tmr, 7); 1153 1154 db_printf("IRR Interrupts:\n"); 1155 dump_field(irr, 0); 1156 dump_field(irr, 1); 1157 dump_field(irr, 2); 1158 dump_field(irr, 3); 1159 dump_field(irr, 4); 1160 dump_field(irr, 5); 1161 dump_field(irr, 6); 1162 dump_field(irr, 7); 1163 1164 #undef dump_field 1165 } 1166 #endif 1167 1168 /* 1169 * APIC probing support code. This includes code to manage enumerators. 1170 */ 1171 1172 static SLIST_HEAD(, apic_enumerator) enumerators = 1173 SLIST_HEAD_INITIALIZER(enumerators); 1174 static struct apic_enumerator *best_enum; 1175 1176 void 1177 apic_register_enumerator(struct apic_enumerator *enumerator) 1178 { 1179 #ifdef INVARIANTS 1180 struct apic_enumerator *apic_enum; 1181 1182 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1183 if (apic_enum == enumerator) 1184 panic("%s: Duplicate register of %s", __func__, 1185 enumerator->apic_name); 1186 } 1187 #endif 1188 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1189 } 1190 1191 /* 1192 * Probe the APIC enumerators, enumerate CPUs, and initialize the 1193 * local APIC. 1194 */ 1195 static void 1196 apic_init(void *dummy __unused) 1197 { 1198 struct apic_enumerator *enumerator; 1199 uint64_t apic_base; 1200 int retval, best; 1201 1202 /* We only support built in local APICs. */ 1203 if (!(cpu_feature & CPUID_APIC)) 1204 return; 1205 1206 /* Don't probe if APIC mode is disabled. */ 1207 if (resource_disabled("apic", 0)) 1208 return; 1209 1210 /* First, probe all the enumerators to find the best match. */ 1211 best_enum = NULL; 1212 best = 0; 1213 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1214 retval = enumerator->apic_probe(); 1215 if (retval > 0) 1216 continue; 1217 if (best_enum == NULL || best < retval) { 1218 best_enum = enumerator; 1219 best = retval; 1220 } 1221 } 1222 if (best_enum == NULL) { 1223 if (bootverbose) 1224 printf("APIC: Could not find any APICs.\n"); 1225 return; 1226 } 1227 1228 if (bootverbose) 1229 printf("APIC: Using the %s enumerator.\n", 1230 best_enum->apic_name); 1231 1232 /* 1233 * To work around an errata, we disable the local APIC on some 1234 * CPUs during early startup. We need to turn the local APIC back 1235 * on on such CPUs now. 1236 */ 1237 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1238 (cpu_id & 0xff0) == 0x610) { 1239 apic_base = rdmsr(MSR_APICBASE); 1240 apic_base |= APICBASE_ENABLED; 1241 wrmsr(MSR_APICBASE, apic_base); 1242 } 1243 1244 /* Second, probe the CPU's in the system. */ 1245 retval = best_enum->apic_probe_cpus(); 1246 if (retval != 0) 1247 printf("%s: Failed to probe CPUs: returned %d\n", 1248 best_enum->apic_name, retval); 1249 1250 /* Third, initialize the local APIC. */ 1251 retval = best_enum->apic_setup_local(); 1252 if (retval != 0) 1253 printf("%s: Failed to setup the local APIC: returned %d\n", 1254 best_enum->apic_name, retval); 1255 } 1256 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1257 1258 /* 1259 * Setup the I/O APICs. 1260 */ 1261 static void 1262 apic_setup_io(void *dummy __unused) 1263 { 1264 int retval; 1265 1266 if (best_enum == NULL) 1267 return; 1268 retval = best_enum->apic_setup_io(); 1269 if (retval != 0) 1270 printf("%s: Failed to setup I/O APICs: returned %d\n", 1271 best_enum->apic_name, retval); 1272 1273 #ifdef XEN 1274 return; 1275 #endif 1276 /* 1277 * Finish setting up the local APIC on the BSP once we know how to 1278 * properly program the LINT pins. 1279 */ 1280 lapic_setup(1); 1281 intr_register_pic(&lapic_pic); 1282 if (bootverbose) 1283 lapic_dump("BSP"); 1284 1285 /* Enable the MSI "pic". */ 1286 msi_init(); 1287 } 1288 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1289 1290 #ifdef SMP 1291 /* 1292 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1293 * private to the sys/i386 code. The public interface for the rest of the 1294 * kernel is defined in mp_machdep.c. 1295 */ 1296 int 1297 lapic_ipi_wait(int delay) 1298 { 1299 int x, incr; 1300 1301 /* 1302 * Wait delay loops for IPI to be sent. This is highly bogus 1303 * since this is sensitive to CPU clock speed. If delay is 1304 * -1, we wait forever. 1305 */ 1306 if (delay == -1) { 1307 incr = 0; 1308 delay = 1; 1309 } else 1310 incr = 1; 1311 for (x = 0; x < delay; x += incr) { 1312 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1313 return (1); 1314 ia32_pause(); 1315 } 1316 return (0); 1317 } 1318 1319 void 1320 lapic_ipi_raw(register_t icrlo, u_int dest) 1321 { 1322 register_t value, eflags; 1323 1324 /* XXX: Need more sanity checking of icrlo? */ 1325 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1326 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1327 ("%s: invalid dest field", __func__)); 1328 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1329 ("%s: reserved bits set in ICR LO register", __func__)); 1330 1331 /* Set destination in ICR HI register if it is being used. */ 1332 eflags = intr_disable(); 1333 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1334 value = lapic->icr_hi; 1335 value &= ~APIC_ID_MASK; 1336 value |= dest << APIC_ID_SHIFT; 1337 lapic->icr_hi = value; 1338 } 1339 1340 /* Program the contents of the IPI and dispatch it. */ 1341 value = lapic->icr_lo; 1342 value &= APIC_ICRLO_RESV_MASK; 1343 value |= icrlo; 1344 lapic->icr_lo = value; 1345 intr_restore(eflags); 1346 } 1347 1348 #define BEFORE_SPIN 1000000 1349 #ifdef DETECT_DEADLOCK 1350 #define AFTER_SPIN 1000 1351 #endif 1352 1353 void 1354 lapic_ipi_vectored(u_int vector, int dest) 1355 { 1356 register_t icrlo, destfield; 1357 1358 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1359 ("%s: invalid vector %d", __func__, vector)); 1360 1361 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE; 1362 1363 /* 1364 * IPI_STOP_HARD is just a "fake" vector used to send a NMI. 1365 * Use special rules regard NMI if passed, otherwise specify 1366 * the vector. 1367 */ 1368 if (vector == IPI_STOP_HARD) 1369 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT; 1370 else 1371 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT; 1372 destfield = 0; 1373 switch (dest) { 1374 case APIC_IPI_DEST_SELF: 1375 icrlo |= APIC_DEST_SELF; 1376 break; 1377 case APIC_IPI_DEST_ALL: 1378 icrlo |= APIC_DEST_ALLISELF; 1379 break; 1380 case APIC_IPI_DEST_OTHERS: 1381 icrlo |= APIC_DEST_ALLESELF; 1382 break; 1383 default: 1384 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1385 ("%s: invalid destination 0x%x", __func__, dest)); 1386 destfield = dest; 1387 } 1388 1389 /* Wait for an earlier IPI to finish. */ 1390 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1391 if (panicstr != NULL) 1392 return; 1393 else 1394 panic("APIC: Previous IPI is stuck"); 1395 } 1396 1397 lapic_ipi_raw(icrlo, destfield); 1398 1399 #ifdef DETECT_DEADLOCK 1400 /* Wait for IPI to be delivered. */ 1401 if (!lapic_ipi_wait(AFTER_SPIN)) { 1402 #ifdef needsattention 1403 /* 1404 * XXX FIXME: 1405 * 1406 * The above function waits for the message to actually be 1407 * delivered. It breaks out after an arbitrary timeout 1408 * since the message should eventually be delivered (at 1409 * least in theory) and that if it wasn't we would catch 1410 * the failure with the check above when the next IPI is 1411 * sent. 1412 * 1413 * We could skip this wait entirely, EXCEPT it probably 1414 * protects us from other routines that assume that the 1415 * message was delivered and acted upon when this function 1416 * returns. 1417 */ 1418 printf("APIC: IPI might be stuck\n"); 1419 #else /* !needsattention */ 1420 /* Wait until mesage is sent without a timeout. */ 1421 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1422 ia32_pause(); 1423 #endif /* needsattention */ 1424 } 1425 #endif /* DETECT_DEADLOCK */ 1426 } 1427 #endif /* SMP */
Cache object: e903393eddc487317d6cb8a75c80d05d
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]