Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/longrun.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Tamotsu Hattori. 5 * Copyright (c) 2001 Mitsuru IWASAKI. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD: releng/12.0/sys/i386/i386/longrun.c 325966 2017-11-18 14:26:50Z pfg $"); 40 41 #include "opt_cpu.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/conf.h> 47 #include <sys/power.h> 48 #include <sys/sysctl.h> 49 #include <sys/types.h> 50 51 #include <machine/cputypes.h> 52 #include <machine/md_var.h> 53 #include <machine/specialreg.h> 54 55 /* 56 * Transmeta Crusoe LongRun Support by Tamotsu Hattori. 57 */ 58 59 #define MSR_TMx86_LONGRUN 0x80868010 60 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011 61 62 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f) 63 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80) 64 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y)) 65 66 #define LONGRUN_MODE_MINFREQUENCY 0x00 67 #define LONGRUN_MODE_ECONOMY 0x01 68 #define LONGRUN_MODE_PERFORMANCE 0x02 69 #define LONGRUN_MODE_MAXFREQUENCY 0x03 70 #define LONGRUN_MODE_UNKNOWN 0x04 71 #define LONGRUN_MODE_MAX 0x04 72 73 union msrinfo { 74 u_int64_t msr; 75 u_int32_t regs[2]; 76 }; 77 78 static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = { 79 /* MSR low, MSR high, flags bit0 */ 80 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */ 81 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */ 82 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */ 83 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */ 84 }; 85 86 static u_int 87 tmx86_get_longrun_mode(void) 88 { 89 register_t saveintr; 90 union msrinfo msrinfo; 91 u_int low, high, flags, mode; 92 93 saveintr = intr_disable(); 94 95 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 96 low = LONGRUN_MODE_MASK(msrinfo.regs[0]); 97 high = LONGRUN_MODE_MASK(msrinfo.regs[1]); 98 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01; 99 100 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) { 101 if (low == longrun_modes[mode][0] && 102 high == longrun_modes[mode][1] && 103 flags == longrun_modes[mode][2]) { 104 goto out; 105 } 106 } 107 mode = LONGRUN_MODE_UNKNOWN; 108 out: 109 intr_restore(saveintr); 110 return (mode); 111 } 112 113 static u_int 114 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage) 115 { 116 register_t saveintr; 117 u_int regs[4]; 118 119 saveintr = intr_disable(); 120 121 do_cpuid(0x80860007, regs); 122 *frequency = regs[0]; 123 *voltage = regs[1]; 124 *percentage = regs[2]; 125 126 intr_restore(saveintr); 127 return (1); 128 } 129 130 static u_int 131 tmx86_set_longrun_mode(u_int mode) 132 { 133 register_t saveintr; 134 union msrinfo msrinfo; 135 136 if (mode >= LONGRUN_MODE_UNKNOWN) { 137 return (0); 138 } 139 140 saveintr = intr_disable(); 141 142 /* Write LongRun mode values to Model Specific Register. */ 143 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 144 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0], 145 longrun_modes[mode][0]); 146 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1], 147 longrun_modes[mode][1]); 148 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); 149 150 /* Write LongRun mode flags to Model Specific Register. */ 151 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); 152 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2]; 153 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); 154 155 intr_restore(saveintr); 156 return (1); 157 } 158 159 static u_int crusoe_longrun; 160 static u_int crusoe_frequency; 161 static u_int crusoe_voltage; 162 static u_int crusoe_percentage; 163 static u_int crusoe_performance_longrun = LONGRUN_MODE_PERFORMANCE; 164 static u_int crusoe_economy_longrun = LONGRUN_MODE_ECONOMY; 165 static struct sysctl_ctx_list crusoe_sysctl_ctx; 166 static struct sysctl_oid *crusoe_sysctl_tree; 167 168 static void 169 tmx86_longrun_power_profile(void *arg) 170 { 171 int state; 172 u_int new; 173 174 state = power_profile_get_state(); 175 if (state != POWER_PROFILE_PERFORMANCE && 176 state != POWER_PROFILE_ECONOMY) { 177 return; 178 } 179 180 switch (state) { 181 case POWER_PROFILE_PERFORMANCE: 182 new =crusoe_performance_longrun; 183 break; 184 case POWER_PROFILE_ECONOMY: 185 new = crusoe_economy_longrun; 186 break; 187 default: 188 new = tmx86_get_longrun_mode(); 189 break; 190 } 191 192 if (tmx86_get_longrun_mode() != new) { 193 tmx86_set_longrun_mode(new); 194 } 195 } 196 197 static int 198 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS) 199 { 200 u_int mode; 201 int error; 202 203 crusoe_longrun = tmx86_get_longrun_mode(); 204 mode = crusoe_longrun; 205 error = sysctl_handle_int(oidp, &mode, 0, req); 206 if (error || !req->newptr) { 207 return (error); 208 } 209 if (mode >= LONGRUN_MODE_UNKNOWN) { 210 error = EINVAL; 211 return (error); 212 } 213 if (crusoe_longrun != mode) { 214 crusoe_longrun = mode; 215 tmx86_set_longrun_mode(crusoe_longrun); 216 } 217 218 return (error); 219 } 220 221 static int 222 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS) 223 { 224 u_int val; 225 int error; 226 227 tmx86_get_longrun_status(&crusoe_frequency, 228 &crusoe_voltage, &crusoe_percentage); 229 val = *(u_int *)oidp->oid_arg1; 230 error = sysctl_handle_int(oidp, &val, 0, req); 231 return (error); 232 } 233 234 static int 235 tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS) 236 { 237 u_int32_t *argp; 238 u_int32_t arg; 239 int error; 240 241 argp = (u_int32_t *)oidp->oid_arg1; 242 arg = *argp; 243 error = sysctl_handle_int(oidp, &arg, 0, req); 244 245 /* error or no new value */ 246 if ((error != 0) || (req->newptr == NULL)) 247 return (error); 248 249 /* range check */ 250 if (arg >= LONGRUN_MODE_UNKNOWN) 251 return (EINVAL); 252 253 /* set new value and possibly switch */ 254 *argp = arg; 255 256 tmx86_longrun_power_profile(NULL); 257 258 return (0); 259 260 } 261 262 static void 263 setup_tmx86_longrun(void *dummy __unused) 264 { 265 266 if (cpu_vendor_id != CPU_VENDOR_TRANSMETA) 267 return; 268 269 crusoe_longrun = tmx86_get_longrun_mode(); 270 tmx86_get_longrun_status(&crusoe_frequency, 271 &crusoe_voltage, &crusoe_percentage); 272 printf("Crusoe LongRun support enabled, current mode: %d " 273 "<%dMHz %dmV %d%%>\n", crusoe_longrun, crusoe_frequency, 274 crusoe_voltage, crusoe_percentage); 275 276 sysctl_ctx_init(&crusoe_sysctl_ctx); 277 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx, 278 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 279 "crusoe", CTLFLAG_RD, 0, 280 "Transmeta Crusoe LongRun support"); 281 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 282 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW, 283 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I", 284 "LongRun mode [0-3]"); 285 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 286 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD, 287 &crusoe_frequency, 0, tmx86_status_sysctl, "I", 288 "Current frequency (MHz)"); 289 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 290 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD, 291 &crusoe_voltage, 0, tmx86_status_sysctl, "I", 292 "Current voltage (mV)"); 293 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 294 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD, 295 &crusoe_percentage, 0, tmx86_status_sysctl, "I", 296 "Processing performance (%)"); 297 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 298 OID_AUTO, "performance_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW, 299 &crusoe_performance_longrun, 0, tmx86_longrun_profile_sysctl, "I", ""); 300 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree), 301 OID_AUTO, "economy_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW, 302 &crusoe_economy_longrun, 0, tmx86_longrun_profile_sysctl, "I", ""); 303 304 /* register performance profile change handler */ 305 EVENTHANDLER_REGISTER(power_profile_change, tmx86_longrun_power_profile, NULL, 0); 306 } 307 SYSINIT(setup_tmx86_longrun, SI_SUB_CPU, SI_ORDER_ANY, setup_tmx86_longrun, 308 NULL);
Cache object: d133059fd271718b9c1d3333b673e0a7
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]