Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/machdep.c
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1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2018 The FreeBSD Foundation 5 * Copyright (c) 1992 Terrence R. Lambert. 6 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Portions of this software were developed by A. Joseph Koshy under 13 * sponsorship from the FreeBSD Foundation and Google, Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include "opt_apic.h" 50 #include "opt_atpic.h" 51 #include "opt_cpu.h" 52 #include "opt_ddb.h" 53 #include "opt_inet.h" 54 #include "opt_isa.h" 55 #include "opt_kstack_pages.h" 56 #include "opt_maxmem.h" 57 #include "opt_mp_watchdog.h" 58 #include "opt_perfmon.h" 59 #include "opt_platform.h" 60 61 #include <sys/param.h> 62 #include <sys/proc.h> 63 #include <sys/systm.h> 64 #include <sys/bio.h> 65 #include <sys/buf.h> 66 #include <sys/bus.h> 67 #include <sys/callout.h> 68 #include <sys/cons.h> 69 #include <sys/cpu.h> 70 #include <sys/eventhandler.h> 71 #include <sys/exec.h> 72 #include <sys/imgact.h> 73 #include <sys/kdb.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/linker.h> 77 #include <sys/lock.h> 78 #include <sys/malloc.h> 79 #include <sys/memrange.h> 80 #include <sys/msgbuf.h> 81 #include <sys/mutex.h> 82 #include <sys/pcpu.h> 83 #include <sys/ptrace.h> 84 #include <sys/reboot.h> 85 #include <sys/reg.h> 86 #include <sys/rwlock.h> 87 #include <sys/sched.h> 88 #include <sys/signalvar.h> 89 #include <sys/smp.h> 90 #include <sys/syscallsubr.h> 91 #include <sys/sysctl.h> 92 #include <sys/sysent.h> 93 #include <sys/sysproto.h> 94 #include <sys/ucontext.h> 95 #include <sys/vmmeter.h> 96 97 #include <vm/vm.h> 98 #include <vm/vm_param.h> 99 #include <vm/vm_extern.h> 100 #include <vm/vm_kern.h> 101 #include <vm/vm_page.h> 102 #include <vm/vm_map.h> 103 #include <vm/vm_object.h> 104 #include <vm/vm_pager.h> 105 #include <vm/vm_phys.h> 106 #include <vm/vm_dumpset.h> 107 108 #ifdef DDB 109 #ifndef KDB 110 #error KDB must be enabled in order for DDB to work! 111 #endif 112 #include <ddb/ddb.h> 113 #include <ddb/db_sym.h> 114 #endif 115 116 #include <isa/rtc.h> 117 118 #include <net/netisr.h> 119 120 #include <machine/bootinfo.h> 121 #include <machine/clock.h> 122 #include <machine/cpu.h> 123 #include <machine/cputypes.h> 124 #include <machine/intr_machdep.h> 125 #include <x86/mca.h> 126 #include <machine/md_var.h> 127 #include <machine/metadata.h> 128 #include <machine/mp_watchdog.h> 129 #include <machine/pc/bios.h> 130 #include <machine/pcb.h> 131 #include <machine/pcb_ext.h> 132 #include <machine/proc.h> 133 #include <machine/sigframe.h> 134 #include <machine/specialreg.h> 135 #include <machine/sysarch.h> 136 #include <machine/trap.h> 137 #include <x86/ucode.h> 138 #include <machine/vm86.h> 139 #include <x86/init.h> 140 #ifdef PERFMON 141 #include <machine/perfmon.h> 142 #endif 143 #ifdef SMP 144 #include <machine/smp.h> 145 #endif 146 #ifdef FDT 147 #include <x86/fdt.h> 148 #endif 149 150 #ifdef DEV_APIC 151 #include <x86/apicvar.h> 152 #endif 153 154 #ifdef DEV_ISA 155 #include <x86/isa/icu.h> 156 #endif 157 158 /* Sanity check for __curthread() */ 159 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 160 161 register_t init386(int first); 162 void dblfault_handler(void); 163 void identify_cpu(void); 164 165 static void cpu_startup(void *); 166 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 167 168 /* Intel ICH registers */ 169 #define ICH_PMBASE 0x400 170 #define ICH_SMI_EN ICH_PMBASE + 0x30 171 172 int _udatasel, _ucodesel; 173 u_int basemem; 174 static int above4g_allow = 1; 175 static int above24g_allow = 0; 176 177 int cold = 1; 178 179 long Maxmem = 0; 180 long realmem = 0; 181 182 #ifdef PAE 183 FEATURE(pae, "Physical Address Extensions"); 184 #endif 185 186 struct kva_md_info kmi; 187 188 static struct trapframe proc0_tf; 189 struct pcpu __pcpu[MAXCPU]; 190 191 static void i386_clock_source_init(void); 192 193 struct mtx icu_lock; 194 195 struct mem_range_softc mem_range_softc; 196 197 extern char start_exceptions[], end_exceptions[]; 198 199 extern struct sysentvec elf32_freebsd_sysvec; 200 201 /* Default init_ops implementation. */ 202 struct init_ops init_ops = { 203 .early_clock_source_init = i386_clock_source_init, 204 .early_delay = i8254_delay, 205 #ifdef DEV_APIC 206 .msi_init = msi_init, 207 #endif 208 }; 209 210 static void 211 i386_clock_source_init(void) 212 { 213 i8254_init(); 214 tsc_init(); 215 } 216 217 static void 218 cpu_startup(dummy) 219 void *dummy; 220 { 221 uintmax_t memsize; 222 char *sysenv; 223 224 /* 225 * On MacBooks, we need to disallow the legacy USB circuit to 226 * generate an SMI# because this can cause several problems, 227 * namely: incorrect CPU frequency detection and failure to 228 * start the APs. 229 * We do this by disabling a bit in the SMI_EN (SMI Control and 230 * Enable register) of the Intel ICH LPC Interface Bridge. 231 */ 232 sysenv = kern_getenv("smbios.system.product"); 233 if (sysenv != NULL) { 234 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 235 strncmp(sysenv, "MacBook3,1", 10) == 0 || 236 strncmp(sysenv, "MacBook4,1", 10) == 0 || 237 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 238 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 239 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 240 strncmp(sysenv, "MacBookPro4,1", 13) == 0 || 241 strncmp(sysenv, "Macmini1,1", 10) == 0) { 242 if (bootverbose) 243 printf("Disabling LEGACY_USB_EN bit on " 244 "Intel ICH.\n"); 245 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 246 } 247 freeenv(sysenv); 248 } 249 250 /* 251 * Good {morning,afternoon,evening,night}. 252 */ 253 startrtclock(); 254 printcpuinfo(); 255 panicifcpuunsupported(); 256 #ifdef PERFMON 257 perfmon_init(); 258 #endif 259 260 /* 261 * Display physical memory if SMBIOS reports reasonable amount. 262 */ 263 memsize = 0; 264 sysenv = kern_getenv("smbios.memory.enabled"); 265 if (sysenv != NULL) { 266 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 267 freeenv(sysenv); 268 } 269 if (memsize < ptoa((uintmax_t)vm_free_count())) 270 memsize = ptoa((uintmax_t)Maxmem); 271 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 272 realmem = atop(memsize); 273 274 /* 275 * Display any holes after the first chunk of extended memory. 276 */ 277 if (bootverbose) { 278 int indx; 279 280 printf("Physical memory chunk(s):\n"); 281 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 282 vm_paddr_t size; 283 284 size = phys_avail[indx + 1] - phys_avail[indx]; 285 printf( 286 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 287 (uintmax_t)phys_avail[indx], 288 (uintmax_t)phys_avail[indx + 1] - 1, 289 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 290 } 291 } 292 293 vm_ksubmap_init(&kmi); 294 295 printf("avail memory = %ju (%ju MB)\n", 296 ptoa((uintmax_t)vm_free_count()), 297 ptoa((uintmax_t)vm_free_count()) / 1048576); 298 299 /* 300 * Set up buffers, so they can be used to read disk labels. 301 */ 302 bufinit(); 303 vm_pager_bufferinit(); 304 cpu_setregs(); 305 } 306 307 void 308 cpu_setregs(void) 309 { 310 unsigned int cr0; 311 312 cr0 = rcr0(); 313 314 /* 315 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support: 316 * 317 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 318 * instructions. We must set the CR0_MP bit and use the CR0_TS 319 * bit to control the trap, because setting the CR0_EM bit does 320 * not cause WAIT instructions to trap. It's important to trap 321 * WAIT instructions - otherwise the "wait" variants of no-wait 322 * control instructions would degenerate to the "no-wait" variants 323 * after FP context switches but work correctly otherwise. It's 324 * particularly important to trap WAITs when there is no NPX - 325 * otherwise the "wait" variants would always degenerate. 326 * 327 * Try setting CR0_NE to get correct error reporting on 486DX's. 328 * Setting it should fail or do nothing on lesser processors. 329 */ 330 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 331 load_cr0(cr0); 332 load_gs(_udatasel); 333 } 334 335 u_long bootdev; /* not a struct cdev *- encoding is different */ 336 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 337 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)"); 338 339 static char bootmethod[16] = "BIOS"; 340 SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0, 341 "System firmware boot method"); 342 343 /* 344 * Initialize 386 and configure to run kernel 345 */ 346 347 /* 348 * Initialize segments & interrupt table 349 */ 350 351 int _default_ldt; 352 353 struct mtx dt_lock; /* lock for GDT and LDT */ 354 355 union descriptor gdt0[NGDT]; /* initial global descriptor table */ 356 union descriptor *gdt = gdt0; /* global descriptor table */ 357 358 union descriptor *ldt; /* local descriptor table */ 359 360 static struct gate_descriptor idt0[NIDT]; 361 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 362 363 static struct i386tss *dblfault_tss; 364 static char *dblfault_stack; 365 366 static struct i386tss common_tss0; 367 368 vm_offset_t proc0kstack; 369 370 /* 371 * software prototypes -- in more palatable form. 372 * 373 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret 374 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it) 375 */ 376 struct soft_segment_descriptor gdt_segs[] = { 377 /* GNULL_SEL 0 Null Descriptor */ 378 { .ssd_base = 0x0, 379 .ssd_limit = 0x0, 380 .ssd_type = 0, 381 .ssd_dpl = SEL_KPL, 382 .ssd_p = 0, 383 .ssd_xx = 0, .ssd_xx1 = 0, 384 .ssd_def32 = 0, 385 .ssd_gran = 0 }, 386 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */ 387 { .ssd_base = 0x0, 388 .ssd_limit = 0xfffff, 389 .ssd_type = SDT_MEMRWA, 390 .ssd_dpl = SEL_KPL, 391 .ssd_p = 1, 392 .ssd_xx = 0, .ssd_xx1 = 0, 393 .ssd_def32 = 1, 394 .ssd_gran = 1 }, 395 /* GUFS_SEL 2 %fs Descriptor for user */ 396 { .ssd_base = 0x0, 397 .ssd_limit = 0xfffff, 398 .ssd_type = SDT_MEMRWA, 399 .ssd_dpl = SEL_UPL, 400 .ssd_p = 1, 401 .ssd_xx = 0, .ssd_xx1 = 0, 402 .ssd_def32 = 1, 403 .ssd_gran = 1 }, 404 /* GUGS_SEL 3 %gs Descriptor for user */ 405 { .ssd_base = 0x0, 406 .ssd_limit = 0xfffff, 407 .ssd_type = SDT_MEMRWA, 408 .ssd_dpl = SEL_UPL, 409 .ssd_p = 1, 410 .ssd_xx = 0, .ssd_xx1 = 0, 411 .ssd_def32 = 1, 412 .ssd_gran = 1 }, 413 /* GCODE_SEL 4 Code Descriptor for kernel */ 414 { .ssd_base = 0x0, 415 .ssd_limit = 0xfffff, 416 .ssd_type = SDT_MEMERA, 417 .ssd_dpl = SEL_KPL, 418 .ssd_p = 1, 419 .ssd_xx = 0, .ssd_xx1 = 0, 420 .ssd_def32 = 1, 421 .ssd_gran = 1 }, 422 /* GDATA_SEL 5 Data Descriptor for kernel */ 423 { .ssd_base = 0x0, 424 .ssd_limit = 0xfffff, 425 .ssd_type = SDT_MEMRWA, 426 .ssd_dpl = SEL_KPL, 427 .ssd_p = 1, 428 .ssd_xx = 0, .ssd_xx1 = 0, 429 .ssd_def32 = 1, 430 .ssd_gran = 1 }, 431 /* GUCODE_SEL 6 Code Descriptor for user */ 432 { .ssd_base = 0x0, 433 .ssd_limit = 0xfffff, 434 .ssd_type = SDT_MEMERA, 435 .ssd_dpl = SEL_UPL, 436 .ssd_p = 1, 437 .ssd_xx = 0, .ssd_xx1 = 0, 438 .ssd_def32 = 1, 439 .ssd_gran = 1 }, 440 /* GUDATA_SEL 7 Data Descriptor for user */ 441 { .ssd_base = 0x0, 442 .ssd_limit = 0xfffff, 443 .ssd_type = SDT_MEMRWA, 444 .ssd_dpl = SEL_UPL, 445 .ssd_p = 1, 446 .ssd_xx = 0, .ssd_xx1 = 0, 447 .ssd_def32 = 1, 448 .ssd_gran = 1 }, 449 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */ 450 { .ssd_base = 0x400, 451 .ssd_limit = 0xfffff, 452 .ssd_type = SDT_MEMRWA, 453 .ssd_dpl = SEL_KPL, 454 .ssd_p = 1, 455 .ssd_xx = 0, .ssd_xx1 = 0, 456 .ssd_def32 = 1, 457 .ssd_gran = 1 }, 458 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 459 { 460 .ssd_base = 0x0, 461 .ssd_limit = sizeof(struct i386tss)-1, 462 .ssd_type = SDT_SYS386TSS, 463 .ssd_dpl = 0, 464 .ssd_p = 1, 465 .ssd_xx = 0, .ssd_xx1 = 0, 466 .ssd_def32 = 0, 467 .ssd_gran = 0 }, 468 /* GLDT_SEL 10 LDT Descriptor */ 469 { .ssd_base = 0, 470 .ssd_limit = sizeof(union descriptor) * NLDT - 1, 471 .ssd_type = SDT_SYSLDT, 472 .ssd_dpl = SEL_UPL, 473 .ssd_p = 1, 474 .ssd_xx = 0, .ssd_xx1 = 0, 475 .ssd_def32 = 0, 476 .ssd_gran = 0 }, 477 /* GUSERLDT_SEL 11 User LDT Descriptor per process */ 478 { .ssd_base = 0, 479 .ssd_limit = (512 * sizeof(union descriptor)-1), 480 .ssd_type = SDT_SYSLDT, 481 .ssd_dpl = 0, 482 .ssd_p = 1, 483 .ssd_xx = 0, .ssd_xx1 = 0, 484 .ssd_def32 = 0, 485 .ssd_gran = 0 }, 486 /* GPANIC_SEL 12 Panic Tss Descriptor */ 487 { .ssd_base = 0, 488 .ssd_limit = sizeof(struct i386tss)-1, 489 .ssd_type = SDT_SYS386TSS, 490 .ssd_dpl = 0, 491 .ssd_p = 1, 492 .ssd_xx = 0, .ssd_xx1 = 0, 493 .ssd_def32 = 0, 494 .ssd_gran = 0 }, 495 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */ 496 { .ssd_base = 0, 497 .ssd_limit = 0xfffff, 498 .ssd_type = SDT_MEMERA, 499 .ssd_dpl = 0, 500 .ssd_p = 1, 501 .ssd_xx = 0, .ssd_xx1 = 0, 502 .ssd_def32 = 0, 503 .ssd_gran = 1 }, 504 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */ 505 { .ssd_base = 0, 506 .ssd_limit = 0xfffff, 507 .ssd_type = SDT_MEMERA, 508 .ssd_dpl = 0, 509 .ssd_p = 1, 510 .ssd_xx = 0, .ssd_xx1 = 0, 511 .ssd_def32 = 0, 512 .ssd_gran = 1 }, 513 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */ 514 { .ssd_base = 0, 515 .ssd_limit = 0xfffff, 516 .ssd_type = SDT_MEMRWA, 517 .ssd_dpl = 0, 518 .ssd_p = 1, 519 .ssd_xx = 0, .ssd_xx1 = 0, 520 .ssd_def32 = 1, 521 .ssd_gran = 1 }, 522 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */ 523 { .ssd_base = 0, 524 .ssd_limit = 0xfffff, 525 .ssd_type = SDT_MEMRWA, 526 .ssd_dpl = 0, 527 .ssd_p = 1, 528 .ssd_xx = 0, .ssd_xx1 = 0, 529 .ssd_def32 = 0, 530 .ssd_gran = 1 }, 531 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */ 532 { .ssd_base = 0, 533 .ssd_limit = 0xfffff, 534 .ssd_type = SDT_MEMRWA, 535 .ssd_dpl = 0, 536 .ssd_p = 1, 537 .ssd_xx = 0, .ssd_xx1 = 0, 538 .ssd_def32 = 0, 539 .ssd_gran = 1 }, 540 /* GNDIS_SEL 18 NDIS Descriptor */ 541 { .ssd_base = 0x0, 542 .ssd_limit = 0x0, 543 .ssd_type = 0, 544 .ssd_dpl = 0, 545 .ssd_p = 0, 546 .ssd_xx = 0, .ssd_xx1 = 0, 547 .ssd_def32 = 0, 548 .ssd_gran = 0 }, 549 }; 550 551 static struct soft_segment_descriptor ldt_segs[] = { 552 /* Null Descriptor - overwritten by call gate */ 553 { .ssd_base = 0x0, 554 .ssd_limit = 0x0, 555 .ssd_type = 0, 556 .ssd_dpl = 0, 557 .ssd_p = 0, 558 .ssd_xx = 0, .ssd_xx1 = 0, 559 .ssd_def32 = 0, 560 .ssd_gran = 0 }, 561 /* Null Descriptor - overwritten by call gate */ 562 { .ssd_base = 0x0, 563 .ssd_limit = 0x0, 564 .ssd_type = 0, 565 .ssd_dpl = 0, 566 .ssd_p = 0, 567 .ssd_xx = 0, .ssd_xx1 = 0, 568 .ssd_def32 = 0, 569 .ssd_gran = 0 }, 570 /* Null Descriptor - overwritten by call gate */ 571 { .ssd_base = 0x0, 572 .ssd_limit = 0x0, 573 .ssd_type = 0, 574 .ssd_dpl = 0, 575 .ssd_p = 0, 576 .ssd_xx = 0, .ssd_xx1 = 0, 577 .ssd_def32 = 0, 578 .ssd_gran = 0 }, 579 /* Code Descriptor for user */ 580 { .ssd_base = 0x0, 581 .ssd_limit = 0xfffff, 582 .ssd_type = SDT_MEMERA, 583 .ssd_dpl = SEL_UPL, 584 .ssd_p = 1, 585 .ssd_xx = 0, .ssd_xx1 = 0, 586 .ssd_def32 = 1, 587 .ssd_gran = 1 }, 588 /* Null Descriptor - overwritten by call gate */ 589 { .ssd_base = 0x0, 590 .ssd_limit = 0x0, 591 .ssd_type = 0, 592 .ssd_dpl = 0, 593 .ssd_p = 0, 594 .ssd_xx = 0, .ssd_xx1 = 0, 595 .ssd_def32 = 0, 596 .ssd_gran = 0 }, 597 /* Data Descriptor for user */ 598 { .ssd_base = 0x0, 599 .ssd_limit = 0xfffff, 600 .ssd_type = SDT_MEMRWA, 601 .ssd_dpl = SEL_UPL, 602 .ssd_p = 1, 603 .ssd_xx = 0, .ssd_xx1 = 0, 604 .ssd_def32 = 1, 605 .ssd_gran = 1 }, 606 }; 607 608 size_t setidt_disp; 609 610 void 611 setidt(int idx, inthand_t *func, int typ, int dpl, int selec) 612 { 613 uintptr_t off; 614 615 off = func != NULL ? (uintptr_t)func + setidt_disp : 0; 616 setidt_nodisp(idx, off, typ, dpl, selec); 617 } 618 619 void 620 setidt_nodisp(int idx, uintptr_t off, int typ, int dpl, int selec) 621 { 622 struct gate_descriptor *ip; 623 624 ip = idt + idx; 625 ip->gd_looffset = off; 626 ip->gd_selector = selec; 627 ip->gd_stkcpy = 0; 628 ip->gd_xx = 0; 629 ip->gd_type = typ; 630 ip->gd_dpl = dpl; 631 ip->gd_p = 1; 632 ip->gd_hioffset = ((u_int)off) >> 16 ; 633 } 634 635 extern inthand_t 636 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 637 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 638 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 639 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 640 IDTVEC(xmm), 641 #ifdef KDTRACE_HOOKS 642 IDTVEC(dtrace_ret), 643 #endif 644 #ifdef XENHVM 645 IDTVEC(xen_intr_upcall), 646 #endif 647 IDTVEC(int0x80_syscall); 648 649 #ifdef DDB 650 /* 651 * Display the index and function name of any IDT entries that don't use 652 * the default 'rsvd' entry point. 653 */ 654 DB_SHOW_COMMAND(idt, db_show_idt) 655 { 656 struct gate_descriptor *ip; 657 int idx; 658 uintptr_t func, func_trm; 659 bool trm; 660 661 ip = idt; 662 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 663 if (ip->gd_type == SDT_SYSTASKGT) { 664 db_printf("%3d\t<TASK>\n", idx); 665 } else { 666 func = (ip->gd_hioffset << 16 | ip->gd_looffset); 667 if (func >= PMAP_TRM_MIN_ADDRESS) { 668 func_trm = func; 669 func -= setidt_disp; 670 trm = true; 671 } else 672 trm = false; 673 if (func != (uintptr_t)&IDTVEC(rsvd)) { 674 db_printf("%3d\t", idx); 675 db_printsym(func, DB_STGY_PROC); 676 if (trm) 677 db_printf(" (trampoline %#x)", 678 func_trm); 679 db_printf("\n"); 680 } 681 } 682 ip++; 683 } 684 } 685 686 /* Show privileged registers. */ 687 DB_SHOW_COMMAND(sysregs, db_show_sysregs) 688 { 689 uint64_t idtr, gdtr; 690 691 idtr = ridt(); 692 db_printf("idtr\t0x%08x/%04x\n", 693 (u_int)(idtr >> 16), (u_int)idtr & 0xffff); 694 gdtr = rgdt(); 695 db_printf("gdtr\t0x%08x/%04x\n", 696 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff); 697 db_printf("ldtr\t0x%04x\n", rldt()); 698 db_printf("tr\t0x%04x\n", rtr()); 699 db_printf("cr0\t0x%08x\n", rcr0()); 700 db_printf("cr2\t0x%08x\n", rcr2()); 701 db_printf("cr3\t0x%08x\n", rcr3()); 702 db_printf("cr4\t0x%08x\n", rcr4()); 703 if (rcr4() & CR4_XSAVE) 704 db_printf("xcr0\t0x%016llx\n", rxcr(0)); 705 if (amd_feature & (AMDID_NX | AMDID_LM)) 706 db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER)); 707 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) 708 db_printf("FEATURES_CTL\t0x%016llx\n", 709 rdmsr(MSR_IA32_FEATURE_CONTROL)); 710 if (((cpu_vendor_id == CPU_VENDOR_INTEL || 711 cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) || 712 cpu_vendor_id == CPU_VENDOR_HYGON) 713 db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR)); 714 if (cpu_feature & CPUID_PAT) 715 db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT)); 716 } 717 718 DB_SHOW_COMMAND(dbregs, db_show_dbregs) 719 { 720 721 db_printf("dr0\t0x%08x\n", rdr0()); 722 db_printf("dr1\t0x%08x\n", rdr1()); 723 db_printf("dr2\t0x%08x\n", rdr2()); 724 db_printf("dr3\t0x%08x\n", rdr3()); 725 db_printf("dr6\t0x%08x\n", rdr6()); 726 db_printf("dr7\t0x%08x\n", rdr7()); 727 } 728 729 DB_SHOW_COMMAND(frame, db_show_frame) 730 { 731 struct trapframe *frame; 732 733 frame = have_addr ? (struct trapframe *)addr : curthread->td_frame; 734 printf("ss %#x esp %#x efl %#x cs %#x eip %#x\n", 735 frame->tf_ss, frame->tf_esp, frame->tf_eflags, frame->tf_cs, 736 frame->tf_eip); 737 printf("err %#x trapno %d\n", frame->tf_err, frame->tf_trapno); 738 printf("ds %#x es %#x fs %#x\n", 739 frame->tf_ds, frame->tf_es, frame->tf_fs); 740 printf("eax %#x ecx %#x edx %#x ebx %#x\n", 741 frame->tf_eax, frame->tf_ecx, frame->tf_edx, frame->tf_ebx); 742 printf("ebp %#x esi %#x edi %#x\n", 743 frame->tf_ebp, frame->tf_esi, frame->tf_edi); 744 745 } 746 #endif 747 748 void 749 sdtossd(sd, ssd) 750 struct segment_descriptor *sd; 751 struct soft_segment_descriptor *ssd; 752 { 753 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 754 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 755 ssd->ssd_type = sd->sd_type; 756 ssd->ssd_dpl = sd->sd_dpl; 757 ssd->ssd_p = sd->sd_p; 758 ssd->ssd_def32 = sd->sd_def32; 759 ssd->ssd_gran = sd->sd_gran; 760 } 761 762 static int 763 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 764 int *physmap_idxp) 765 { 766 uint64_t lim, ign; 767 int i, insert_idx, physmap_idx; 768 769 physmap_idx = *physmap_idxp; 770 771 if (length == 0) 772 return (1); 773 774 lim = 0x100000000; /* 4G */ 775 if (pae_mode && above4g_allow) 776 lim = above24g_allow ? -1ULL : 0x600000000; /* 24G */ 777 if (base >= lim) { 778 printf("%uK of memory above %uGB ignored, pae %d " 779 "above4g_allow %d above24g_allow %d\n", 780 (u_int)(length / 1024), (u_int)(lim >> 30), pae_mode, 781 above4g_allow, above24g_allow); 782 return (1); 783 } 784 if (base + length >= lim) { 785 ign = base + length - lim; 786 length -= ign; 787 printf("%uK of memory above %uGB ignored, pae %d " 788 "above4g_allow %d above24g_allow %d\n", 789 (u_int)(ign / 1024), (u_int)(lim >> 30), pae_mode, 790 above4g_allow, above24g_allow); 791 } 792 793 /* 794 * Find insertion point while checking for overlap. Start off by 795 * assuming the new entry will be added to the end. 796 */ 797 insert_idx = physmap_idx + 2; 798 for (i = 0; i <= physmap_idx; i += 2) { 799 if (base < physmap[i + 1]) { 800 if (base + length <= physmap[i]) { 801 insert_idx = i; 802 break; 803 } 804 if (boothowto & RB_VERBOSE) 805 printf( 806 "Overlapping memory regions, ignoring second region\n"); 807 return (1); 808 } 809 } 810 811 /* See if we can prepend to the next entry. */ 812 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 813 physmap[insert_idx] = base; 814 return (1); 815 } 816 817 /* See if we can append to the previous entry. */ 818 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 819 physmap[insert_idx - 1] += length; 820 return (1); 821 } 822 823 physmap_idx += 2; 824 *physmap_idxp = physmap_idx; 825 if (physmap_idx == PHYS_AVAIL_ENTRIES) { 826 printf( 827 "Too many segments in the physical address map, giving up\n"); 828 return (0); 829 } 830 831 /* 832 * Move the last 'N' entries down to make room for the new 833 * entry if needed. 834 */ 835 for (i = physmap_idx; i > insert_idx; i -= 2) { 836 physmap[i] = physmap[i - 2]; 837 physmap[i + 1] = physmap[i - 1]; 838 } 839 840 /* Insert the new entry. */ 841 physmap[insert_idx] = base; 842 physmap[insert_idx + 1] = base + length; 843 return (1); 844 } 845 846 static int 847 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 848 { 849 if (boothowto & RB_VERBOSE) 850 printf("SMAP type=%02x base=%016llx len=%016llx\n", 851 smap->type, smap->base, smap->length); 852 853 if (smap->type != SMAP_TYPE_MEMORY) 854 return (1); 855 856 return (add_physmap_entry(smap->base, smap->length, physmap, 857 physmap_idxp)); 858 } 859 860 static void 861 add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap, 862 int *physmap_idxp) 863 { 864 struct bios_smap *smap, *smapend; 865 u_int32_t smapsize; 866 /* 867 * Memory map from INT 15:E820. 868 * 869 * subr_module.c says: 870 * "Consumer may safely assume that size value precedes data." 871 * ie: an int32_t immediately precedes SMAP. 872 */ 873 smapsize = *((u_int32_t *)smapbase - 1); 874 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 875 876 for (smap = smapbase; smap < smapend; smap++) 877 if (!add_smap_entry(smap, physmap, physmap_idxp)) 878 break; 879 } 880 881 static void 882 basemem_setup(void) 883 { 884 885 if (basemem > 640) { 886 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n", 887 basemem); 888 basemem = 640; 889 } 890 891 pmap_basemem_setup(basemem); 892 } 893 894 /* 895 * Populate the (physmap) array with base/bound pairs describing the 896 * available physical memory in the system, then test this memory and 897 * build the phys_avail array describing the actually-available memory. 898 * 899 * If we cannot accurately determine the physical memory map, then use 900 * value from the 0xE801 call, and failing that, the RTC. 901 * 902 * Total memory size may be set by the kernel environment variable 903 * hw.physmem or the compile-time define MAXMEM. 904 * 905 * XXX first should be vm_paddr_t. 906 */ 907 static void 908 getmemsize(int first) 909 { 910 int has_smap, off, physmap_idx, pa_indx, da_indx; 911 u_long memtest; 912 vm_paddr_t physmap[PHYS_AVAIL_ENTRIES]; 913 quad_t dcons_addr, dcons_size, physmem_tunable; 914 int hasbrokenint12, i, res; 915 u_int extmem; 916 struct vm86frame vmf; 917 struct vm86context vmc; 918 vm_paddr_t pa; 919 struct bios_smap *smap, *smapbase; 920 caddr_t kmdp; 921 922 has_smap = 0; 923 bzero(&vmf, sizeof(vmf)); 924 bzero(physmap, sizeof(physmap)); 925 basemem = 0; 926 927 /* 928 * Tell the physical memory allocator about pages used to store 929 * the kernel and preloaded data. See kmem_bootstrap_free(). 930 */ 931 vm_phys_early_add_seg((vm_paddr_t)KERNLOAD, trunc_page(first)); 932 933 TUNABLE_INT_FETCH("hw.above4g_allow", &above4g_allow); 934 TUNABLE_INT_FETCH("hw.above24g_allow", &above24g_allow); 935 936 /* 937 * Check if the loader supplied an SMAP memory map. If so, 938 * use that and do not make any VM86 calls. 939 */ 940 physmap_idx = 0; 941 kmdp = preload_search_by_type("elf kernel"); 942 if (kmdp == NULL) 943 kmdp = preload_search_by_type("elf32 kernel"); 944 smapbase = (struct bios_smap *)preload_search_info(kmdp, 945 MODINFO_METADATA | MODINFOMD_SMAP); 946 if (smapbase != NULL) { 947 add_smap_entries(smapbase, physmap, &physmap_idx); 948 has_smap = 1; 949 goto have_smap; 950 } 951 952 /* 953 * Some newer BIOSes have a broken INT 12H implementation 954 * which causes a kernel panic immediately. In this case, we 955 * need use the SMAP to determine the base memory size. 956 */ 957 hasbrokenint12 = 0; 958 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12); 959 if (hasbrokenint12 == 0) { 960 /* Use INT12 to determine base memory size. */ 961 vm86_intcall(0x12, &vmf); 962 basemem = vmf.vmf_ax; 963 basemem_setup(); 964 } 965 966 /* 967 * Fetch the memory map with INT 15:E820. Map page 1 R/W into 968 * the kernel page table so we can use it as a buffer. The 969 * kernel will unmap this page later. 970 */ 971 vmc.npages = 0; 972 smap = (void *)vm86_addpage(&vmc, 1, PMAP_MAP_LOW + ptoa(1)); 973 res = vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di); 974 KASSERT(res != 0, ("vm86_getptr() failed: address not found")); 975 976 vmf.vmf_ebx = 0; 977 do { 978 vmf.vmf_eax = 0xE820; 979 vmf.vmf_edx = SMAP_SIG; 980 vmf.vmf_ecx = sizeof(struct bios_smap); 981 i = vm86_datacall(0x15, &vmf, &vmc); 982 if (i || vmf.vmf_eax != SMAP_SIG) 983 break; 984 has_smap = 1; 985 if (!add_smap_entry(smap, physmap, &physmap_idx)) 986 break; 987 } while (vmf.vmf_ebx != 0); 988 989 have_smap: 990 /* 991 * If we didn't fetch the "base memory" size from INT12, 992 * figure it out from the SMAP (or just guess). 993 */ 994 if (basemem == 0) { 995 for (i = 0; i <= physmap_idx; i += 2) { 996 if (physmap[i] == 0x00000000) { 997 basemem = physmap[i + 1] / 1024; 998 break; 999 } 1000 } 1001 1002 /* XXX: If we couldn't find basemem from SMAP, just guess. */ 1003 if (basemem == 0) 1004 basemem = 640; 1005 basemem_setup(); 1006 } 1007 1008 if (physmap[1] != 0) 1009 goto physmap_done; 1010 1011 /* 1012 * If we failed to find an SMAP, figure out the extended 1013 * memory size. We will then build a simple memory map with 1014 * two segments, one for "base memory" and the second for 1015 * "extended memory". Note that "extended memory" starts at a 1016 * physical address of 1MB and that both basemem and extmem 1017 * are in units of 1KB. 1018 * 1019 * First, try to fetch the extended memory size via INT 15:E801. 1020 */ 1021 vmf.vmf_ax = 0xE801; 1022 if (vm86_intcall(0x15, &vmf) == 0) { 1023 extmem = vmf.vmf_cx + vmf.vmf_dx * 64; 1024 } else { 1025 /* 1026 * If INT15:E801 fails, this is our last ditch effort 1027 * to determine the extended memory size. Currently 1028 * we prefer the RTC value over INT15:88. 1029 */ 1030 #if 0 1031 vmf.vmf_ah = 0x88; 1032 vm86_intcall(0x15, &vmf); 1033 extmem = vmf.vmf_ax; 1034 #else 1035 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8); 1036 #endif 1037 } 1038 1039 /* 1040 * Special hack for chipsets that still remap the 384k hole when 1041 * there's 16MB of memory - this really confuses people that 1042 * are trying to use bus mastering ISA controllers with the 1043 * "16MB limit"; they only have 16MB, but the remapping puts 1044 * them beyond the limit. 1045 * 1046 * If extended memory is between 15-16MB (16-17MB phys address range), 1047 * chop it to 15MB. 1048 */ 1049 if ((extmem > 15 * 1024) && (extmem < 16 * 1024)) 1050 extmem = 15 * 1024; 1051 1052 physmap[0] = 0; 1053 physmap[1] = basemem * 1024; 1054 physmap_idx = 2; 1055 physmap[physmap_idx] = 0x100000; 1056 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024; 1057 1058 physmap_done: 1059 /* 1060 * Now, physmap contains a map of physical memory. 1061 */ 1062 1063 #ifdef SMP 1064 /* make hole for AP bootstrap code */ 1065 alloc_ap_trampoline(physmap, &physmap_idx); 1066 #endif 1067 1068 /* 1069 * Maxmem isn't the "maximum memory", it's one larger than the 1070 * highest page of the physical address space. It should be 1071 * called something like "Maxphyspage". We may adjust this 1072 * based on ``hw.physmem'' and the results of the memory test. 1073 * 1074 * This is especially confusing when it is much larger than the 1075 * memory size and is displayed as "realmem". 1076 */ 1077 Maxmem = atop(physmap[physmap_idx + 1]); 1078 1079 #ifdef MAXMEM 1080 Maxmem = MAXMEM / 4; 1081 #endif 1082 1083 if (TUNABLE_QUAD_FETCH("hw.physmem", &physmem_tunable)) 1084 Maxmem = atop(physmem_tunable); 1085 1086 /* 1087 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend 1088 * the amount of memory in the system. 1089 */ 1090 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1])) 1091 Maxmem = atop(physmap[physmap_idx + 1]); 1092 1093 /* 1094 * The boot memory test is disabled by default, as it takes a 1095 * significant amount of time on large-memory systems, and is 1096 * unfriendly to virtual machines as it unnecessarily touches all 1097 * pages. 1098 * 1099 * A general name is used as the code may be extended to support 1100 * additional tests beyond the current "page present" test. 1101 */ 1102 memtest = 0; 1103 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1104 1105 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1106 (boothowto & RB_VERBOSE)) 1107 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1108 1109 /* 1110 * If Maxmem has been increased beyond what the system has detected, 1111 * extend the last memory segment to the new limit. 1112 */ 1113 if (atop(physmap[physmap_idx + 1]) < Maxmem) 1114 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem); 1115 1116 /* call pmap initialization to make new kernel address space */ 1117 pmap_bootstrap(first); 1118 1119 /* 1120 * Size up each available chunk of physical memory. 1121 */ 1122 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1123 pa_indx = 0; 1124 da_indx = 1; 1125 phys_avail[pa_indx++] = physmap[0]; 1126 phys_avail[pa_indx] = physmap[0]; 1127 dump_avail[da_indx] = physmap[0]; 1128 1129 /* 1130 * Get dcons buffer address 1131 */ 1132 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1133 getenv_quad("dcons.size", &dcons_size) == 0) 1134 dcons_addr = 0; 1135 1136 /* 1137 * physmap is in bytes, so when converting to page boundaries, 1138 * round up the start address and round down the end address. 1139 */ 1140 for (i = 0; i <= physmap_idx; i += 2) { 1141 vm_paddr_t end; 1142 1143 end = ptoa((vm_paddr_t)Maxmem); 1144 if (physmap[i + 1] < end) 1145 end = trunc_page(physmap[i + 1]); 1146 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1147 int tmp, page_bad, full; 1148 int *ptr; 1149 1150 full = FALSE; 1151 /* 1152 * block out kernel memory as not available. 1153 */ 1154 if (pa >= KERNLOAD && pa < first) 1155 goto do_dump_avail; 1156 1157 /* 1158 * block out dcons buffer 1159 */ 1160 if (dcons_addr > 0 1161 && pa >= trunc_page(dcons_addr) 1162 && pa < dcons_addr + dcons_size) 1163 goto do_dump_avail; 1164 1165 page_bad = FALSE; 1166 if (memtest == 0) 1167 goto skip_memtest; 1168 1169 /* 1170 * map page into kernel: valid, read/write,non-cacheable 1171 */ 1172 ptr = (int *)pmap_cmap3(pa, PG_V | PG_RW | PG_N); 1173 1174 tmp = *(int *)ptr; 1175 /* 1176 * Test for alternating 1's and 0's 1177 */ 1178 *(volatile int *)ptr = 0xaaaaaaaa; 1179 if (*(volatile int *)ptr != 0xaaaaaaaa) 1180 page_bad = TRUE; 1181 /* 1182 * Test for alternating 0's and 1's 1183 */ 1184 *(volatile int *)ptr = 0x55555555; 1185 if (*(volatile int *)ptr != 0x55555555) 1186 page_bad = TRUE; 1187 /* 1188 * Test for all 1's 1189 */ 1190 *(volatile int *)ptr = 0xffffffff; 1191 if (*(volatile int *)ptr != 0xffffffff) 1192 page_bad = TRUE; 1193 /* 1194 * Test for all 0's 1195 */ 1196 *(volatile int *)ptr = 0x0; 1197 if (*(volatile int *)ptr != 0x0) 1198 page_bad = TRUE; 1199 /* 1200 * Restore original value. 1201 */ 1202 *(int *)ptr = tmp; 1203 1204 skip_memtest: 1205 /* 1206 * Adjust array of valid/good pages. 1207 */ 1208 if (page_bad == TRUE) 1209 continue; 1210 /* 1211 * If this good page is a continuation of the 1212 * previous set of good pages, then just increase 1213 * the end pointer. Otherwise start a new chunk. 1214 * Note that "end" points one higher than end, 1215 * making the range >= start and < end. 1216 * If we're also doing a speculative memory 1217 * test and we at or past the end, bump up Maxmem 1218 * so that we keep going. The first bad page 1219 * will terminate the loop. 1220 */ 1221 if (phys_avail[pa_indx] == pa) { 1222 phys_avail[pa_indx] += PAGE_SIZE; 1223 } else { 1224 pa_indx++; 1225 if (pa_indx == PHYS_AVAIL_ENTRIES) { 1226 printf( 1227 "Too many holes in the physical address space, giving up\n"); 1228 pa_indx--; 1229 full = TRUE; 1230 goto do_dump_avail; 1231 } 1232 phys_avail[pa_indx++] = pa; /* start */ 1233 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1234 } 1235 physmem++; 1236 do_dump_avail: 1237 if (dump_avail[da_indx] == pa) { 1238 dump_avail[da_indx] += PAGE_SIZE; 1239 } else { 1240 da_indx++; 1241 if (da_indx == PHYS_AVAIL_ENTRIES) { 1242 da_indx--; 1243 goto do_next; 1244 } 1245 dump_avail[da_indx++] = pa; /* start */ 1246 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1247 } 1248 do_next: 1249 if (full) 1250 break; 1251 } 1252 } 1253 pmap_cmap3(0, 0); 1254 1255 /* 1256 * XXX 1257 * The last chunk must contain at least one page plus the message 1258 * buffer to avoid complicating other code (message buffer address 1259 * calculation, etc.). 1260 */ 1261 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1262 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1263 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1264 phys_avail[pa_indx--] = 0; 1265 phys_avail[pa_indx--] = 0; 1266 } 1267 1268 Maxmem = atop(phys_avail[pa_indx]); 1269 1270 /* Trim off space for the message buffer. */ 1271 phys_avail[pa_indx] -= round_page(msgbufsize); 1272 1273 /* Map the message buffer. */ 1274 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE) 1275 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] + 1276 off); 1277 } 1278 1279 static void 1280 i386_kdb_init(void) 1281 { 1282 #ifdef DDB 1283 db_fetch_ksymtab(bootinfo.bi_symtab, bootinfo.bi_esymtab, 0); 1284 #endif 1285 kdb_init(); 1286 #ifdef KDB 1287 if (boothowto & RB_KDB) 1288 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 1289 #endif 1290 } 1291 1292 static void 1293 fixup_idt(void) 1294 { 1295 struct gate_descriptor *ip; 1296 uintptr_t off; 1297 int x; 1298 1299 for (x = 0; x < NIDT; x++) { 1300 ip = &idt[x]; 1301 if (ip->gd_type != SDT_SYS386IGT && 1302 ip->gd_type != SDT_SYS386TGT) 1303 continue; 1304 off = ip->gd_looffset + (((u_int)ip->gd_hioffset) << 16); 1305 KASSERT(off >= (uintptr_t)start_exceptions && 1306 off < (uintptr_t)end_exceptions, 1307 ("IDT[%d] type %d off %#x", x, ip->gd_type, off)); 1308 off += setidt_disp; 1309 MPASS(off >= PMAP_TRM_MIN_ADDRESS && 1310 off < PMAP_TRM_MAX_ADDRESS); 1311 ip->gd_looffset = off; 1312 ip->gd_hioffset = off >> 16; 1313 } 1314 } 1315 1316 static void 1317 i386_setidt1(void) 1318 { 1319 int x; 1320 1321 /* exceptions */ 1322 for (x = 0; x < NIDT; x++) 1323 setidt(x, &IDTVEC(rsvd), SDT_SYS386IGT, SEL_KPL, 1324 GSEL(GCODE_SEL, SEL_KPL)); 1325 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386IGT, SEL_KPL, 1326 GSEL(GCODE_SEL, SEL_KPL)); 1327 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL, 1328 GSEL(GCODE_SEL, SEL_KPL)); 1329 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL, 1330 GSEL(GCODE_SEL, SEL_KPL)); 1331 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL, 1332 GSEL(GCODE_SEL, SEL_KPL)); 1333 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386IGT, SEL_UPL, 1334 GSEL(GCODE_SEL, SEL_KPL)); 1335 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386IGT, SEL_KPL, 1336 GSEL(GCODE_SEL, SEL_KPL)); 1337 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, 1338 GSEL(GCODE_SEL, SEL_KPL)); 1339 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386IGT, SEL_KPL, 1340 GSEL(GCODE_SEL, SEL_KPL)); 1341 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, 1342 SEL_KPL)); 1343 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386IGT, 1344 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1345 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386IGT, SEL_KPL, 1346 GSEL(GCODE_SEL, SEL_KPL)); 1347 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386IGT, SEL_KPL, 1348 GSEL(GCODE_SEL, SEL_KPL)); 1349 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386IGT, SEL_KPL, 1350 GSEL(GCODE_SEL, SEL_KPL)); 1351 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, 1352 GSEL(GCODE_SEL, SEL_KPL)); 1353 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, 1354 GSEL(GCODE_SEL, SEL_KPL)); 1355 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386IGT, SEL_KPL, 1356 GSEL(GCODE_SEL, SEL_KPL)); 1357 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386IGT, SEL_KPL, 1358 GSEL(GCODE_SEL, SEL_KPL)); 1359 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386IGT, SEL_KPL, 1360 GSEL(GCODE_SEL, SEL_KPL)); 1361 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386IGT, SEL_KPL, 1362 GSEL(GCODE_SEL, SEL_KPL)); 1363 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall), 1364 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL)); 1365 #ifdef KDTRACE_HOOKS 1366 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), 1367 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL)); 1368 #endif 1369 #ifdef XENHVM 1370 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), 1371 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1372 #endif 1373 } 1374 1375 static void 1376 i386_setidt2(void) 1377 { 1378 1379 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, 1380 GSEL(GCODE_SEL, SEL_KPL)); 1381 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, 1382 GSEL(GCODE_SEL, SEL_KPL)); 1383 } 1384 1385 #if defined(DEV_ISA) && !defined(DEV_ATPIC) 1386 static void 1387 i386_setidt3(void) 1388 { 1389 1390 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), 1391 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1392 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), 1393 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1394 } 1395 #endif 1396 1397 register_t 1398 init386(int first) 1399 { 1400 struct region_descriptor r_gdt, r_idt; /* table descriptors */ 1401 int gsel_tss, metadata_missing, x, pa; 1402 struct pcpu *pc; 1403 struct xstate_hdr *xhdr; 1404 caddr_t kmdp; 1405 vm_offset_t addend; 1406 size_t ucode_len; 1407 int late_console; 1408 1409 thread0.td_kstack = proc0kstack; 1410 thread0.td_kstack_pages = TD0_KSTACK_PAGES; 1411 1412 /* 1413 * This may be done better later if it gets more high level 1414 * components in it. If so just link td->td_proc here. 1415 */ 1416 proc_linkup0(&proc0, &thread0); 1417 1418 if (bootinfo.bi_modulep) { 1419 metadata_missing = 0; 1420 addend = (vm_paddr_t)bootinfo.bi_modulep < KERNBASE ? 1421 PMAP_MAP_LOW : 0; 1422 preload_metadata = (caddr_t)bootinfo.bi_modulep + addend; 1423 preload_bootstrap_relocate(addend); 1424 } else { 1425 metadata_missing = 1; 1426 } 1427 1428 if (bootinfo.bi_envp != 0) { 1429 addend = (vm_paddr_t)bootinfo.bi_envp < KERNBASE ? 1430 PMAP_MAP_LOW : 0; 1431 init_static_kenv((char *)bootinfo.bi_envp + addend, 0); 1432 } else { 1433 init_static_kenv(NULL, 0); 1434 } 1435 1436 /* 1437 * Re-evaluate CPU features if we loaded a microcode update. 1438 */ 1439 ucode_len = ucode_load_bsp(first); 1440 if (ucode_len != 0) { 1441 identify_cpu(); 1442 first = roundup2(first + ucode_len, PAGE_SIZE); 1443 } 1444 1445 identify_hypervisor(); 1446 1447 /* Init basic tunables, hz etc */ 1448 init_param1(); 1449 1450 /* 1451 * Make gdt memory segments. All segments cover the full 4GB 1452 * of address space and permissions are enforced at page level. 1453 */ 1454 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1); 1455 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1); 1456 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1); 1457 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1); 1458 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1); 1459 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1); 1460 1461 pc = &__pcpu[0]; 1462 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1); 1463 gdt_segs[GPRIV_SEL].ssd_base = (int)pc; 1464 gdt_segs[GPROC0_SEL].ssd_base = (int)&common_tss0; 1465 1466 for (x = 0; x < NGDT; x++) 1467 ssdtosd(&gdt_segs[x], &gdt0[x].sd); 1468 1469 r_gdt.rd_limit = NGDT * sizeof(gdt0[0]) - 1; 1470 r_gdt.rd_base = (int)gdt0; 1471 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN); 1472 lgdt(&r_gdt); 1473 1474 pcpu_init(pc, 0, sizeof(struct pcpu)); 1475 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE) 1476 pmap_kenter(pa, pa); 1477 dpcpu_init((void *)first, 0); 1478 first += DPCPU_SIZE; 1479 PCPU_SET(prvspace, pc); 1480 PCPU_SET(curthread, &thread0); 1481 /* Non-late cninit() and printf() can be moved up to here. */ 1482 1483 /* 1484 * Initialize mutexes. 1485 * 1486 * icu_lock: in order to allow an interrupt to occur in a critical 1487 * section, to set pcpu->ipending (etc...) properly, we 1488 * must be able to get the icu lock, so it can't be 1489 * under witness. 1490 */ 1491 mutex_init(); 1492 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE); 1493 1494 i386_setidt1(); 1495 1496 r_idt.rd_limit = sizeof(idt0) - 1; 1497 r_idt.rd_base = (int) idt; 1498 lidt(&r_idt); 1499 1500 finishidentcpu(); /* Final stage of CPU initialization */ 1501 1502 /* 1503 * Initialize the clock before the console so that console 1504 * initialization can use DELAY(). 1505 */ 1506 clock_init(); 1507 1508 i386_setidt2(); 1509 pmap_set_nx(); 1510 initializecpu(); /* Initialize CPU registers */ 1511 initializecpucache(); 1512 1513 /* pointer to selector slot for %fs/%gs */ 1514 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd); 1515 1516 /* Initialize the tss (except for the final esp0) early for vm86. */ 1517 common_tss0.tss_esp0 = thread0.td_kstack + thread0.td_kstack_pages * 1518 PAGE_SIZE - VM86_STACK_SPACE; 1519 common_tss0.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 1520 common_tss0.tss_ioopt = sizeof(struct i386tss) << 16; 1521 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1522 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd); 1523 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 1524 ltr(gsel_tss); 1525 1526 /* Initialize the PIC early for vm86 calls. */ 1527 #ifdef DEV_ISA 1528 #ifdef DEV_ATPIC 1529 elcr_probe(); 1530 atpic_startup(); 1531 #else 1532 /* Reset and mask the atpics and leave them shut down. */ 1533 atpic_reset(); 1534 1535 /* 1536 * Point the ICU spurious interrupt vectors at the APIC spurious 1537 * interrupt handler. 1538 */ 1539 i386_setidt3(); 1540 #endif 1541 #endif 1542 1543 /* 1544 * The console and kdb should be initialized even earlier than here, 1545 * but some console drivers don't work until after getmemsize(). 1546 * Default to late console initialization to support these drivers. 1547 * This loses mainly printf()s in getmemsize() and early debugging. 1548 */ 1549 late_console = 1; 1550 TUNABLE_INT_FETCH("debug.late_console", &late_console); 1551 if (!late_console) { 1552 cninit(); 1553 i386_kdb_init(); 1554 } 1555 1556 kmdp = preload_search_by_type("elf kernel"); 1557 link_elf_ireloc(kmdp); 1558 1559 vm86_initialize(); 1560 getmemsize(first); 1561 init_param2(physmem); 1562 1563 /* now running on new page tables, configured,and u/iom is accessible */ 1564 1565 if (late_console) 1566 cninit(); 1567 1568 if (metadata_missing) 1569 printf("WARNING: loader(8) metadata is missing!\n"); 1570 1571 if (late_console) 1572 i386_kdb_init(); 1573 1574 msgbufinit(msgbufp, msgbufsize); 1575 npxinit(true); 1576 /* 1577 * Set up thread0 pcb after npxinit calculated pcb + fpu save 1578 * area size. Zero out the extended state header in fpu save 1579 * area. 1580 */ 1581 thread0.td_pcb = get_pcb_td(&thread0); 1582 thread0.td_pcb->pcb_save = get_pcb_user_save_td(&thread0); 1583 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1584 if (use_xsave) { 1585 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1586 1); 1587 xhdr->xstate_bv = xsave_mask; 1588 } 1589 PCPU_SET(curpcb, thread0.td_pcb); 1590 /* Move esp0 in the tss to its final place. */ 1591 /* Note: -16 is so we can grow the trapframe if we came from vm86 */ 1592 common_tss0.tss_esp0 = (vm_offset_t)thread0.td_pcb - VM86_STACK_SPACE; 1593 PCPU_SET(kesp0, common_tss0.tss_esp0); 1594 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; /* clear busy bit */ 1595 ltr(gsel_tss); 1596 1597 /* transfer to user mode */ 1598 1599 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1600 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1601 1602 /* setup proc 0's pcb */ 1603 thread0.td_pcb->pcb_flags = 0; 1604 thread0.td_pcb->pcb_cr3 = pmap_get_kcr3(); 1605 thread0.td_pcb->pcb_ext = 0; 1606 thread0.td_frame = &proc0_tf; 1607 1608 #ifdef FDT 1609 x86_init_fdt(); 1610 #endif 1611 1612 /* Location of kernel stack for locore */ 1613 return ((register_t)thread0.td_pcb); 1614 } 1615 1616 static void 1617 machdep_init_trampoline(void) 1618 { 1619 struct region_descriptor r_gdt, r_idt; 1620 struct i386tss *tss; 1621 char *copyout_buf, *trampoline, *tramp_stack_base; 1622 int x; 1623 1624 gdt = pmap_trm_alloc(sizeof(union descriptor) * NGDT * mp_ncpus, 1625 M_NOWAIT | M_ZERO); 1626 bcopy(gdt0, gdt, sizeof(union descriptor) * NGDT); 1627 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1628 r_gdt.rd_base = (int)gdt; 1629 lgdt(&r_gdt); 1630 1631 tss = pmap_trm_alloc(sizeof(struct i386tss) * mp_ncpus, 1632 M_NOWAIT | M_ZERO); 1633 bcopy(&common_tss0, tss, sizeof(struct i386tss)); 1634 gdt[GPROC0_SEL].sd.sd_lobase = (int)tss; 1635 gdt[GPROC0_SEL].sd.sd_hibase = (u_int)tss >> 24; 1636 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 1637 1638 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd); 1639 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd); 1640 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 1641 PCPU_SET(common_tssp, tss); 1642 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 1643 1644 trampoline = pmap_trm_alloc(end_exceptions - start_exceptions, 1645 M_NOWAIT); 1646 bcopy(start_exceptions, trampoline, end_exceptions - start_exceptions); 1647 tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT); 1648 PCPU_SET(trampstk, (uintptr_t)tramp_stack_base + TRAMP_STACK_SZ - 1649 VM86_STACK_SPACE); 1650 tss[0].tss_esp0 = PCPU_GET(trampstk); 1651 1652 idt = pmap_trm_alloc(sizeof(idt0), M_NOWAIT | M_ZERO); 1653 bcopy(idt0, idt, sizeof(idt0)); 1654 1655 /* Re-initialize new IDT since the handlers were relocated */ 1656 setidt_disp = trampoline - start_exceptions; 1657 if (bootverbose) 1658 printf("Trampoline disposition %#zx\n", setidt_disp); 1659 fixup_idt(); 1660 1661 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1; 1662 r_idt.rd_base = (int)idt; 1663 lidt(&r_idt); 1664 1665 /* dblfault TSS */ 1666 dblfault_tss = pmap_trm_alloc(sizeof(struct i386tss), M_NOWAIT | M_ZERO); 1667 dblfault_stack = pmap_trm_alloc(PAGE_SIZE, M_NOWAIT); 1668 dblfault_tss->tss_esp = dblfault_tss->tss_esp0 = 1669 dblfault_tss->tss_esp1 = dblfault_tss->tss_esp2 = 1670 (int)dblfault_stack + PAGE_SIZE; 1671 dblfault_tss->tss_ss = dblfault_tss->tss_ss0 = dblfault_tss->tss_ss1 = 1672 dblfault_tss->tss_ss2 = GSEL(GDATA_SEL, SEL_KPL); 1673 dblfault_tss->tss_cr3 = pmap_get_kcr3(); 1674 dblfault_tss->tss_eip = (int)dblfault_handler; 1675 dblfault_tss->tss_eflags = PSL_KERNEL; 1676 dblfault_tss->tss_ds = dblfault_tss->tss_es = 1677 dblfault_tss->tss_gs = GSEL(GDATA_SEL, SEL_KPL); 1678 dblfault_tss->tss_fs = GSEL(GPRIV_SEL, SEL_KPL); 1679 dblfault_tss->tss_cs = GSEL(GCODE_SEL, SEL_KPL); 1680 dblfault_tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 1681 gdt[GPANIC_SEL].sd.sd_lobase = (int)dblfault_tss; 1682 gdt[GPANIC_SEL].sd.sd_hibase = (u_int)dblfault_tss >> 24; 1683 1684 /* make ldt memory segments */ 1685 ldt = pmap_trm_alloc(sizeof(union descriptor) * NLDT, 1686 M_NOWAIT | M_ZERO); 1687 gdt[GLDT_SEL].sd.sd_lobase = (int)ldt; 1688 gdt[GLDT_SEL].sd.sd_hibase = (u_int)ldt >> 24; 1689 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1); 1690 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1); 1691 for (x = 0; x < nitems(ldt_segs); x++) 1692 ssdtosd(&ldt_segs[x], &ldt[x].sd); 1693 1694 _default_ldt = GSEL(GLDT_SEL, SEL_KPL); 1695 lldt(_default_ldt); 1696 PCPU_SET(currentldt, _default_ldt); 1697 1698 copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT); 1699 PCPU_SET(copyout_buf, copyout_buf); 1700 copyout_init_tramp(); 1701 } 1702 SYSINIT(vm_mem, SI_SUB_VM, SI_ORDER_SECOND, machdep_init_trampoline, NULL); 1703 1704 #ifdef COMPAT_43 1705 static void 1706 i386_setup_lcall_gate(void) 1707 { 1708 struct sysentvec *sv; 1709 struct user_segment_descriptor desc; 1710 u_int lcall_addr; 1711 1712 sv = &elf32_freebsd_sysvec; 1713 lcall_addr = (uintptr_t)sv->sv_psstrings - sz_lcall_tramp; 1714 1715 bzero(&desc, sizeof(desc)); 1716 desc.sd_type = SDT_MEMERA; 1717 desc.sd_dpl = SEL_UPL; 1718 desc.sd_p = 1; 1719 desc.sd_def32 = 1; 1720 desc.sd_gran = 1; 1721 desc.sd_lolimit = 0xffff; 1722 desc.sd_hilimit = 0xf; 1723 desc.sd_lobase = lcall_addr; 1724 desc.sd_hibase = lcall_addr >> 24; 1725 bcopy(&desc, &ldt[LSYS5CALLS_SEL], sizeof(desc)); 1726 } 1727 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_ANY, i386_setup_lcall_gate, NULL); 1728 #endif 1729 1730 void 1731 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1732 { 1733 1734 pcpu->pc_acpi_id = 0xffffffff; 1735 } 1736 1737 static int 1738 smap_sysctl_handler(SYSCTL_HANDLER_ARGS) 1739 { 1740 struct bios_smap *smapbase; 1741 struct bios_smap_xattr smap; 1742 caddr_t kmdp; 1743 uint32_t *smapattr; 1744 int count, error, i; 1745 1746 /* Retrieve the system memory map from the loader. */ 1747 kmdp = preload_search_by_type("elf kernel"); 1748 if (kmdp == NULL) 1749 kmdp = preload_search_by_type("elf32 kernel"); 1750 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1751 MODINFO_METADATA | MODINFOMD_SMAP); 1752 if (smapbase == NULL) 1753 return (0); 1754 smapattr = (uint32_t *)preload_search_info(kmdp, 1755 MODINFO_METADATA | MODINFOMD_SMAP_XATTR); 1756 count = *((u_int32_t *)smapbase - 1) / sizeof(*smapbase); 1757 error = 0; 1758 for (i = 0; i < count; i++) { 1759 smap.base = smapbase[i].base; 1760 smap.length = smapbase[i].length; 1761 smap.type = smapbase[i].type; 1762 if (smapattr != NULL) 1763 smap.xattr = smapattr[i]; 1764 else 1765 smap.xattr = 0; 1766 error = SYSCTL_OUT(req, &smap, sizeof(smap)); 1767 } 1768 return (error); 1769 } 1770 SYSCTL_PROC(_machdep, OID_AUTO, smap, 1771 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1772 smap_sysctl_handler, "S,bios_smap_xattr", 1773 "Raw BIOS SMAP data"); 1774 1775 void 1776 spinlock_enter(void) 1777 { 1778 struct thread *td; 1779 register_t flags; 1780 1781 td = curthread; 1782 if (td->td_md.md_spinlock_count == 0) { 1783 flags = intr_disable(); 1784 td->td_md.md_spinlock_count = 1; 1785 td->td_md.md_saved_flags = flags; 1786 critical_enter(); 1787 } else 1788 td->td_md.md_spinlock_count++; 1789 } 1790 1791 void 1792 spinlock_exit(void) 1793 { 1794 struct thread *td; 1795 register_t flags; 1796 1797 td = curthread; 1798 flags = td->td_md.md_saved_flags; 1799 td->td_md.md_spinlock_count--; 1800 if (td->td_md.md_spinlock_count == 0) { 1801 critical_exit(); 1802 intr_restore(flags); 1803 } 1804 } 1805 1806 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 1807 static void f00f_hack(void *unused); 1808 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL); 1809 1810 static void 1811 f00f_hack(void *unused) 1812 { 1813 struct region_descriptor r_idt; 1814 struct gate_descriptor *new_idt; 1815 vm_offset_t tmp; 1816 1817 if (!has_f00f_bug) 1818 return; 1819 1820 GIANT_REQUIRED; 1821 1822 printf("Intel Pentium detected, installing workaround for F00F bug\n"); 1823 1824 tmp = (vm_offset_t)pmap_trm_alloc(PAGE_SIZE * 3, M_NOWAIT | M_ZERO); 1825 if (tmp == 0) 1826 panic("kmem_malloc returned 0"); 1827 tmp = round_page(tmp); 1828 1829 /* Put the problematic entry (#6) at the end of the lower page. */ 1830 new_idt = (struct gate_descriptor *) 1831 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor)); 1832 bcopy(idt, new_idt, sizeof(idt0)); 1833 r_idt.rd_base = (u_int)new_idt; 1834 r_idt.rd_limit = sizeof(idt0) - 1; 1835 lidt(&r_idt); 1836 /* SMP machines do not need the F00F hack. */ 1837 idt = new_idt; 1838 pmap_protect(kernel_pmap, tmp, tmp + PAGE_SIZE, VM_PROT_READ); 1839 } 1840 #endif /* defined(I586_CPU) && !NO_F00F_HACK */ 1841 1842 /* 1843 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1844 * we want to start a backtrace from the function that caused us to enter 1845 * the debugger. We have the context in the trapframe, but base the trace 1846 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1847 * enough for a backtrace. 1848 */ 1849 void 1850 makectx(struct trapframe *tf, struct pcb *pcb) 1851 { 1852 1853 pcb->pcb_edi = tf->tf_edi; 1854 pcb->pcb_esi = tf->tf_esi; 1855 pcb->pcb_ebp = tf->tf_ebp; 1856 pcb->pcb_ebx = tf->tf_ebx; 1857 pcb->pcb_eip = tf->tf_eip; 1858 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8; 1859 pcb->pcb_gs = rgs(); 1860 } 1861 1862 #ifdef KDB 1863 1864 /* 1865 * Provide inb() and outb() as functions. They are normally only available as 1866 * inline functions, thus cannot be called from the debugger. 1867 */ 1868 1869 /* silence compiler warnings */ 1870 u_char inb_(u_short); 1871 void outb_(u_short, u_char); 1872 1873 u_char 1874 inb_(u_short port) 1875 { 1876 return inb(port); 1877 } 1878 1879 void 1880 outb_(u_short port, u_char data) 1881 { 1882 outb(port, data); 1883 } 1884 1885 #endif /* KDB */
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