1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 */
39
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD: releng/8.1/sys/i386/i386/machdep.c 206890 2010-04-20 08:19:43Z kib $");
42
43 #include "opt_apic.h"
44 #include "opt_atalk.h"
45 #include "opt_compat.h"
46 #include "opt_cpu.h"
47 #include "opt_ddb.h"
48 #include "opt_inet.h"
49 #include "opt_ipx.h"
50 #include "opt_isa.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_msgbuf.h"
54 #include "opt_npx.h"
55 #include "opt_perfmon.h"
56 #include "opt_xbox.h"
57
58 #include <sys/param.h>
59 #include <sys/proc.h>
60 #include <sys/systm.h>
61 #include <sys/bio.h>
62 #include <sys/buf.h>
63 #include <sys/bus.h>
64 #include <sys/callout.h>
65 #include <sys/cons.h>
66 #include <sys/cpu.h>
67 #include <sys/eventhandler.h>
68 #include <sys/exec.h>
69 #include <sys/imgact.h>
70 #include <sys/kdb.h>
71 #include <sys/kernel.h>
72 #include <sys/ktr.h>
73 #include <sys/linker.h>
74 #include <sys/lock.h>
75 #include <sys/malloc.h>
76 #include <sys/memrange.h>
77 #include <sys/msgbuf.h>
78 #include <sys/mutex.h>
79 #include <sys/pcpu.h>
80 #include <sys/ptrace.h>
81 #include <sys/reboot.h>
82 #include <sys/sched.h>
83 #include <sys/signalvar.h>
84 #include <sys/sysctl.h>
85 #include <sys/sysent.h>
86 #include <sys/sysproto.h>
87 #include <sys/ucontext.h>
88 #include <sys/vmmeter.h>
89
90 #include <vm/vm.h>
91 #include <vm/vm_extern.h>
92 #include <vm/vm_kern.h>
93 #include <vm/vm_page.h>
94 #include <vm/vm_map.h>
95 #include <vm/vm_object.h>
96 #include <vm/vm_pager.h>
97 #include <vm/vm_param.h>
98
99 #ifdef DDB
100 #ifndef KDB
101 #error KDB must be enabled in order for DDB to work!
102 #endif
103 #include <ddb/ddb.h>
104 #include <ddb/db_sym.h>
105 #endif
106
107 #include <isa/rtc.h>
108
109 #include <net/netisr.h>
110
111 #include <machine/bootinfo.h>
112 #include <machine/clock.h>
113 #include <machine/cpu.h>
114 #include <machine/cputypes.h>
115 #include <machine/intr_machdep.h>
116 #include <machine/mca.h>
117 #include <machine/md_var.h>
118 #include <machine/metadata.h>
119 #include <machine/pc/bios.h>
120 #include <machine/pcb.h>
121 #include <machine/pcb_ext.h>
122 #include <machine/proc.h>
123 #include <machine/reg.h>
124 #include <machine/sigframe.h>
125 #include <machine/specialreg.h>
126 #include <machine/vm86.h>
127 #ifdef PERFMON
128 #include <machine/perfmon.h>
129 #endif
130 #ifdef SMP
131 #include <machine/smp.h>
132 #endif
133
134 #ifdef DEV_ISA
135 #include <i386/isa/icu.h>
136 #endif
137
138 #ifdef XBOX
139 #include <machine/xbox.h>
140
141 int arch_i386_is_xbox = 0;
142 uint32_t arch_i386_xbox_memsize = 0;
143 #endif
144
145 #ifdef XEN
146 /* XEN includes */
147 #include <machine/xen/xen-os.h>
148 #include <xen/hypervisor.h>
149 #include <machine/xen/xen-os.h>
150 #include <machine/xen/xenvar.h>
151 #include <machine/xen/xenfunc.h>
152 #include <xen/xen_intr.h>
153
154 void Xhypervisor_callback(void);
155 void failsafe_callback(void);
156
157 extern trap_info_t trap_table[];
158 struct proc_ldt default_proc_ldt;
159 extern int init_first;
160 int running_xen = 1;
161 extern unsigned long physfree;
162 #endif /* XEN */
163
164 /* Sanity check for __curthread() */
165 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
166
167 extern void init386(int first);
168 extern void dblfault_handler(void);
169
170 extern void printcpuinfo(void); /* XXX header file */
171 extern void finishidentcpu(void);
172 extern void panicifcpuunsupported(void);
173 extern void initializecpu(void);
174
175 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
176 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
177
178 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
179 #define CPU_ENABLE_SSE
180 #endif
181
182 static void cpu_startup(void *);
183 static void fpstate_drop(struct thread *td);
184 static void get_fpcontext(struct thread *td, mcontext_t *mcp);
185 static int set_fpcontext(struct thread *td, const mcontext_t *mcp);
186 #ifdef CPU_ENABLE_SSE
187 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
188 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
189 #endif /* CPU_ENABLE_SSE */
190 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
191
192 #ifdef DDB
193 extern vm_offset_t ksym_start, ksym_end;
194 #endif
195
196 /* Intel ICH registers */
197 #define ICH_PMBASE 0x400
198 #define ICH_SMI_EN ICH_PMBASE + 0x30
199
200 int _udatasel, _ucodesel;
201 u_int basemem;
202
203 int cold = 1;
204
205 #ifdef COMPAT_43
206 static void osendsig(sig_t catcher, ksiginfo_t *, sigset_t *mask);
207 #endif
208 #ifdef COMPAT_FREEBSD4
209 static void freebsd4_sendsig(sig_t catcher, ksiginfo_t *, sigset_t *mask);
210 #endif
211
212 long Maxmem = 0;
213 long realmem = 0;
214
215 #ifdef PAE
216 FEATURE(pae, "Physical Address Extensions");
217 #endif
218
219 /*
220 * The number of PHYSMAP entries must be one less than the number of
221 * PHYSSEG entries because the PHYSMAP entry that spans the largest
222 * physical address that is accessible by ISA DMA is split into two
223 * PHYSSEG entries.
224 */
225 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
226
227 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
228 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
229
230 /* must be 2 less so 0 0 can signal end of chunks */
231 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2)
232 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2)
233
234 struct kva_md_info kmi;
235
236 static struct trapframe proc0_tf;
237 struct pcpu __pcpu[MAXCPU];
238
239 struct mtx icu_lock;
240
241 struct mem_range_softc mem_range_softc;
242
243 static void
244 cpu_startup(dummy)
245 void *dummy;
246 {
247 uintmax_t memsize;
248 char *sysenv;
249
250 /*
251 * On MacBooks, we need to disallow the legacy USB circuit to
252 * generate an SMI# because this can cause several problems,
253 * namely: incorrect CPU frequency detection and failure to
254 * start the APs.
255 * We do this by disabling a bit in the SMI_EN (SMI Control and
256 * Enable register) of the Intel ICH LPC Interface Bridge.
257 */
258 sysenv = getenv("smbios.system.product");
259 if (sysenv != NULL) {
260 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
261 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
262 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
263 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
264 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
265 strncmp(sysenv, "Macmini1,1", 10) == 0) {
266 if (bootverbose)
267 printf("Disabling LEGACY_USB_EN bit on "
268 "Intel ICH.\n");
269 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
270 }
271 freeenv(sysenv);
272 }
273
274 /*
275 * Good {morning,afternoon,evening,night}.
276 */
277 startrtclock();
278 printcpuinfo();
279 panicifcpuunsupported();
280 #ifdef PERFMON
281 perfmon_init();
282 #endif
283 realmem = Maxmem;
284
285 /*
286 * Display physical memory if SMBIOS reports reasonable amount.
287 */
288 memsize = 0;
289 sysenv = getenv("smbios.memory.enabled");
290 if (sysenv != NULL) {
291 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
292 freeenv(sysenv);
293 }
294 if (memsize < ptoa((uintmax_t)cnt.v_free_count))
295 memsize = ptoa((uintmax_t)Maxmem);
296 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
297
298 /*
299 * Display any holes after the first chunk of extended memory.
300 */
301 if (bootverbose) {
302 int indx;
303
304 printf("Physical memory chunk(s):\n");
305 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
306 vm_paddr_t size;
307
308 size = phys_avail[indx + 1] - phys_avail[indx];
309 printf(
310 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
311 (uintmax_t)phys_avail[indx],
312 (uintmax_t)phys_avail[indx + 1] - 1,
313 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
314 }
315 }
316
317 vm_ksubmap_init(&kmi);
318
319 printf("avail memory = %ju (%ju MB)\n",
320 ptoa((uintmax_t)cnt.v_free_count),
321 ptoa((uintmax_t)cnt.v_free_count) / 1048576);
322
323 /*
324 * Set up buffers, so they can be used to read disk labels.
325 */
326 bufinit();
327 vm_pager_bufferinit();
328 #ifndef XEN
329 cpu_setregs();
330 #endif
331 mca_init();
332 }
333
334 /*
335 * Send an interrupt to process.
336 *
337 * Stack is set up to allow sigcode stored
338 * at top to call routine, followed by kcall
339 * to sigreturn routine below. After sigreturn
340 * resets the signal mask, the stack, and the
341 * frame pointer, it returns to the user
342 * specified pc, psl.
343 */
344 #ifdef COMPAT_43
345 static void
346 osendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
347 {
348 struct osigframe sf, *fp;
349 struct proc *p;
350 struct thread *td;
351 struct sigacts *psp;
352 struct trapframe *regs;
353 int sig;
354 int oonstack;
355
356 td = curthread;
357 p = td->td_proc;
358 PROC_LOCK_ASSERT(p, MA_OWNED);
359 sig = ksi->ksi_signo;
360 psp = p->p_sigacts;
361 mtx_assert(&psp->ps_mtx, MA_OWNED);
362 regs = td->td_frame;
363 oonstack = sigonstack(regs->tf_esp);
364
365 /* Allocate space for the signal handler context. */
366 if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
367 SIGISMEMBER(psp->ps_sigonstack, sig)) {
368 fp = (struct osigframe *)(td->td_sigstk.ss_sp +
369 td->td_sigstk.ss_size - sizeof(struct osigframe));
370 #if defined(COMPAT_43)
371 td->td_sigstk.ss_flags |= SS_ONSTACK;
372 #endif
373 } else
374 fp = (struct osigframe *)regs->tf_esp - 1;
375
376 /* Translate the signal if appropriate. */
377 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
378 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
379
380 /* Build the argument list for the signal handler. */
381 sf.sf_signum = sig;
382 sf.sf_scp = (register_t)&fp->sf_siginfo.si_sc;
383 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
384 /* Signal handler installed with SA_SIGINFO. */
385 sf.sf_arg2 = (register_t)&fp->sf_siginfo;
386 sf.sf_siginfo.si_signo = sig;
387 sf.sf_siginfo.si_code = ksi->ksi_code;
388 sf.sf_ahu.sf_action = (__osiginfohandler_t *)catcher;
389 } else {
390 /* Old FreeBSD-style arguments. */
391 sf.sf_arg2 = ksi->ksi_code;
392 sf.sf_addr = (register_t)ksi->ksi_addr;
393 sf.sf_ahu.sf_handler = catcher;
394 }
395 mtx_unlock(&psp->ps_mtx);
396 PROC_UNLOCK(p);
397
398 /* Save most if not all of trap frame. */
399 sf.sf_siginfo.si_sc.sc_eax = regs->tf_eax;
400 sf.sf_siginfo.si_sc.sc_ebx = regs->tf_ebx;
401 sf.sf_siginfo.si_sc.sc_ecx = regs->tf_ecx;
402 sf.sf_siginfo.si_sc.sc_edx = regs->tf_edx;
403 sf.sf_siginfo.si_sc.sc_esi = regs->tf_esi;
404 sf.sf_siginfo.si_sc.sc_edi = regs->tf_edi;
405 sf.sf_siginfo.si_sc.sc_cs = regs->tf_cs;
406 sf.sf_siginfo.si_sc.sc_ds = regs->tf_ds;
407 sf.sf_siginfo.si_sc.sc_ss = regs->tf_ss;
408 sf.sf_siginfo.si_sc.sc_es = regs->tf_es;
409 sf.sf_siginfo.si_sc.sc_fs = regs->tf_fs;
410 sf.sf_siginfo.si_sc.sc_gs = rgs();
411 sf.sf_siginfo.si_sc.sc_isp = regs->tf_isp;
412
413 /* Build the signal context to be used by osigreturn(). */
414 sf.sf_siginfo.si_sc.sc_onstack = (oonstack) ? 1 : 0;
415 SIG2OSIG(*mask, sf.sf_siginfo.si_sc.sc_mask);
416 sf.sf_siginfo.si_sc.sc_sp = regs->tf_esp;
417 sf.sf_siginfo.si_sc.sc_fp = regs->tf_ebp;
418 sf.sf_siginfo.si_sc.sc_pc = regs->tf_eip;
419 sf.sf_siginfo.si_sc.sc_ps = regs->tf_eflags;
420 sf.sf_siginfo.si_sc.sc_trapno = regs->tf_trapno;
421 sf.sf_siginfo.si_sc.sc_err = regs->tf_err;
422
423 /*
424 * If we're a vm86 process, we want to save the segment registers.
425 * We also change eflags to be our emulated eflags, not the actual
426 * eflags.
427 */
428 if (regs->tf_eflags & PSL_VM) {
429 /* XXX confusing names: `tf' isn't a trapframe; `regs' is. */
430 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
431 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
432
433 sf.sf_siginfo.si_sc.sc_gs = tf->tf_vm86_gs;
434 sf.sf_siginfo.si_sc.sc_fs = tf->tf_vm86_fs;
435 sf.sf_siginfo.si_sc.sc_es = tf->tf_vm86_es;
436 sf.sf_siginfo.si_sc.sc_ds = tf->tf_vm86_ds;
437
438 if (vm86->vm86_has_vme == 0)
439 sf.sf_siginfo.si_sc.sc_ps =
440 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
441 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
442
443 /* See sendsig() for comments. */
444 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
445 }
446
447 /*
448 * Copy the sigframe out to the user's stack.
449 */
450 if (copyout(&sf, fp, sizeof(*fp)) != 0) {
451 #ifdef DEBUG
452 printf("process %ld has trashed its stack\n", (long)p->p_pid);
453 #endif
454 PROC_LOCK(p);
455 sigexit(td, SIGILL);
456 }
457
458 regs->tf_esp = (int)fp;
459 regs->tf_eip = PS_STRINGS - szosigcode;
460 regs->tf_eflags &= ~(PSL_T | PSL_D);
461 regs->tf_cs = _ucodesel;
462 regs->tf_ds = _udatasel;
463 regs->tf_es = _udatasel;
464 regs->tf_fs = _udatasel;
465 load_gs(_udatasel);
466 regs->tf_ss = _udatasel;
467 PROC_LOCK(p);
468 mtx_lock(&psp->ps_mtx);
469 }
470 #endif /* COMPAT_43 */
471
472 #ifdef COMPAT_FREEBSD4
473 static void
474 freebsd4_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
475 {
476 struct sigframe4 sf, *sfp;
477 struct proc *p;
478 struct thread *td;
479 struct sigacts *psp;
480 struct trapframe *regs;
481 int sig;
482 int oonstack;
483
484 td = curthread;
485 p = td->td_proc;
486 PROC_LOCK_ASSERT(p, MA_OWNED);
487 sig = ksi->ksi_signo;
488 psp = p->p_sigacts;
489 mtx_assert(&psp->ps_mtx, MA_OWNED);
490 regs = td->td_frame;
491 oonstack = sigonstack(regs->tf_esp);
492
493 /* Save user context. */
494 bzero(&sf, sizeof(sf));
495 sf.sf_uc.uc_sigmask = *mask;
496 sf.sf_uc.uc_stack = td->td_sigstk;
497 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
498 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
499 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
500 sf.sf_uc.uc_mcontext.mc_gs = rgs();
501 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(*regs));
502
503 /* Allocate space for the signal handler context. */
504 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
505 SIGISMEMBER(psp->ps_sigonstack, sig)) {
506 sfp = (struct sigframe4 *)(td->td_sigstk.ss_sp +
507 td->td_sigstk.ss_size - sizeof(struct sigframe4));
508 #if defined(COMPAT_43)
509 td->td_sigstk.ss_flags |= SS_ONSTACK;
510 #endif
511 } else
512 sfp = (struct sigframe4 *)regs->tf_esp - 1;
513
514 /* Translate the signal if appropriate. */
515 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
516 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
517
518 /* Build the argument list for the signal handler. */
519 sf.sf_signum = sig;
520 sf.sf_ucontext = (register_t)&sfp->sf_uc;
521 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
522 /* Signal handler installed with SA_SIGINFO. */
523 sf.sf_siginfo = (register_t)&sfp->sf_si;
524 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
525
526 /* Fill in POSIX parts */
527 sf.sf_si.si_signo = sig;
528 sf.sf_si.si_code = ksi->ksi_code;
529 sf.sf_si.si_addr = ksi->ksi_addr;
530 } else {
531 /* Old FreeBSD-style arguments. */
532 sf.sf_siginfo = ksi->ksi_code;
533 sf.sf_addr = (register_t)ksi->ksi_addr;
534 sf.sf_ahu.sf_handler = catcher;
535 }
536 mtx_unlock(&psp->ps_mtx);
537 PROC_UNLOCK(p);
538
539 /*
540 * If we're a vm86 process, we want to save the segment registers.
541 * We also change eflags to be our emulated eflags, not the actual
542 * eflags.
543 */
544 if (regs->tf_eflags & PSL_VM) {
545 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
546 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
547
548 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
549 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
550 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
551 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
552
553 if (vm86->vm86_has_vme == 0)
554 sf.sf_uc.uc_mcontext.mc_eflags =
555 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
556 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
557
558 /*
559 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
560 * syscalls made by the signal handler. This just avoids
561 * wasting time for our lazy fixup of such faults. PSL_NT
562 * does nothing in vm86 mode, but vm86 programs can set it
563 * almost legitimately in probes for old cpu types.
564 */
565 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
566 }
567
568 /*
569 * Copy the sigframe out to the user's stack.
570 */
571 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) {
572 #ifdef DEBUG
573 printf("process %ld has trashed its stack\n", (long)p->p_pid);
574 #endif
575 PROC_LOCK(p);
576 sigexit(td, SIGILL);
577 }
578
579 regs->tf_esp = (int)sfp;
580 regs->tf_eip = PS_STRINGS - szfreebsd4_sigcode;
581 regs->tf_eflags &= ~(PSL_T | PSL_D);
582 regs->tf_cs = _ucodesel;
583 regs->tf_ds = _udatasel;
584 regs->tf_es = _udatasel;
585 regs->tf_fs = _udatasel;
586 regs->tf_ss = _udatasel;
587 PROC_LOCK(p);
588 mtx_lock(&psp->ps_mtx);
589 }
590 #endif /* COMPAT_FREEBSD4 */
591
592 void
593 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
594 {
595 struct sigframe sf, *sfp;
596 struct proc *p;
597 struct thread *td;
598 struct sigacts *psp;
599 char *sp;
600 struct trapframe *regs;
601 struct segment_descriptor *sdp;
602 int sig;
603 int oonstack;
604
605 td = curthread;
606 p = td->td_proc;
607 PROC_LOCK_ASSERT(p, MA_OWNED);
608 sig = ksi->ksi_signo;
609 psp = p->p_sigacts;
610 mtx_assert(&psp->ps_mtx, MA_OWNED);
611 #ifdef COMPAT_FREEBSD4
612 if (SIGISMEMBER(psp->ps_freebsd4, sig)) {
613 freebsd4_sendsig(catcher, ksi, mask);
614 return;
615 }
616 #endif
617 #ifdef COMPAT_43
618 if (SIGISMEMBER(psp->ps_osigset, sig)) {
619 osendsig(catcher, ksi, mask);
620 return;
621 }
622 #endif
623 regs = td->td_frame;
624 oonstack = sigonstack(regs->tf_esp);
625
626 /* Save user context. */
627 bzero(&sf, sizeof(sf));
628 sf.sf_uc.uc_sigmask = *mask;
629 sf.sf_uc.uc_stack = td->td_sigstk;
630 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
631 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
632 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
633 sf.sf_uc.uc_mcontext.mc_gs = rgs();
634 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(*regs));
635 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */
636 get_fpcontext(td, &sf.sf_uc.uc_mcontext);
637 fpstate_drop(td);
638 /*
639 * Unconditionally fill the fsbase and gsbase into the mcontext.
640 */
641 sdp = &td->td_pcb->pcb_gsd;
642 sf.sf_uc.uc_mcontext.mc_fsbase = sdp->sd_hibase << 24 |
643 sdp->sd_lobase;
644 sdp = &td->td_pcb->pcb_fsd;
645 sf.sf_uc.uc_mcontext.mc_gsbase = sdp->sd_hibase << 24 |
646 sdp->sd_lobase;
647
648 /* Allocate space for the signal handler context. */
649 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
650 SIGISMEMBER(psp->ps_sigonstack, sig)) {
651 sp = td->td_sigstk.ss_sp +
652 td->td_sigstk.ss_size - sizeof(struct sigframe);
653 #if defined(COMPAT_43)
654 td->td_sigstk.ss_flags |= SS_ONSTACK;
655 #endif
656 } else
657 sp = (char *)regs->tf_esp - sizeof(struct sigframe);
658 /* Align to 16 bytes. */
659 sfp = (struct sigframe *)((unsigned int)sp & ~0xF);
660
661 /* Translate the signal if appropriate. */
662 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
663 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
664
665 /* Build the argument list for the signal handler. */
666 sf.sf_signum = sig;
667 sf.sf_ucontext = (register_t)&sfp->sf_uc;
668 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
669 /* Signal handler installed with SA_SIGINFO. */
670 sf.sf_siginfo = (register_t)&sfp->sf_si;
671 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
672
673 /* Fill in POSIX parts */
674 sf.sf_si = ksi->ksi_info;
675 sf.sf_si.si_signo = sig; /* maybe a translated signal */
676 } else {
677 /* Old FreeBSD-style arguments. */
678 sf.sf_siginfo = ksi->ksi_code;
679 sf.sf_addr = (register_t)ksi->ksi_addr;
680 sf.sf_ahu.sf_handler = catcher;
681 }
682 mtx_unlock(&psp->ps_mtx);
683 PROC_UNLOCK(p);
684
685 /*
686 * If we're a vm86 process, we want to save the segment registers.
687 * We also change eflags to be our emulated eflags, not the actual
688 * eflags.
689 */
690 if (regs->tf_eflags & PSL_VM) {
691 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
692 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
693
694 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
695 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
696 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
697 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
698
699 if (vm86->vm86_has_vme == 0)
700 sf.sf_uc.uc_mcontext.mc_eflags =
701 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
702 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
703
704 /*
705 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
706 * syscalls made by the signal handler. This just avoids
707 * wasting time for our lazy fixup of such faults. PSL_NT
708 * does nothing in vm86 mode, but vm86 programs can set it
709 * almost legitimately in probes for old cpu types.
710 */
711 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
712 }
713
714 /*
715 * Copy the sigframe out to the user's stack.
716 */
717 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) {
718 #ifdef DEBUG
719 printf("process %ld has trashed its stack\n", (long)p->p_pid);
720 #endif
721 PROC_LOCK(p);
722 sigexit(td, SIGILL);
723 }
724
725 regs->tf_esp = (int)sfp;
726 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
727 regs->tf_eflags &= ~(PSL_T | PSL_D);
728 regs->tf_cs = _ucodesel;
729 regs->tf_ds = _udatasel;
730 regs->tf_es = _udatasel;
731 regs->tf_fs = _udatasel;
732 regs->tf_ss = _udatasel;
733 PROC_LOCK(p);
734 mtx_lock(&psp->ps_mtx);
735 }
736
737 /*
738 * System call to cleanup state after a signal
739 * has been taken. Reset signal mask and
740 * stack state from context left by sendsig (above).
741 * Return to previous pc and psl as specified by
742 * context left by sendsig. Check carefully to
743 * make sure that the user has not modified the
744 * state to gain improper privileges.
745 *
746 * MPSAFE
747 */
748 #ifdef COMPAT_43
749 int
750 osigreturn(td, uap)
751 struct thread *td;
752 struct osigreturn_args /* {
753 struct osigcontext *sigcntxp;
754 } */ *uap;
755 {
756 struct osigcontext sc;
757 struct trapframe *regs;
758 struct osigcontext *scp;
759 int eflags, error;
760 ksiginfo_t ksi;
761
762 regs = td->td_frame;
763 error = copyin(uap->sigcntxp, &sc, sizeof(sc));
764 if (error != 0)
765 return (error);
766 scp = ≻
767 eflags = scp->sc_ps;
768 if (eflags & PSL_VM) {
769 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
770 struct vm86_kernel *vm86;
771
772 /*
773 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
774 * set up the vm86 area, and we can't enter vm86 mode.
775 */
776 if (td->td_pcb->pcb_ext == 0)
777 return (EINVAL);
778 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
779 if (vm86->vm86_inited == 0)
780 return (EINVAL);
781
782 /* Go back to user mode if both flags are set. */
783 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
784 ksiginfo_init_trap(&ksi);
785 ksi.ksi_signo = SIGBUS;
786 ksi.ksi_code = BUS_OBJERR;
787 ksi.ksi_addr = (void *)regs->tf_eip;
788 trapsignal(td, &ksi);
789 }
790
791 if (vm86->vm86_has_vme) {
792 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
793 (eflags & VME_USERCHANGE) | PSL_VM;
794 } else {
795 vm86->vm86_eflags = eflags; /* save VIF, VIP */
796 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
797 (eflags & VM_USERCHANGE) | PSL_VM;
798 }
799 tf->tf_vm86_ds = scp->sc_ds;
800 tf->tf_vm86_es = scp->sc_es;
801 tf->tf_vm86_fs = scp->sc_fs;
802 tf->tf_vm86_gs = scp->sc_gs;
803 tf->tf_ds = _udatasel;
804 tf->tf_es = _udatasel;
805 tf->tf_fs = _udatasel;
806 } else {
807 /*
808 * Don't allow users to change privileged or reserved flags.
809 */
810 /*
811 * XXX do allow users to change the privileged flag PSL_RF.
812 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
813 * should sometimes set it there too. tf_eflags is kept in
814 * the signal context during signal handling and there is no
815 * other place to remember it, so the PSL_RF bit may be
816 * corrupted by the signal handler without us knowing.
817 * Corruption of the PSL_RF bit at worst causes one more or
818 * one less debugger trap, so allowing it is fairly harmless.
819 */
820 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
821 return (EINVAL);
822 }
823
824 /*
825 * Don't allow users to load a valid privileged %cs. Let the
826 * hardware check for invalid selectors, excess privilege in
827 * other selectors, invalid %eip's and invalid %esp's.
828 */
829 if (!CS_SECURE(scp->sc_cs)) {
830 ksiginfo_init_trap(&ksi);
831 ksi.ksi_signo = SIGBUS;
832 ksi.ksi_code = BUS_OBJERR;
833 ksi.ksi_trapno = T_PROTFLT;
834 ksi.ksi_addr = (void *)regs->tf_eip;
835 trapsignal(td, &ksi);
836 return (EINVAL);
837 }
838 regs->tf_ds = scp->sc_ds;
839 regs->tf_es = scp->sc_es;
840 regs->tf_fs = scp->sc_fs;
841 }
842
843 /* Restore remaining registers. */
844 regs->tf_eax = scp->sc_eax;
845 regs->tf_ebx = scp->sc_ebx;
846 regs->tf_ecx = scp->sc_ecx;
847 regs->tf_edx = scp->sc_edx;
848 regs->tf_esi = scp->sc_esi;
849 regs->tf_edi = scp->sc_edi;
850 regs->tf_cs = scp->sc_cs;
851 regs->tf_ss = scp->sc_ss;
852 regs->tf_isp = scp->sc_isp;
853 regs->tf_ebp = scp->sc_fp;
854 regs->tf_esp = scp->sc_sp;
855 regs->tf_eip = scp->sc_pc;
856 regs->tf_eflags = eflags;
857
858 #if defined(COMPAT_43)
859 if (scp->sc_onstack & 1)
860 td->td_sigstk.ss_flags |= SS_ONSTACK;
861 else
862 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
863 #endif
864 kern_sigprocmask(td, SIG_SETMASK, (sigset_t *)&scp->sc_mask, NULL,
865 SIGPROCMASK_OLD);
866 return (EJUSTRETURN);
867 }
868 #endif /* COMPAT_43 */
869
870 #ifdef COMPAT_FREEBSD4
871 /*
872 * MPSAFE
873 */
874 int
875 freebsd4_sigreturn(td, uap)
876 struct thread *td;
877 struct freebsd4_sigreturn_args /* {
878 const ucontext4 *sigcntxp;
879 } */ *uap;
880 {
881 struct ucontext4 uc;
882 struct trapframe *regs;
883 struct ucontext4 *ucp;
884 int cs, eflags, error;
885 ksiginfo_t ksi;
886
887 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
888 if (error != 0)
889 return (error);
890 ucp = &uc;
891 regs = td->td_frame;
892 eflags = ucp->uc_mcontext.mc_eflags;
893 if (eflags & PSL_VM) {
894 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
895 struct vm86_kernel *vm86;
896
897 /*
898 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
899 * set up the vm86 area, and we can't enter vm86 mode.
900 */
901 if (td->td_pcb->pcb_ext == 0)
902 return (EINVAL);
903 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
904 if (vm86->vm86_inited == 0)
905 return (EINVAL);
906
907 /* Go back to user mode if both flags are set. */
908 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
909 ksiginfo_init_trap(&ksi);
910 ksi.ksi_signo = SIGBUS;
911 ksi.ksi_code = BUS_OBJERR;
912 ksi.ksi_addr = (void *)regs->tf_eip;
913 trapsignal(td, &ksi);
914 }
915 if (vm86->vm86_has_vme) {
916 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
917 (eflags & VME_USERCHANGE) | PSL_VM;
918 } else {
919 vm86->vm86_eflags = eflags; /* save VIF, VIP */
920 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
921 (eflags & VM_USERCHANGE) | PSL_VM;
922 }
923 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
924 tf->tf_eflags = eflags;
925 tf->tf_vm86_ds = tf->tf_ds;
926 tf->tf_vm86_es = tf->tf_es;
927 tf->tf_vm86_fs = tf->tf_fs;
928 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
929 tf->tf_ds = _udatasel;
930 tf->tf_es = _udatasel;
931 tf->tf_fs = _udatasel;
932 } else {
933 /*
934 * Don't allow users to change privileged or reserved flags.
935 */
936 /*
937 * XXX do allow users to change the privileged flag PSL_RF.
938 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
939 * should sometimes set it there too. tf_eflags is kept in
940 * the signal context during signal handling and there is no
941 * other place to remember it, so the PSL_RF bit may be
942 * corrupted by the signal handler without us knowing.
943 * Corruption of the PSL_RF bit at worst causes one more or
944 * one less debugger trap, so allowing it is fairly harmless.
945 */
946 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
947 uprintf("pid %d (%s): freebsd4_sigreturn eflags = 0x%x\n",
948 td->td_proc->p_pid, td->td_name, eflags);
949 return (EINVAL);
950 }
951
952 /*
953 * Don't allow users to load a valid privileged %cs. Let the
954 * hardware check for invalid selectors, excess privilege in
955 * other selectors, invalid %eip's and invalid %esp's.
956 */
957 cs = ucp->uc_mcontext.mc_cs;
958 if (!CS_SECURE(cs)) {
959 uprintf("pid %d (%s): freebsd4_sigreturn cs = 0x%x\n",
960 td->td_proc->p_pid, td->td_name, cs);
961 ksiginfo_init_trap(&ksi);
962 ksi.ksi_signo = SIGBUS;
963 ksi.ksi_code = BUS_OBJERR;
964 ksi.ksi_trapno = T_PROTFLT;
965 ksi.ksi_addr = (void *)regs->tf_eip;
966 trapsignal(td, &ksi);
967 return (EINVAL);
968 }
969
970 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(*regs));
971 }
972
973 #if defined(COMPAT_43)
974 if (ucp->uc_mcontext.mc_onstack & 1)
975 td->td_sigstk.ss_flags |= SS_ONSTACK;
976 else
977 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
978 #endif
979 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
980 return (EJUSTRETURN);
981 }
982 #endif /* COMPAT_FREEBSD4 */
983
984 /*
985 * MPSAFE
986 */
987 int
988 sigreturn(td, uap)
989 struct thread *td;
990 struct sigreturn_args /* {
991 const struct __ucontext *sigcntxp;
992 } */ *uap;
993 {
994 ucontext_t uc;
995 struct trapframe *regs;
996 ucontext_t *ucp;
997 int cs, eflags, error, ret;
998 ksiginfo_t ksi;
999
1000 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
1001 if (error != 0)
1002 return (error);
1003 ucp = &uc;
1004 regs = td->td_frame;
1005 eflags = ucp->uc_mcontext.mc_eflags;
1006 if (eflags & PSL_VM) {
1007 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
1008 struct vm86_kernel *vm86;
1009
1010 /*
1011 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
1012 * set up the vm86 area, and we can't enter vm86 mode.
1013 */
1014 if (td->td_pcb->pcb_ext == 0)
1015 return (EINVAL);
1016 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
1017 if (vm86->vm86_inited == 0)
1018 return (EINVAL);
1019
1020 /* Go back to user mode if both flags are set. */
1021 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
1022 ksiginfo_init_trap(&ksi);
1023 ksi.ksi_signo = SIGBUS;
1024 ksi.ksi_code = BUS_OBJERR;
1025 ksi.ksi_addr = (void *)regs->tf_eip;
1026 trapsignal(td, &ksi);
1027 }
1028
1029 if (vm86->vm86_has_vme) {
1030 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
1031 (eflags & VME_USERCHANGE) | PSL_VM;
1032 } else {
1033 vm86->vm86_eflags = eflags; /* save VIF, VIP */
1034 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
1035 (eflags & VM_USERCHANGE) | PSL_VM;
1036 }
1037 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
1038 tf->tf_eflags = eflags;
1039 tf->tf_vm86_ds = tf->tf_ds;
1040 tf->tf_vm86_es = tf->tf_es;
1041 tf->tf_vm86_fs = tf->tf_fs;
1042 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
1043 tf->tf_ds = _udatasel;
1044 tf->tf_es = _udatasel;
1045 tf->tf_fs = _udatasel;
1046 } else {
1047 /*
1048 * Don't allow users to change privileged or reserved flags.
1049 */
1050 /*
1051 * XXX do allow users to change the privileged flag PSL_RF.
1052 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
1053 * should sometimes set it there too. tf_eflags is kept in
1054 * the signal context during signal handling and there is no
1055 * other place to remember it, so the PSL_RF bit may be
1056 * corrupted by the signal handler without us knowing.
1057 * Corruption of the PSL_RF bit at worst causes one more or
1058 * one less debugger trap, so allowing it is fairly harmless.
1059 */
1060 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
1061 uprintf("pid %d (%s): sigreturn eflags = 0x%x\n",
1062 td->td_proc->p_pid, td->td_name, eflags);
1063 return (EINVAL);
1064 }
1065
1066 /*
1067 * Don't allow users to load a valid privileged %cs. Let the
1068 * hardware check for invalid selectors, excess privilege in
1069 * other selectors, invalid %eip's and invalid %esp's.
1070 */
1071 cs = ucp->uc_mcontext.mc_cs;
1072 if (!CS_SECURE(cs)) {
1073 uprintf("pid %d (%s): sigreturn cs = 0x%x\n",
1074 td->td_proc->p_pid, td->td_name, cs);
1075 ksiginfo_init_trap(&ksi);
1076 ksi.ksi_signo = SIGBUS;
1077 ksi.ksi_code = BUS_OBJERR;
1078 ksi.ksi_trapno = T_PROTFLT;
1079 ksi.ksi_addr = (void *)regs->tf_eip;
1080 trapsignal(td, &ksi);
1081 return (EINVAL);
1082 }
1083
1084 ret = set_fpcontext(td, &ucp->uc_mcontext);
1085 if (ret != 0)
1086 return (ret);
1087 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(*regs));
1088 }
1089
1090 #if defined(COMPAT_43)
1091 if (ucp->uc_mcontext.mc_onstack & 1)
1092 td->td_sigstk.ss_flags |= SS_ONSTACK;
1093 else
1094 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
1095 #endif
1096
1097 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
1098 return (EJUSTRETURN);
1099 }
1100
1101 /*
1102 * Machine dependent boot() routine
1103 *
1104 * I haven't seen anything to put here yet
1105 * Possibly some stuff might be grafted back here from boot()
1106 */
1107 void
1108 cpu_boot(int howto)
1109 {
1110 }
1111
1112 /*
1113 * Flush the D-cache for non-DMA I/O so that the I-cache can
1114 * be made coherent later.
1115 */
1116 void
1117 cpu_flush_dcache(void *ptr, size_t len)
1118 {
1119 /* Not applicable */
1120 }
1121
1122 /* Get current clock frequency for the given cpu id. */
1123 int
1124 cpu_est_clockrate(int cpu_id, uint64_t *rate)
1125 {
1126 register_t reg;
1127 uint64_t tsc1, tsc2;
1128
1129 if (pcpu_find(cpu_id) == NULL || rate == NULL)
1130 return (EINVAL);
1131 if (!tsc_present)
1132 return (EOPNOTSUPP);
1133
1134 /* If we're booting, trust the rate calibrated moments ago. */
1135 if (cold) {
1136 *rate = tsc_freq;
1137 return (0);
1138 }
1139
1140 #ifdef SMP
1141 /* Schedule ourselves on the indicated cpu. */
1142 thread_lock(curthread);
1143 sched_bind(curthread, cpu_id);
1144 thread_unlock(curthread);
1145 #endif
1146
1147 /* Calibrate by measuring a short delay. */
1148 reg = intr_disable();
1149 tsc1 = rdtsc();
1150 DELAY(1000);
1151 tsc2 = rdtsc();
1152 intr_restore(reg);
1153
1154 #ifdef SMP
1155 thread_lock(curthread);
1156 sched_unbind(curthread);
1157 thread_unlock(curthread);
1158 #endif
1159
1160 /*
1161 * Calculate the difference in readings, convert to Mhz, and
1162 * subtract 0.5% of the total. Empirical testing has shown that
1163 * overhead in DELAY() works out to approximately this value.
1164 */
1165 tsc2 -= tsc1;
1166 *rate = tsc2 * 1000 - tsc2 * 5;
1167 return (0);
1168 }
1169
1170
1171 void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
1172
1173 #ifdef XEN
1174
1175 void
1176 cpu_halt(void)
1177 {
1178 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
1179 }
1180
1181 int scheduler_running;
1182
1183 static void
1184 cpu_idle_hlt(int busy)
1185 {
1186
1187 scheduler_running = 1;
1188 enable_intr();
1189 idle_block();
1190 }
1191
1192 #else
1193 /*
1194 * Shutdown the CPU as much as possible
1195 */
1196 void
1197 cpu_halt(void)
1198 {
1199 for (;;)
1200 __asm__ ("hlt");
1201 }
1202
1203 static void
1204 cpu_idle_hlt(int busy)
1205 {
1206 /*
1207 * we must absolutely guarentee that hlt is the next instruction
1208 * after sti or we introduce a timing window.
1209 */
1210 disable_intr();
1211 if (sched_runnable())
1212 enable_intr();
1213 else
1214 __asm __volatile("sti; hlt");
1215 }
1216 #endif
1217
1218 static void
1219 cpu_idle_acpi(int busy)
1220 {
1221 disable_intr();
1222 if (sched_runnable())
1223 enable_intr();
1224 else if (cpu_idle_hook)
1225 cpu_idle_hook();
1226 else
1227 __asm __volatile("sti; hlt");
1228 }
1229
1230 static int cpu_ident_amdc1e = 0;
1231
1232 static int
1233 cpu_probe_amdc1e(void)
1234 {
1235 #ifdef DEV_APIC
1236 int i;
1237
1238 /*
1239 * Forget it, if we're not using local APIC timer.
1240 */
1241 if (resource_disabled("apic", 0) ||
1242 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0))
1243 return (0);
1244
1245 /*
1246 * Detect the presence of C1E capability mostly on latest
1247 * dual-cores (or future) k8 family.
1248 */
1249 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1250 (cpu_id & 0x00000f00) == 0x00000f00 &&
1251 (cpu_id & 0x0fff0000) >= 0x00040000) {
1252 cpu_ident_amdc1e = 1;
1253 return (1);
1254 }
1255 #endif
1256 return (0);
1257 }
1258
1259 /*
1260 * C1E renders the local APIC timer dead, so we disable it by
1261 * reading the Interrupt Pending Message register and clearing
1262 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
1263 *
1264 * Reference:
1265 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
1266 * #32559 revision 3.00+
1267 */
1268 #define MSR_AMDK8_IPM 0xc0010055
1269 #define AMDK8_SMIONCMPHALT (1ULL << 27)
1270 #define AMDK8_C1EONCMPHALT (1ULL << 28)
1271 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
1272
1273 static void
1274 cpu_idle_amdc1e(int busy)
1275 {
1276
1277 disable_intr();
1278 if (sched_runnable())
1279 enable_intr();
1280 else {
1281 uint64_t msr;
1282
1283 msr = rdmsr(MSR_AMDK8_IPM);
1284 if (msr & AMDK8_CMPHALT)
1285 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
1286
1287 if (cpu_idle_hook)
1288 cpu_idle_hook();
1289 else
1290 __asm __volatile("sti; hlt");
1291 }
1292 }
1293
1294 static void
1295 cpu_idle_spin(int busy)
1296 {
1297 return;
1298 }
1299
1300 #ifdef XEN
1301 void (*cpu_idle_fn)(int) = cpu_idle_hlt;
1302 #else
1303 void (*cpu_idle_fn)(int) = cpu_idle_acpi;
1304 #endif
1305
1306 void
1307 cpu_idle(int busy)
1308 {
1309 #if defined(SMP) && !defined(XEN)
1310 if (mp_grab_cpu_hlt())
1311 return;
1312 #endif
1313 cpu_idle_fn(busy);
1314 }
1315
1316 /*
1317 * mwait cpu power states. Lower 4 bits are sub-states.
1318 */
1319 #define MWAIT_C0 0xf0
1320 #define MWAIT_C1 0x00
1321 #define MWAIT_C2 0x10
1322 #define MWAIT_C3 0x20
1323 #define MWAIT_C4 0x30
1324
1325 #define MWAIT_DISABLED 0x0
1326 #define MWAIT_WOKEN 0x1
1327 #define MWAIT_WAITING 0x2
1328
1329 static void
1330 cpu_idle_mwait(int busy)
1331 {
1332 int *mwait;
1333
1334 mwait = (int *)PCPU_PTR(monitorbuf);
1335 *mwait = MWAIT_WAITING;
1336 if (sched_runnable())
1337 return;
1338 cpu_monitor(mwait, 0, 0);
1339 if (*mwait == MWAIT_WAITING)
1340 cpu_mwait(0, MWAIT_C1);
1341 }
1342
1343 static void
1344 cpu_idle_mwait_hlt(int busy)
1345 {
1346 int *mwait;
1347
1348 mwait = (int *)PCPU_PTR(monitorbuf);
1349 if (busy == 0) {
1350 *mwait = MWAIT_DISABLED;
1351 cpu_idle_hlt(busy);
1352 return;
1353 }
1354 *mwait = MWAIT_WAITING;
1355 if (sched_runnable())
1356 return;
1357 cpu_monitor(mwait, 0, 0);
1358 if (*mwait == MWAIT_WAITING)
1359 cpu_mwait(0, MWAIT_C1);
1360 }
1361
1362 int
1363 cpu_idle_wakeup(int cpu)
1364 {
1365 struct pcpu *pcpu;
1366 int *mwait;
1367
1368 if (cpu_idle_fn == cpu_idle_spin)
1369 return (1);
1370 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt)
1371 return (0);
1372 pcpu = pcpu_find(cpu);
1373 mwait = (int *)pcpu->pc_monitorbuf;
1374 /*
1375 * This doesn't need to be atomic since missing the race will
1376 * simply result in unnecessary IPIs.
1377 */
1378 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED)
1379 return (0);
1380 *mwait = MWAIT_WOKEN;
1381
1382 return (1);
1383 }
1384
1385 /*
1386 * Ordered by speed/power consumption.
1387 */
1388 struct {
1389 void *id_fn;
1390 char *id_name;
1391 } idle_tbl[] = {
1392 { cpu_idle_spin, "spin" },
1393 { cpu_idle_mwait, "mwait" },
1394 { cpu_idle_mwait_hlt, "mwait_hlt" },
1395 { cpu_idle_amdc1e, "amdc1e" },
1396 { cpu_idle_hlt, "hlt" },
1397 { cpu_idle_acpi, "acpi" },
1398 { NULL, NULL }
1399 };
1400
1401 static int
1402 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
1403 {
1404 char *avail, *p;
1405 int error;
1406 int i;
1407
1408 avail = malloc(256, M_TEMP, M_WAITOK);
1409 p = avail;
1410 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1411 if (strstr(idle_tbl[i].id_name, "mwait") &&
1412 (cpu_feature2 & CPUID2_MON) == 0)
1413 continue;
1414 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
1415 cpu_ident_amdc1e == 0)
1416 continue;
1417 p += sprintf(p, "%s, ", idle_tbl[i].id_name);
1418 }
1419 error = sysctl_handle_string(oidp, avail, 0, req);
1420 free(avail, M_TEMP);
1421 return (error);
1422 }
1423
1424 static int
1425 idle_sysctl(SYSCTL_HANDLER_ARGS)
1426 {
1427 char buf[16];
1428 int error;
1429 char *p;
1430 int i;
1431
1432 p = "unknown";
1433 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1434 if (idle_tbl[i].id_fn == cpu_idle_fn) {
1435 p = idle_tbl[i].id_name;
1436 break;
1437 }
1438 }
1439 strncpy(buf, p, sizeof(buf));
1440 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
1441 if (error != 0 || req->newptr == NULL)
1442 return (error);
1443 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1444 if (strstr(idle_tbl[i].id_name, "mwait") &&
1445 (cpu_feature2 & CPUID2_MON) == 0)
1446 continue;
1447 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
1448 cpu_ident_amdc1e == 0)
1449 continue;
1450 if (strcmp(idle_tbl[i].id_name, buf))
1451 continue;
1452 cpu_idle_fn = idle_tbl[i].id_fn;
1453 return (0);
1454 }
1455 return (EINVAL);
1456 }
1457
1458 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
1459 0, 0, idle_sysctl_available, "A", "list of available idle functions");
1460
1461 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
1462 idle_sysctl, "A", "currently selected idle function");
1463
1464 /*
1465 * Reset registers to default values on exec.
1466 */
1467 void
1468 exec_setregs(td, entry, stack, ps_strings)
1469 struct thread *td;
1470 u_long entry;
1471 u_long stack;
1472 u_long ps_strings;
1473 {
1474 struct trapframe *regs = td->td_frame;
1475 struct pcb *pcb = td->td_pcb;
1476
1477 /* Reset pc->pcb_gs and %gs before possibly invalidating it. */
1478 pcb->pcb_gs = _udatasel;
1479 load_gs(_udatasel);
1480
1481 mtx_lock_spin(&dt_lock);
1482 if (td->td_proc->p_md.md_ldt)
1483 user_ldt_free(td);
1484 else
1485 mtx_unlock_spin(&dt_lock);
1486
1487 bzero((char *)regs, sizeof(struct trapframe));
1488 regs->tf_eip = entry;
1489 regs->tf_esp = stack;
1490 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1491 regs->tf_ss = _udatasel;
1492 regs->tf_ds = _udatasel;
1493 regs->tf_es = _udatasel;
1494 regs->tf_fs = _udatasel;
1495 regs->tf_cs = _ucodesel;
1496
1497 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1498 regs->tf_ebx = ps_strings;
1499
1500 /*
1501 * Reset the hardware debug registers if they were in use.
1502 * They won't have any meaning for the newly exec'd process.
1503 */
1504 if (pcb->pcb_flags & PCB_DBREGS) {
1505 pcb->pcb_dr0 = 0;
1506 pcb->pcb_dr1 = 0;
1507 pcb->pcb_dr2 = 0;
1508 pcb->pcb_dr3 = 0;
1509 pcb->pcb_dr6 = 0;
1510 pcb->pcb_dr7 = 0;
1511 if (pcb == PCPU_GET(curpcb)) {
1512 /*
1513 * Clear the debug registers on the running
1514 * CPU, otherwise they will end up affecting
1515 * the next process we switch to.
1516 */
1517 reset_dbregs();
1518 }
1519 pcb->pcb_flags &= ~PCB_DBREGS;
1520 }
1521
1522 /*
1523 * Initialize the math emulator (if any) for the current process.
1524 * Actually, just clear the bit that says that the emulator has
1525 * been initialized. Initialization is delayed until the process
1526 * traps to the emulator (if it is done at all) mainly because
1527 * emulators don't provide an entry point for initialization.
1528 */
1529 td->td_pcb->pcb_flags &= ~FP_SOFTFP;
1530 pcb->pcb_initial_npxcw = __INITIAL_NPXCW__;
1531
1532 /*
1533 * Drop the FP state if we hold it, so that the process gets a
1534 * clean FP state if it uses the FPU again.
1535 */
1536 fpstate_drop(td);
1537
1538 /*
1539 * XXX - Linux emulator
1540 * Make sure sure edx is 0x0 on entry. Linux binaries depend
1541 * on it.
1542 */
1543 td->td_retval[1] = 0;
1544 }
1545
1546 void
1547 cpu_setregs(void)
1548 {
1549 unsigned int cr0;
1550
1551 cr0 = rcr0();
1552
1553 /*
1554 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support:
1555 *
1556 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
1557 * instructions. We must set the CR0_MP bit and use the CR0_TS
1558 * bit to control the trap, because setting the CR0_EM bit does
1559 * not cause WAIT instructions to trap. It's important to trap
1560 * WAIT instructions - otherwise the "wait" variants of no-wait
1561 * control instructions would degenerate to the "no-wait" variants
1562 * after FP context switches but work correctly otherwise. It's
1563 * particularly important to trap WAITs when there is no NPX -
1564 * otherwise the "wait" variants would always degenerate.
1565 *
1566 * Try setting CR0_NE to get correct error reporting on 486DX's.
1567 * Setting it should fail or do nothing on lesser processors.
1568 */
1569 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
1570 load_cr0(cr0);
1571 load_gs(_udatasel);
1572 }
1573
1574 u_long bootdev; /* not a struct cdev *- encoding is different */
1575 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1576 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)");
1577
1578 /*
1579 * Initialize 386 and configure to run kernel
1580 */
1581
1582 /*
1583 * Initialize segments & interrupt table
1584 */
1585
1586 int _default_ldt;
1587
1588 #ifdef XEN
1589 union descriptor *gdt;
1590 union descriptor *ldt;
1591 #else
1592 union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1593 union descriptor ldt[NLDT]; /* local descriptor table */
1594 #endif
1595 static struct gate_descriptor idt0[NIDT];
1596 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1597 struct region_descriptor r_gdt, r_idt; /* table descriptors */
1598 struct mtx dt_lock; /* lock for GDT and LDT */
1599
1600 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1601 extern int has_f00f_bug;
1602 #endif
1603
1604 static struct i386tss dblfault_tss;
1605 static char dblfault_stack[PAGE_SIZE];
1606
1607 extern vm_offset_t proc0kstack;
1608
1609
1610 /*
1611 * software prototypes -- in more palatable form.
1612 *
1613 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret
1614 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it)
1615 */
1616 struct soft_segment_descriptor gdt_segs[] = {
1617 /* GNULL_SEL 0 Null Descriptor */
1618 { .ssd_base = 0x0,
1619 .ssd_limit = 0x0,
1620 .ssd_type = 0,
1621 .ssd_dpl = SEL_KPL,
1622 .ssd_p = 0,
1623 .ssd_xx = 0, .ssd_xx1 = 0,
1624 .ssd_def32 = 0,
1625 .ssd_gran = 0 },
1626 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */
1627 { .ssd_base = 0x0,
1628 .ssd_limit = 0xfffff,
1629 .ssd_type = SDT_MEMRWA,
1630 .ssd_dpl = SEL_KPL,
1631 .ssd_p = 1,
1632 .ssd_xx = 0, .ssd_xx1 = 0,
1633 .ssd_def32 = 1,
1634 .ssd_gran = 1 },
1635 /* GUFS_SEL 2 %fs Descriptor for user */
1636 { .ssd_base = 0x0,
1637 .ssd_limit = 0xfffff,
1638 .ssd_type = SDT_MEMRWA,
1639 .ssd_dpl = SEL_UPL,
1640 .ssd_p = 1,
1641 .ssd_xx = 0, .ssd_xx1 = 0,
1642 .ssd_def32 = 1,
1643 .ssd_gran = 1 },
1644 /* GUGS_SEL 3 %gs Descriptor for user */
1645 { .ssd_base = 0x0,
1646 .ssd_limit = 0xfffff,
1647 .ssd_type = SDT_MEMRWA,
1648 .ssd_dpl = SEL_UPL,
1649 .ssd_p = 1,
1650 .ssd_xx = 0, .ssd_xx1 = 0,
1651 .ssd_def32 = 1,
1652 .ssd_gran = 1 },
1653 /* GCODE_SEL 4 Code Descriptor for kernel */
1654 { .ssd_base = 0x0,
1655 .ssd_limit = 0xfffff,
1656 .ssd_type = SDT_MEMERA,
1657 .ssd_dpl = SEL_KPL,
1658 .ssd_p = 1,
1659 .ssd_xx = 0, .ssd_xx1 = 0,
1660 .ssd_def32 = 1,
1661 .ssd_gran = 1 },
1662 /* GDATA_SEL 5 Data Descriptor for kernel */
1663 { .ssd_base = 0x0,
1664 .ssd_limit = 0xfffff,
1665 .ssd_type = SDT_MEMRWA,
1666 .ssd_dpl = SEL_KPL,
1667 .ssd_p = 1,
1668 .ssd_xx = 0, .ssd_xx1 = 0,
1669 .ssd_def32 = 1,
1670 .ssd_gran = 1 },
1671 /* GUCODE_SEL 6 Code Descriptor for user */
1672 { .ssd_base = 0x0,
1673 .ssd_limit = 0xfffff,
1674 .ssd_type = SDT_MEMERA,
1675 .ssd_dpl = SEL_UPL,
1676 .ssd_p = 1,
1677 .ssd_xx = 0, .ssd_xx1 = 0,
1678 .ssd_def32 = 1,
1679 .ssd_gran = 1 },
1680 /* GUDATA_SEL 7 Data Descriptor for user */
1681 { .ssd_base = 0x0,
1682 .ssd_limit = 0xfffff,
1683 .ssd_type = SDT_MEMRWA,
1684 .ssd_dpl = SEL_UPL,
1685 .ssd_p = 1,
1686 .ssd_xx = 0, .ssd_xx1 = 0,
1687 .ssd_def32 = 1,
1688 .ssd_gran = 1 },
1689 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1690 { .ssd_base = 0x400,
1691 .ssd_limit = 0xfffff,
1692 .ssd_type = SDT_MEMRWA,
1693 .ssd_dpl = SEL_KPL,
1694 .ssd_p = 1,
1695 .ssd_xx = 0, .ssd_xx1 = 0,
1696 .ssd_def32 = 1,
1697 .ssd_gran = 1 },
1698 #ifndef XEN
1699 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
1700 {
1701 .ssd_base = 0x0,
1702 .ssd_limit = sizeof(struct i386tss)-1,
1703 .ssd_type = SDT_SYS386TSS,
1704 .ssd_dpl = 0,
1705 .ssd_p = 1,
1706 .ssd_xx = 0, .ssd_xx1 = 0,
1707 .ssd_def32 = 0,
1708 .ssd_gran = 0 },
1709 /* GLDT_SEL 10 LDT Descriptor */
1710 { .ssd_base = (int) ldt,
1711 .ssd_limit = sizeof(ldt)-1,
1712 .ssd_type = SDT_SYSLDT,
1713 .ssd_dpl = SEL_UPL,
1714 .ssd_p = 1,
1715 .ssd_xx = 0, .ssd_xx1 = 0,
1716 .ssd_def32 = 0,
1717 .ssd_gran = 0 },
1718 /* GUSERLDT_SEL 11 User LDT Descriptor per process */
1719 { .ssd_base = (int) ldt,
1720 .ssd_limit = (512 * sizeof(union descriptor)-1),
1721 .ssd_type = SDT_SYSLDT,
1722 .ssd_dpl = 0,
1723 .ssd_p = 1,
1724 .ssd_xx = 0, .ssd_xx1 = 0,
1725 .ssd_def32 = 0,
1726 .ssd_gran = 0 },
1727 /* GPANIC_SEL 12 Panic Tss Descriptor */
1728 { .ssd_base = (int) &dblfault_tss,
1729 .ssd_limit = sizeof(struct i386tss)-1,
1730 .ssd_type = SDT_SYS386TSS,
1731 .ssd_dpl = 0,
1732 .ssd_p = 1,
1733 .ssd_xx = 0, .ssd_xx1 = 0,
1734 .ssd_def32 = 0,
1735 .ssd_gran = 0 },
1736 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */
1737 { .ssd_base = 0,
1738 .ssd_limit = 0xfffff,
1739 .ssd_type = SDT_MEMERA,
1740 .ssd_dpl = 0,
1741 .ssd_p = 1,
1742 .ssd_xx = 0, .ssd_xx1 = 0,
1743 .ssd_def32 = 0,
1744 .ssd_gran = 1 },
1745 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */
1746 { .ssd_base = 0,
1747 .ssd_limit = 0xfffff,
1748 .ssd_type = SDT_MEMERA,
1749 .ssd_dpl = 0,
1750 .ssd_p = 1,
1751 .ssd_xx = 0, .ssd_xx1 = 0,
1752 .ssd_def32 = 0,
1753 .ssd_gran = 1 },
1754 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */
1755 { .ssd_base = 0,
1756 .ssd_limit = 0xfffff,
1757 .ssd_type = SDT_MEMRWA,
1758 .ssd_dpl = 0,
1759 .ssd_p = 1,
1760 .ssd_xx = 0, .ssd_xx1 = 0,
1761 .ssd_def32 = 1,
1762 .ssd_gran = 1 },
1763 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */
1764 { .ssd_base = 0,
1765 .ssd_limit = 0xfffff,
1766 .ssd_type = SDT_MEMRWA,
1767 .ssd_dpl = 0,
1768 .ssd_p = 1,
1769 .ssd_xx = 0, .ssd_xx1 = 0,
1770 .ssd_def32 = 0,
1771 .ssd_gran = 1 },
1772 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */
1773 { .ssd_base = 0,
1774 .ssd_limit = 0xfffff,
1775 .ssd_type = SDT_MEMRWA,
1776 .ssd_dpl = 0,
1777 .ssd_p = 1,
1778 .ssd_xx = 0, .ssd_xx1 = 0,
1779 .ssd_def32 = 0,
1780 .ssd_gran = 1 },
1781 /* GNDIS_SEL 18 NDIS Descriptor */
1782 { .ssd_base = 0x0,
1783 .ssd_limit = 0x0,
1784 .ssd_type = 0,
1785 .ssd_dpl = 0,
1786 .ssd_p = 0,
1787 .ssd_xx = 0, .ssd_xx1 = 0,
1788 .ssd_def32 = 0,
1789 .ssd_gran = 0 },
1790 #endif /* !XEN */
1791 };
1792
1793 static struct soft_segment_descriptor ldt_segs[] = {
1794 /* Null Descriptor - overwritten by call gate */
1795 { .ssd_base = 0x0,
1796 .ssd_limit = 0x0,
1797 .ssd_type = 0,
1798 .ssd_dpl = 0,
1799 .ssd_p = 0,
1800 .ssd_xx = 0, .ssd_xx1 = 0,
1801 .ssd_def32 = 0,
1802 .ssd_gran = 0 },
1803 /* Null Descriptor - overwritten by call gate */
1804 { .ssd_base = 0x0,
1805 .ssd_limit = 0x0,
1806 .ssd_type = 0,
1807 .ssd_dpl = 0,
1808 .ssd_p = 0,
1809 .ssd_xx = 0, .ssd_xx1 = 0,
1810 .ssd_def32 = 0,
1811 .ssd_gran = 0 },
1812 /* Null Descriptor - overwritten by call gate */
1813 { .ssd_base = 0x0,
1814 .ssd_limit = 0x0,
1815 .ssd_type = 0,
1816 .ssd_dpl = 0,
1817 .ssd_p = 0,
1818 .ssd_xx = 0, .ssd_xx1 = 0,
1819 .ssd_def32 = 0,
1820 .ssd_gran = 0 },
1821 /* Code Descriptor for user */
1822 { .ssd_base = 0x0,
1823 .ssd_limit = 0xfffff,
1824 .ssd_type = SDT_MEMERA,
1825 .ssd_dpl = SEL_UPL,
1826 .ssd_p = 1,
1827 .ssd_xx = 0, .ssd_xx1 = 0,
1828 .ssd_def32 = 1,
1829 .ssd_gran = 1 },
1830 /* Null Descriptor - overwritten by call gate */
1831 { .ssd_base = 0x0,
1832 .ssd_limit = 0x0,
1833 .ssd_type = 0,
1834 .ssd_dpl = 0,
1835 .ssd_p = 0,
1836 .ssd_xx = 0, .ssd_xx1 = 0,
1837 .ssd_def32 = 0,
1838 .ssd_gran = 0 },
1839 /* Data Descriptor for user */
1840 { .ssd_base = 0x0,
1841 .ssd_limit = 0xfffff,
1842 .ssd_type = SDT_MEMRWA,
1843 .ssd_dpl = SEL_UPL,
1844 .ssd_p = 1,
1845 .ssd_xx = 0, .ssd_xx1 = 0,
1846 .ssd_def32 = 1,
1847 .ssd_gran = 1 },
1848 };
1849
1850 void
1851 setidt(idx, func, typ, dpl, selec)
1852 int idx;
1853 inthand_t *func;
1854 int typ;
1855 int dpl;
1856 int selec;
1857 {
1858 struct gate_descriptor *ip;
1859
1860 ip = idt + idx;
1861 ip->gd_looffset = (int)func;
1862 ip->gd_selector = selec;
1863 ip->gd_stkcpy = 0;
1864 ip->gd_xx = 0;
1865 ip->gd_type = typ;
1866 ip->gd_dpl = dpl;
1867 ip->gd_p = 1;
1868 ip->gd_hioffset = ((int)func)>>16 ;
1869 }
1870
1871 extern inthand_t
1872 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1873 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1874 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1875 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1876 IDTVEC(xmm), IDTVEC(lcall_syscall), IDTVEC(int0x80_syscall);
1877
1878 #ifdef DDB
1879 /*
1880 * Display the index and function name of any IDT entries that don't use
1881 * the default 'rsvd' entry point.
1882 */
1883 DB_SHOW_COMMAND(idt, db_show_idt)
1884 {
1885 struct gate_descriptor *ip;
1886 int idx;
1887 uintptr_t func;
1888
1889 ip = idt;
1890 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
1891 func = (ip->gd_hioffset << 16 | ip->gd_looffset);
1892 if (func != (uintptr_t)&IDTVEC(rsvd)) {
1893 db_printf("%3d\t", idx);
1894 db_printsym(func, DB_STGY_PROC);
1895 db_printf("\n");
1896 }
1897 ip++;
1898 }
1899 }
1900
1901 /* Show privileged registers. */
1902 DB_SHOW_COMMAND(sysregs, db_show_sysregs)
1903 {
1904 uint64_t idtr, gdtr;
1905
1906 idtr = ridt();
1907 db_printf("idtr\t0x%08x/%04x\n",
1908 (u_int)(idtr >> 16), (u_int)idtr & 0xffff);
1909 gdtr = rgdt();
1910 db_printf("gdtr\t0x%08x/%04x\n",
1911 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff);
1912 db_printf("ldtr\t0x%04x\n", rldt());
1913 db_printf("tr\t0x%04x\n", rtr());
1914 db_printf("cr0\t0x%08x\n", rcr0());
1915 db_printf("cr2\t0x%08x\n", rcr2());
1916 db_printf("cr3\t0x%08x\n", rcr3());
1917 db_printf("cr4\t0x%08x\n", rcr4());
1918 }
1919 #endif
1920
1921 void
1922 sdtossd(sd, ssd)
1923 struct segment_descriptor *sd;
1924 struct soft_segment_descriptor *ssd;
1925 {
1926 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1927 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1928 ssd->ssd_type = sd->sd_type;
1929 ssd->ssd_dpl = sd->sd_dpl;
1930 ssd->ssd_p = sd->sd_p;
1931 ssd->ssd_def32 = sd->sd_def32;
1932 ssd->ssd_gran = sd->sd_gran;
1933 }
1934
1935 static int
1936 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
1937 {
1938 int i, insert_idx, physmap_idx;
1939
1940 physmap_idx = *physmap_idxp;
1941
1942 if (boothowto & RB_VERBOSE)
1943 printf("SMAP type=%02x base=%016llx len=%016llx\n",
1944 smap->type, smap->base, smap->length);
1945
1946 if (smap->type != SMAP_TYPE_MEMORY)
1947 return (1);
1948
1949 if (smap->length == 0)
1950 return (1);
1951
1952 #ifndef PAE
1953 if (smap->base >= 0xffffffff) {
1954 printf("%uK of memory above 4GB ignored\n",
1955 (u_int)(smap->length / 1024));
1956 return (1);
1957 }
1958 #endif
1959
1960 /*
1961 * Find insertion point while checking for overlap. Start off by
1962 * assuming the new entry will be added to the end.
1963 */
1964 insert_idx = physmap_idx + 2;
1965 for (i = 0; i <= physmap_idx; i += 2) {
1966 if (smap->base < physmap[i + 1]) {
1967 if (smap->base + smap->length <= physmap[i]) {
1968 insert_idx = i;
1969 break;
1970 }
1971 if (boothowto & RB_VERBOSE)
1972 printf(
1973 "Overlapping memory regions, ignoring second region\n");
1974 return (1);
1975 }
1976 }
1977
1978 /* See if we can prepend to the next entry. */
1979 if (insert_idx <= physmap_idx &&
1980 smap->base + smap->length == physmap[insert_idx]) {
1981 physmap[insert_idx] = smap->base;
1982 return (1);
1983 }
1984
1985 /* See if we can append to the previous entry. */
1986 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) {
1987 physmap[insert_idx - 1] += smap->length;
1988 return (1);
1989 }
1990
1991 physmap_idx += 2;
1992 *physmap_idxp = physmap_idx;
1993 if (physmap_idx == PHYSMAP_SIZE) {
1994 printf(
1995 "Too many segments in the physical address map, giving up\n");
1996 return (0);
1997 }
1998
1999 /*
2000 * Move the last 'N' entries down to make room for the new
2001 * entry if needed.
2002 */
2003 for (i = physmap_idx; i > insert_idx; i -= 2) {
2004 physmap[i] = physmap[i - 2];
2005 physmap[i + 1] = physmap[i - 1];
2006 }
2007
2008 /* Insert the new entry. */
2009 physmap[insert_idx] = smap->base;
2010 physmap[insert_idx + 1] = smap->base + smap->length;
2011 return (1);
2012 }
2013
2014 /*
2015 * Populate the (physmap) array with base/bound pairs describing the
2016 * available physical memory in the system, then test this memory and
2017 * build the phys_avail array describing the actually-available memory.
2018 *
2019 * If we cannot accurately determine the physical memory map, then use
2020 * value from the 0xE801 call, and failing that, the RTC.
2021 *
2022 * Total memory size may be set by the kernel environment variable
2023 * hw.physmem or the compile-time define MAXMEM.
2024 *
2025 * XXX first should be vm_paddr_t.
2026 */
2027 static void
2028 getmemsize(int first)
2029 {
2030 int i, off, physmap_idx, pa_indx, da_indx;
2031 int hasbrokenint12, has_smap;
2032 u_long physmem_tunable;
2033 u_int extmem;
2034 struct vm86frame vmf;
2035 struct vm86context vmc;
2036 vm_paddr_t pa, physmap[PHYSMAP_SIZE];
2037 pt_entry_t *pte;
2038 struct bios_smap *smap, *smapbase, *smapend;
2039 u_int32_t smapsize;
2040 quad_t dcons_addr, dcons_size;
2041 caddr_t kmdp;
2042
2043 has_smap = 0;
2044 #ifdef XBOX
2045 if (arch_i386_is_xbox) {
2046 /*
2047 * We queried the memory size before, so chop off 4MB for
2048 * the framebuffer and inform the OS of this.
2049 */
2050 physmap[0] = 0;
2051 physmap[1] = (arch_i386_xbox_memsize * 1024 * 1024) - XBOX_FB_SIZE;
2052 physmap_idx = 0;
2053 goto physmap_done;
2054 }
2055 #endif
2056 #if defined(XEN)
2057 has_smap = 0;
2058 Maxmem = xen_start_info->nr_pages - init_first;
2059 physmem = Maxmem;
2060 basemem = 0;
2061 physmap[0] = init_first << PAGE_SHIFT;
2062 physmap[1] = ptoa(Maxmem) - round_page(MSGBUF_SIZE);
2063 physmap_idx = 0;
2064 goto physmap_done;
2065 #endif
2066 hasbrokenint12 = 0;
2067 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
2068 bzero(&vmf, sizeof(vmf));
2069 bzero(physmap, sizeof(physmap));
2070 basemem = 0;
2071
2072 /*
2073 * Some newer BIOSes has broken INT 12H implementation which cause
2074 * kernel panic immediately. In this case, we need to scan SMAP
2075 * with INT 15:E820 first, then determine base memory size.
2076 */
2077 if (hasbrokenint12) {
2078 goto int15e820;
2079 }
2080
2081 /*
2082 * Perform "base memory" related probes & setup
2083 */
2084 vm86_intcall(0x12, &vmf);
2085 basemem = vmf.vmf_ax;
2086 if (basemem > 640) {
2087 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
2088 basemem);
2089 basemem = 640;
2090 }
2091
2092 /*
2093 * XXX if biosbasemem is now < 640, there is a `hole'
2094 * between the end of base memory and the start of
2095 * ISA memory. The hole may be empty or it may
2096 * contain BIOS code or data. Map it read/write so
2097 * that the BIOS can write to it. (Memory from 0 to
2098 * the physical end of the kernel is mapped read-only
2099 * to begin with and then parts of it are remapped.
2100 * The parts that aren't remapped form holes that
2101 * remain read-only and are unused by the kernel.
2102 * The base memory area is below the physical end of
2103 * the kernel and right now forms a read-only hole.
2104 * The part of it from PAGE_SIZE to
2105 * (trunc_page(biosbasemem * 1024) - 1) will be
2106 * remapped and used by the kernel later.)
2107 *
2108 * This code is similar to the code used in
2109 * pmap_mapdev, but since no memory needs to be
2110 * allocated we simply change the mapping.
2111 */
2112 for (pa = trunc_page(basemem * 1024);
2113 pa < ISA_HOLE_START; pa += PAGE_SIZE)
2114 pmap_kenter(KERNBASE + pa, pa);
2115
2116 /*
2117 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
2118 * the vm86 page table so that vm86 can scribble on them using
2119 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
2120 * page 0, at least as initialized here?
2121 */
2122 pte = (pt_entry_t *)vm86paddr;
2123 for (i = basemem / 4; i < 160; i++)
2124 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
2125
2126 int15e820:
2127 /*
2128 * Fetch the memory map with INT 15:E820. First, check to see
2129 * if the loader supplied it and use that if so. Otherwise,
2130 * use vm86 to invoke the BIOS call directly.
2131 */
2132 physmap_idx = 0;
2133 smapbase = NULL;
2134 kmdp = preload_search_by_type("elf kernel");
2135 if (kmdp == NULL)
2136 kmdp = preload_search_by_type("elf32 kernel");
2137 if (kmdp != NULL)
2138 smapbase = (struct bios_smap *)preload_search_info(kmdp,
2139 MODINFO_METADATA | MODINFOMD_SMAP);
2140 if (smapbase != NULL) {
2141 /* subr_module.c says:
2142 * "Consumer may safely assume that size value precedes data."
2143 * ie: an int32_t immediately precedes smap.
2144 */
2145 smapsize = *((u_int32_t *)smapbase - 1);
2146 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
2147 has_smap = 1;
2148
2149 for (smap = smapbase; smap < smapend; smap++)
2150 if (!add_smap_entry(smap, physmap, &physmap_idx))
2151 break;
2152 } else {
2153 /*
2154 * map page 1 R/W into the kernel page table so we can use it
2155 * as a buffer. The kernel will unmap this page later.
2156 */
2157 pmap_kenter(KERNBASE + (1 << PAGE_SHIFT), 1 << PAGE_SHIFT);
2158 vmc.npages = 0;
2159 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE +
2160 (1 << PAGE_SHIFT));
2161 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
2162
2163 vmf.vmf_ebx = 0;
2164 do {
2165 vmf.vmf_eax = 0xE820;
2166 vmf.vmf_edx = SMAP_SIG;
2167 vmf.vmf_ecx = sizeof(struct bios_smap);
2168 i = vm86_datacall(0x15, &vmf, &vmc);
2169 if (i || vmf.vmf_eax != SMAP_SIG)
2170 break;
2171 has_smap = 1;
2172 if (!add_smap_entry(smap, physmap, &physmap_idx))
2173 break;
2174 } while (vmf.vmf_ebx != 0);
2175 }
2176
2177 /*
2178 * Perform "base memory" related probes & setup based on SMAP
2179 */
2180 if (basemem == 0) {
2181 for (i = 0; i <= physmap_idx; i += 2) {
2182 if (physmap[i] == 0x00000000) {
2183 basemem = physmap[i + 1] / 1024;
2184 break;
2185 }
2186 }
2187
2188 /*
2189 * XXX this function is horribly organized and has to the same
2190 * things that it does above here.
2191 */
2192 if (basemem == 0)
2193 basemem = 640;
2194 if (basemem > 640) {
2195 printf(
2196 "Preposterous BIOS basemem of %uK, truncating to 640K\n",
2197 basemem);
2198 basemem = 640;
2199 }
2200
2201 /*
2202 * Let vm86 scribble on pages between basemem and
2203 * ISA_HOLE_START, as above.
2204 */
2205 for (pa = trunc_page(basemem * 1024);
2206 pa < ISA_HOLE_START; pa += PAGE_SIZE)
2207 pmap_kenter(KERNBASE + pa, pa);
2208 pte = (pt_entry_t *)vm86paddr;
2209 for (i = basemem / 4; i < 160; i++)
2210 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
2211 }
2212
2213 if (physmap[1] != 0)
2214 goto physmap_done;
2215
2216 /*
2217 * If we failed above, try memory map with INT 15:E801
2218 */
2219 vmf.vmf_ax = 0xE801;
2220 if (vm86_intcall(0x15, &vmf) == 0) {
2221 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
2222 } else {
2223 #if 0
2224 vmf.vmf_ah = 0x88;
2225 vm86_intcall(0x15, &vmf);
2226 extmem = vmf.vmf_ax;
2227 #elif !defined(XEN)
2228 /*
2229 * Prefer the RTC value for extended memory.
2230 */
2231 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
2232 #endif
2233 }
2234
2235 /*
2236 * Special hack for chipsets that still remap the 384k hole when
2237 * there's 16MB of memory - this really confuses people that
2238 * are trying to use bus mastering ISA controllers with the
2239 * "16MB limit"; they only have 16MB, but the remapping puts
2240 * them beyond the limit.
2241 *
2242 * If extended memory is between 15-16MB (16-17MB phys address range),
2243 * chop it to 15MB.
2244 */
2245 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
2246 extmem = 15 * 1024;
2247
2248 physmap[0] = 0;
2249 physmap[1] = basemem * 1024;
2250 physmap_idx = 2;
2251 physmap[physmap_idx] = 0x100000;
2252 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
2253
2254 physmap_done:
2255 /*
2256 * Now, physmap contains a map of physical memory.
2257 */
2258
2259 #ifdef SMP
2260 /* make hole for AP bootstrap code */
2261 physmap[1] = mp_bootaddress(physmap[1]);
2262 #endif
2263
2264 /*
2265 * Maxmem isn't the "maximum memory", it's one larger than the
2266 * highest page of the physical address space. It should be
2267 * called something like "Maxphyspage". We may adjust this
2268 * based on ``hw.physmem'' and the results of the memory test.
2269 */
2270 Maxmem = atop(physmap[physmap_idx + 1]);
2271
2272 #ifdef MAXMEM
2273 Maxmem = MAXMEM / 4;
2274 #endif
2275
2276 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
2277 Maxmem = atop(physmem_tunable);
2278
2279 /*
2280 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend
2281 * the amount of memory in the system.
2282 */
2283 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1]))
2284 Maxmem = atop(physmap[physmap_idx + 1]);
2285
2286 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
2287 (boothowto & RB_VERBOSE))
2288 printf("Physical memory use set to %ldK\n", Maxmem * 4);
2289
2290 /*
2291 * If Maxmem has been increased beyond what the system has detected,
2292 * extend the last memory segment to the new limit.
2293 */
2294 if (atop(physmap[physmap_idx + 1]) < Maxmem)
2295 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
2296
2297 /* call pmap initialization to make new kernel address space */
2298 pmap_bootstrap(first);
2299
2300 /*
2301 * Size up each available chunk of physical memory.
2302 */
2303 physmap[0] = PAGE_SIZE; /* mask off page 0 */
2304 pa_indx = 0;
2305 da_indx = 1;
2306 phys_avail[pa_indx++] = physmap[0];
2307 phys_avail[pa_indx] = physmap[0];
2308 dump_avail[da_indx] = physmap[0];
2309 pte = CMAP1;
2310
2311 /*
2312 * Get dcons buffer address
2313 */
2314 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
2315 getenv_quad("dcons.size", &dcons_size) == 0)
2316 dcons_addr = 0;
2317
2318 #ifndef XEN
2319 /*
2320 * physmap is in bytes, so when converting to page boundaries,
2321 * round up the start address and round down the end address.
2322 */
2323 for (i = 0; i <= physmap_idx; i += 2) {
2324 vm_paddr_t end;
2325
2326 end = ptoa((vm_paddr_t)Maxmem);
2327 if (physmap[i + 1] < end)
2328 end = trunc_page(physmap[i + 1]);
2329 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
2330 int tmp, page_bad, full;
2331 int *ptr = (int *)CADDR1;
2332
2333 full = FALSE;
2334 /*
2335 * block out kernel memory as not available.
2336 */
2337 if (pa >= KERNLOAD && pa < first)
2338 goto do_dump_avail;
2339
2340 /*
2341 * block out dcons buffer
2342 */
2343 if (dcons_addr > 0
2344 && pa >= trunc_page(dcons_addr)
2345 && pa < dcons_addr + dcons_size)
2346 goto do_dump_avail;
2347
2348 page_bad = FALSE;
2349
2350 /*
2351 * map page into kernel: valid, read/write,non-cacheable
2352 */
2353 *pte = pa | PG_V | PG_RW | PG_N;
2354 invltlb();
2355
2356 tmp = *(int *)ptr;
2357 /*
2358 * Test for alternating 1's and 0's
2359 */
2360 *(volatile int *)ptr = 0xaaaaaaaa;
2361 if (*(volatile int *)ptr != 0xaaaaaaaa)
2362 page_bad = TRUE;
2363 /*
2364 * Test for alternating 0's and 1's
2365 */
2366 *(volatile int *)ptr = 0x55555555;
2367 if (*(volatile int *)ptr != 0x55555555)
2368 page_bad = TRUE;
2369 /*
2370 * Test for all 1's
2371 */
2372 *(volatile int *)ptr = 0xffffffff;
2373 if (*(volatile int *)ptr != 0xffffffff)
2374 page_bad = TRUE;
2375 /*
2376 * Test for all 0's
2377 */
2378 *(volatile int *)ptr = 0x0;
2379 if (*(volatile int *)ptr != 0x0)
2380 page_bad = TRUE;
2381 /*
2382 * Restore original value.
2383 */
2384 *(int *)ptr = tmp;
2385
2386 /*
2387 * Adjust array of valid/good pages.
2388 */
2389 if (page_bad == TRUE)
2390 continue;
2391 /*
2392 * If this good page is a continuation of the
2393 * previous set of good pages, then just increase
2394 * the end pointer. Otherwise start a new chunk.
2395 * Note that "end" points one higher than end,
2396 * making the range >= start and < end.
2397 * If we're also doing a speculative memory
2398 * test and we at or past the end, bump up Maxmem
2399 * so that we keep going. The first bad page
2400 * will terminate the loop.
2401 */
2402 if (phys_avail[pa_indx] == pa) {
2403 phys_avail[pa_indx] += PAGE_SIZE;
2404 } else {
2405 pa_indx++;
2406 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2407 printf(
2408 "Too many holes in the physical address space, giving up\n");
2409 pa_indx--;
2410 full = TRUE;
2411 goto do_dump_avail;
2412 }
2413 phys_avail[pa_indx++] = pa; /* start */
2414 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
2415 }
2416 physmem++;
2417 do_dump_avail:
2418 if (dump_avail[da_indx] == pa) {
2419 dump_avail[da_indx] += PAGE_SIZE;
2420 } else {
2421 da_indx++;
2422 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2423 da_indx--;
2424 goto do_next;
2425 }
2426 dump_avail[da_indx++] = pa; /* start */
2427 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
2428 }
2429 do_next:
2430 if (full)
2431 break;
2432 }
2433 }
2434 *pte = 0;
2435 invltlb();
2436 #else
2437 phys_avail[0] = physfree;
2438 phys_avail[1] = xen_start_info->nr_pages*PAGE_SIZE;
2439 #endif
2440
2441 /*
2442 * XXX
2443 * The last chunk must contain at least one page plus the message
2444 * buffer to avoid complicating other code (message buffer address
2445 * calculation, etc.).
2446 */
2447 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
2448 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
2449 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
2450 phys_avail[pa_indx--] = 0;
2451 phys_avail[pa_indx--] = 0;
2452 }
2453
2454 Maxmem = atop(phys_avail[pa_indx]);
2455
2456 /* Trim off space for the message buffer. */
2457 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
2458
2459 /* Map the message buffer. */
2460 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2461 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
2462 off);
2463
2464 PT_UPDATES_FLUSH();
2465 }
2466
2467 #ifdef XEN
2468 #define MTOPSIZE (1<<(14 + PAGE_SHIFT))
2469
2470 void
2471 init386(first)
2472 int first;
2473 {
2474 unsigned long gdtmachpfn;
2475 int error, gsel_tss, metadata_missing, x, pa;
2476 struct pcpu *pc;
2477 struct callback_register event = {
2478 .type = CALLBACKTYPE_event,
2479 .address = {GSEL(GCODE_SEL, SEL_KPL), (unsigned long)Xhypervisor_callback },
2480 };
2481 struct callback_register failsafe = {
2482 .type = CALLBACKTYPE_failsafe,
2483 .address = {GSEL(GCODE_SEL, SEL_KPL), (unsigned long)failsafe_callback },
2484 };
2485
2486 thread0.td_kstack = proc0kstack;
2487 thread0.td_pcb = (struct pcb *)
2488 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
2489
2490 /*
2491 * This may be done better later if it gets more high level
2492 * components in it. If so just link td->td_proc here.
2493 */
2494 proc_linkup0(&proc0, &thread0);
2495
2496 metadata_missing = 0;
2497 if (xen_start_info->mod_start) {
2498 preload_metadata = (caddr_t)xen_start_info->mod_start;
2499 preload_bootstrap_relocate(KERNBASE);
2500 } else {
2501 metadata_missing = 1;
2502 }
2503 if (envmode == 1)
2504 kern_envp = static_env;
2505 else if ((caddr_t)xen_start_info->cmd_line)
2506 kern_envp = xen_setbootenv((caddr_t)xen_start_info->cmd_line);
2507
2508 boothowto |= xen_boothowto(kern_envp);
2509
2510 /* Init basic tunables, hz etc */
2511 init_param1();
2512
2513 /*
2514 * XEN occupies a portion of the upper virtual address space
2515 * At its base it manages an array mapping machine page frames
2516 * to physical page frames - hence we need to be able to
2517 * access 4GB - (64MB - 4MB + 64k)
2518 */
2519 gdt_segs[GPRIV_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2520 gdt_segs[GUFS_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2521 gdt_segs[GUGS_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2522 gdt_segs[GCODE_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2523 gdt_segs[GDATA_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2524 gdt_segs[GUCODE_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2525 gdt_segs[GUDATA_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2526 gdt_segs[GBIOSLOWMEM_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2527
2528 pc = &__pcpu[0];
2529 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
2530 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
2531
2532 PT_SET_MA(gdt, xpmap_ptom(VTOP(gdt)) | PG_V | PG_RW);
2533 bzero(gdt, PAGE_SIZE);
2534 for (x = 0; x < NGDT; x++)
2535 ssdtosd(&gdt_segs[x], &gdt[x].sd);
2536
2537 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
2538
2539 gdtmachpfn = vtomach(gdt) >> PAGE_SHIFT;
2540 PT_SET_MA(gdt, xpmap_ptom(VTOP(gdt)) | PG_V);
2541 PANIC_IF(HYPERVISOR_set_gdt(&gdtmachpfn, 512) != 0);
2542 lgdt(&r_gdt);
2543 gdtset = 1;
2544
2545 if ((error = HYPERVISOR_set_trap_table(trap_table)) != 0) {
2546 panic("set_trap_table failed - error %d\n", error);
2547 }
2548
2549 error = HYPERVISOR_callback_op(CALLBACKOP_register, &event);
2550 if (error == 0)
2551 error = HYPERVISOR_callback_op(CALLBACKOP_register, &failsafe);
2552 #if CONFIG_XEN_COMPAT <= 0x030002
2553 if (error == -ENOXENSYS)
2554 HYPERVISOR_set_callbacks(GSEL(GCODE_SEL, SEL_KPL),
2555 (unsigned long)Xhypervisor_callback,
2556 GSEL(GCODE_SEL, SEL_KPL), (unsigned long)failsafe_callback);
2557 #endif
2558 pcpu_init(pc, 0, sizeof(struct pcpu));
2559 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
2560 pmap_kenter(pa + KERNBASE, pa);
2561 dpcpu_init((void *)(first + KERNBASE), 0);
2562 first += DPCPU_SIZE;
2563
2564 PCPU_SET(prvspace, pc);
2565 PCPU_SET(curthread, &thread0);
2566 PCPU_SET(curpcb, thread0.td_pcb);
2567
2568 /*
2569 * Initialize mutexes.
2570 *
2571 * icu_lock: in order to allow an interrupt to occur in a critical
2572 * section, to set pcpu->ipending (etc...) properly, we
2573 * must be able to get the icu lock, so it can't be
2574 * under witness.
2575 */
2576 mutex_init();
2577 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
2578
2579 /* make ldt memory segments */
2580 PT_SET_MA(ldt, xpmap_ptom(VTOP(ldt)) | PG_V | PG_RW);
2581 bzero(ldt, PAGE_SIZE);
2582 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
2583 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
2584 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
2585 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2586
2587 default_proc_ldt.ldt_base = (caddr_t)ldt;
2588 default_proc_ldt.ldt_len = 6;
2589 _default_ldt = (int)&default_proc_ldt;
2590 PCPU_SET(currentldt, _default_ldt)
2591 PT_SET_MA(ldt, *vtopte((unsigned long)ldt) & ~PG_RW);
2592 xen_set_ldt((unsigned long) ldt, (sizeof ldt_segs / sizeof ldt_segs[0]));
2593
2594 #if defined(XEN_PRIVILEGED)
2595 /*
2596 * Initialize the i8254 before the console so that console
2597 * initialization can use DELAY().
2598 */
2599 i8254_init();
2600 #endif
2601
2602 /*
2603 * Initialize the console before we print anything out.
2604 */
2605 cninit();
2606
2607 if (metadata_missing)
2608 printf("WARNING: loader(8) metadata is missing!\n");
2609
2610 #ifdef DEV_ISA
2611 elcr_probe();
2612 atpic_startup();
2613 #endif
2614
2615 #ifdef DDB
2616 ksym_start = bootinfo.bi_symtab;
2617 ksym_end = bootinfo.bi_esymtab;
2618 #endif
2619
2620 kdb_init();
2621
2622 #ifdef KDB
2623 if (boothowto & RB_KDB)
2624 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
2625 #endif
2626
2627 finishidentcpu(); /* Final stage of CPU initialization */
2628 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
2629 GSEL(GCODE_SEL, SEL_KPL));
2630 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
2631 GSEL(GCODE_SEL, SEL_KPL));
2632 initializecpu(); /* Initialize CPU registers */
2633
2634 /* make an initial tss so cpu can get interrupt stack on syscall! */
2635 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
2636 PCPU_SET(common_tss.tss_esp0, thread0.td_kstack +
2637 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb) - 16);
2638 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
2639 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2640 HYPERVISOR_stack_switch(GSEL(GDATA_SEL, SEL_KPL),
2641 PCPU_GET(common_tss.tss_esp0));
2642
2643 /* pointer to selector slot for %fs/%gs */
2644 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
2645
2646 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2647 dblfault_tss.tss_esp2 = (int)&dblfault_stack[sizeof(dblfault_stack)];
2648 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2649 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2650 #ifdef PAE
2651 dblfault_tss.tss_cr3 = (int)IdlePDPT;
2652 #else
2653 dblfault_tss.tss_cr3 = (int)IdlePTD;
2654 #endif
2655 dblfault_tss.tss_eip = (int)dblfault_handler;
2656 dblfault_tss.tss_eflags = PSL_KERNEL;
2657 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2658 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2659 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2660 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2661 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2662
2663 vm86_initialize();
2664 getmemsize(first);
2665 init_param2(physmem);
2666
2667 /* now running on new page tables, configured,and u/iom is accessible */
2668
2669 msgbufinit(msgbufp, MSGBUF_SIZE);
2670 /* transfer to user mode */
2671
2672 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2673 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2674
2675 /* setup proc 0's pcb */
2676 thread0.td_pcb->pcb_flags = 0;
2677 #ifdef PAE
2678 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
2679 #else
2680 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2681 #endif
2682 thread0.td_pcb->pcb_ext = 0;
2683 thread0.td_frame = &proc0_tf;
2684 thread0.td_pcb->pcb_fsd = PCPU_GET(fsgs_gdt)[0];
2685 thread0.td_pcb->pcb_gsd = PCPU_GET(fsgs_gdt)[1];
2686
2687 if (cpu_probe_amdc1e())
2688 cpu_idle_fn = cpu_idle_amdc1e;
2689 }
2690
2691 #else
2692 void
2693 init386(first)
2694 int first;
2695 {
2696 struct gate_descriptor *gdp;
2697 int gsel_tss, metadata_missing, x, pa;
2698 struct pcpu *pc;
2699
2700 thread0.td_kstack = proc0kstack;
2701 thread0.td_pcb = (struct pcb *)
2702 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
2703
2704 /*
2705 * This may be done better later if it gets more high level
2706 * components in it. If so just link td->td_proc here.
2707 */
2708 proc_linkup0(&proc0, &thread0);
2709
2710 metadata_missing = 0;
2711 if (bootinfo.bi_modulep) {
2712 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
2713 preload_bootstrap_relocate(KERNBASE);
2714 } else {
2715 metadata_missing = 1;
2716 }
2717 if (envmode == 1)
2718 kern_envp = static_env;
2719 else if (bootinfo.bi_envp)
2720 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
2721
2722 /* Init basic tunables, hz etc */
2723 init_param1();
2724
2725 /*
2726 * Make gdt memory segments. All segments cover the full 4GB
2727 * of address space and permissions are enforced at page level.
2728 */
2729 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
2730 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
2731 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1);
2732 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1);
2733 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1);
2734 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1);
2735
2736 pc = &__pcpu[0];
2737 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1);
2738 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
2739 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
2740
2741 for (x = 0; x < NGDT; x++)
2742 ssdtosd(&gdt_segs[x], &gdt[x].sd);
2743
2744 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2745 r_gdt.rd_base = (int) gdt;
2746 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
2747 lgdt(&r_gdt);
2748
2749 pcpu_init(pc, 0, sizeof(struct pcpu));
2750 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
2751 pmap_kenter(pa + KERNBASE, pa);
2752 dpcpu_init((void *)(first + KERNBASE), 0);
2753 first += DPCPU_SIZE;
2754 PCPU_SET(prvspace, pc);
2755 PCPU_SET(curthread, &thread0);
2756 PCPU_SET(curpcb, thread0.td_pcb);
2757
2758 /*
2759 * Initialize mutexes.
2760 *
2761 * icu_lock: in order to allow an interrupt to occur in a critical
2762 * section, to set pcpu->ipending (etc...) properly, we
2763 * must be able to get the icu lock, so it can't be
2764 * under witness.
2765 */
2766 mutex_init();
2767 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
2768
2769 /* make ldt memory segments */
2770 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
2771 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
2772 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
2773 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2774
2775 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2776 lldt(_default_ldt);
2777 PCPU_SET(currentldt, _default_ldt);
2778
2779 /* exceptions */
2780 for (x = 0; x < NIDT; x++)
2781 setidt(x, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL,
2782 GSEL(GCODE_SEL, SEL_KPL));
2783 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL,
2784 GSEL(GCODE_SEL, SEL_KPL));
2785 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL,
2786 GSEL(GCODE_SEL, SEL_KPL));
2787 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL,
2788 GSEL(GCODE_SEL, SEL_KPL));
2789 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL,
2790 GSEL(GCODE_SEL, SEL_KPL));
2791 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL,
2792 GSEL(GCODE_SEL, SEL_KPL));
2793 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL,
2794 GSEL(GCODE_SEL, SEL_KPL));
2795 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
2796 GSEL(GCODE_SEL, SEL_KPL));
2797 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL
2798 , GSEL(GCODE_SEL, SEL_KPL));
2799 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2800 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL,
2801 GSEL(GCODE_SEL, SEL_KPL));
2802 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL,
2803 GSEL(GCODE_SEL, SEL_KPL));
2804 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL,
2805 GSEL(GCODE_SEL, SEL_KPL));
2806 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL,
2807 GSEL(GCODE_SEL, SEL_KPL));
2808 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
2809 GSEL(GCODE_SEL, SEL_KPL));
2810 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL,
2811 GSEL(GCODE_SEL, SEL_KPL));
2812 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL,
2813 GSEL(GCODE_SEL, SEL_KPL));
2814 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL,
2815 GSEL(GCODE_SEL, SEL_KPL));
2816 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL,
2817 GSEL(GCODE_SEL, SEL_KPL));
2818 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL,
2819 GSEL(GCODE_SEL, SEL_KPL));
2820 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall), SDT_SYS386TGT, SEL_UPL,
2821 GSEL(GCODE_SEL, SEL_KPL));
2822
2823 r_idt.rd_limit = sizeof(idt0) - 1;
2824 r_idt.rd_base = (int) idt;
2825 lidt(&r_idt);
2826
2827 #ifdef XBOX
2828 /*
2829 * The following code queries the PCI ID of 0:0:0. For the XBOX,
2830 * This should be 0x10de / 0x02a5.
2831 *
2832 * This is exactly what Linux does.
2833 */
2834 outl(0xcf8, 0x80000000);
2835 if (inl(0xcfc) == 0x02a510de) {
2836 arch_i386_is_xbox = 1;
2837 pic16l_setled(XBOX_LED_GREEN);
2838
2839 /*
2840 * We are an XBOX, but we may have either 64MB or 128MB of
2841 * memory. The PCI host bridge should be programmed for this,
2842 * so we just query it.
2843 */
2844 outl(0xcf8, 0x80000084);
2845 arch_i386_xbox_memsize = (inl(0xcfc) == 0x7FFFFFF) ? 128 : 64;
2846 }
2847 #endif /* XBOX */
2848
2849 /*
2850 * Initialize the i8254 before the console so that console
2851 * initialization can use DELAY().
2852 */
2853 i8254_init();
2854
2855 /*
2856 * Initialize the console before we print anything out.
2857 */
2858 cninit();
2859
2860 if (metadata_missing)
2861 printf("WARNING: loader(8) metadata is missing!\n");
2862
2863 #ifdef DEV_ISA
2864 elcr_probe();
2865 atpic_startup();
2866 #endif
2867
2868 #ifdef DDB
2869 ksym_start = bootinfo.bi_symtab;
2870 ksym_end = bootinfo.bi_esymtab;
2871 #endif
2872
2873 kdb_init();
2874
2875 #ifdef KDB
2876 if (boothowto & RB_KDB)
2877 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
2878 #endif
2879
2880 finishidentcpu(); /* Final stage of CPU initialization */
2881 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
2882 GSEL(GCODE_SEL, SEL_KPL));
2883 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
2884 GSEL(GCODE_SEL, SEL_KPL));
2885 initializecpu(); /* Initialize CPU registers */
2886
2887 /* make an initial tss so cpu can get interrupt stack on syscall! */
2888 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
2889 PCPU_SET(common_tss.tss_esp0, thread0.td_kstack +
2890 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb) - 16);
2891 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
2892 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2893 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
2894 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
2895 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
2896 ltr(gsel_tss);
2897
2898 /* pointer to selector slot for %fs/%gs */
2899 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
2900
2901 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2902 dblfault_tss.tss_esp2 = (int)&dblfault_stack[sizeof(dblfault_stack)];
2903 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2904 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2905 #ifdef PAE
2906 dblfault_tss.tss_cr3 = (int)IdlePDPT;
2907 #else
2908 dblfault_tss.tss_cr3 = (int)IdlePTD;
2909 #endif
2910 dblfault_tss.tss_eip = (int)dblfault_handler;
2911 dblfault_tss.tss_eflags = PSL_KERNEL;
2912 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2913 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2914 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2915 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2916 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2917
2918 vm86_initialize();
2919 getmemsize(first);
2920 init_param2(physmem);
2921
2922 /* now running on new page tables, configured,and u/iom is accessible */
2923
2924 msgbufinit(msgbufp, MSGBUF_SIZE);
2925
2926 /* make a call gate to reenter kernel with */
2927 gdp = &ldt[LSYS5CALLS_SEL].gd;
2928
2929 x = (int) &IDTVEC(lcall_syscall);
2930 gdp->gd_looffset = x;
2931 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2932 gdp->gd_stkcpy = 1;
2933 gdp->gd_type = SDT_SYS386CGT;
2934 gdp->gd_dpl = SEL_UPL;
2935 gdp->gd_p = 1;
2936 gdp->gd_hioffset = x >> 16;
2937
2938 /* XXX does this work? */
2939 /* XXX yes! */
2940 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2941 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2942
2943 /* transfer to user mode */
2944
2945 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2946 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2947
2948 /* setup proc 0's pcb */
2949 thread0.td_pcb->pcb_flags = 0;
2950 #ifdef PAE
2951 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
2952 #else
2953 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2954 #endif
2955 thread0.td_pcb->pcb_ext = 0;
2956 thread0.td_frame = &proc0_tf;
2957
2958 if (cpu_probe_amdc1e())
2959 cpu_idle_fn = cpu_idle_amdc1e;
2960 }
2961 #endif
2962
2963 void
2964 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
2965 {
2966
2967 pcpu->pc_acpi_id = 0xffffffff;
2968 }
2969
2970 void
2971 spinlock_enter(void)
2972 {
2973 struct thread *td;
2974
2975 td = curthread;
2976 if (td->td_md.md_spinlock_count == 0)
2977 td->td_md.md_saved_flags = intr_disable();
2978 td->td_md.md_spinlock_count++;
2979 critical_enter();
2980 }
2981
2982 void
2983 spinlock_exit(void)
2984 {
2985 struct thread *td;
2986
2987 td = curthread;
2988 critical_exit();
2989 td->td_md.md_spinlock_count--;
2990 if (td->td_md.md_spinlock_count == 0)
2991 intr_restore(td->td_md.md_saved_flags);
2992 }
2993
2994 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2995 static void f00f_hack(void *unused);
2996 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
2997
2998 static void
2999 f00f_hack(void *unused)
3000 {
3001 struct gate_descriptor *new_idt;
3002 vm_offset_t tmp;
3003
3004 if (!has_f00f_bug)
3005 return;
3006
3007 GIANT_REQUIRED;
3008
3009 printf("Intel Pentium detected, installing workaround for F00F bug\n");
3010
3011 tmp = kmem_alloc(kernel_map, PAGE_SIZE * 2);
3012 if (tmp == 0)
3013 panic("kmem_alloc returned 0");
3014
3015 /* Put the problematic entry (#6) at the end of the lower page. */
3016 new_idt = (struct gate_descriptor*)
3017 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor));
3018 bcopy(idt, new_idt, sizeof(idt0));
3019 r_idt.rd_base = (u_int)new_idt;
3020 lidt(&r_idt);
3021 idt = new_idt;
3022 if (vm_map_protect(kernel_map, tmp, tmp + PAGE_SIZE,
3023 VM_PROT_READ, FALSE) != KERN_SUCCESS)
3024 panic("vm_map_protect failed");
3025 }
3026 #endif /* defined(I586_CPU) && !NO_F00F_HACK */
3027
3028 /*
3029 * Construct a PCB from a trapframe. This is called from kdb_trap() where
3030 * we want to start a backtrace from the function that caused us to enter
3031 * the debugger. We have the context in the trapframe, but base the trace
3032 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
3033 * enough for a backtrace.
3034 */
3035 void
3036 makectx(struct trapframe *tf, struct pcb *pcb)
3037 {
3038
3039 pcb->pcb_edi = tf->tf_edi;
3040 pcb->pcb_esi = tf->tf_esi;
3041 pcb->pcb_ebp = tf->tf_ebp;
3042 pcb->pcb_ebx = tf->tf_ebx;
3043 pcb->pcb_eip = tf->tf_eip;
3044 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8;
3045 }
3046
3047 int
3048 ptrace_set_pc(struct thread *td, u_long addr)
3049 {
3050
3051 td->td_frame->tf_eip = addr;
3052 return (0);
3053 }
3054
3055 int
3056 ptrace_single_step(struct thread *td)
3057 {
3058 td->td_frame->tf_eflags |= PSL_T;
3059 return (0);
3060 }
3061
3062 int
3063 ptrace_clear_single_step(struct thread *td)
3064 {
3065 td->td_frame->tf_eflags &= ~PSL_T;
3066 return (0);
3067 }
3068
3069 int
3070 fill_regs(struct thread *td, struct reg *regs)
3071 {
3072 struct pcb *pcb;
3073 struct trapframe *tp;
3074
3075 tp = td->td_frame;
3076 pcb = td->td_pcb;
3077 regs->r_fs = tp->tf_fs;
3078 regs->r_es = tp->tf_es;
3079 regs->r_ds = tp->tf_ds;
3080 regs->r_edi = tp->tf_edi;
3081 regs->r_esi = tp->tf_esi;
3082 regs->r_ebp = tp->tf_ebp;
3083 regs->r_ebx = tp->tf_ebx;
3084 regs->r_edx = tp->tf_edx;
3085 regs->r_ecx = tp->tf_ecx;
3086 regs->r_eax = tp->tf_eax;
3087 regs->r_eip = tp->tf_eip;
3088 regs->r_cs = tp->tf_cs;
3089 regs->r_eflags = tp->tf_eflags;
3090 regs->r_esp = tp->tf_esp;
3091 regs->r_ss = tp->tf_ss;
3092 regs->r_gs = pcb->pcb_gs;
3093 return (0);
3094 }
3095
3096 int
3097 set_regs(struct thread *td, struct reg *regs)
3098 {
3099 struct pcb *pcb;
3100 struct trapframe *tp;
3101
3102 tp = td->td_frame;
3103 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
3104 !CS_SECURE(regs->r_cs))
3105 return (EINVAL);
3106 pcb = td->td_pcb;
3107 tp->tf_fs = regs->r_fs;
3108 tp->tf_es = regs->r_es;
3109 tp->tf_ds = regs->r_ds;
3110 tp->tf_edi = regs->r_edi;
3111 tp->tf_esi = regs->r_esi;
3112 tp->tf_ebp = regs->r_ebp;
3113 tp->tf_ebx = regs->r_ebx;
3114 tp->tf_edx = regs->r_edx;
3115 tp->tf_ecx = regs->r_ecx;
3116 tp->tf_eax = regs->r_eax;
3117 tp->tf_eip = regs->r_eip;
3118 tp->tf_cs = regs->r_cs;
3119 tp->tf_eflags = regs->r_eflags;
3120 tp->tf_esp = regs->r_esp;
3121 tp->tf_ss = regs->r_ss;
3122 pcb->pcb_gs = regs->r_gs;
3123 return (0);
3124 }
3125
3126 #ifdef CPU_ENABLE_SSE
3127 static void
3128 fill_fpregs_xmm(sv_xmm, sv_87)
3129 struct savexmm *sv_xmm;
3130 struct save87 *sv_87;
3131 {
3132 register struct env87 *penv_87 = &sv_87->sv_env;
3133 register struct envxmm *penv_xmm = &sv_xmm->sv_env;
3134 int i;
3135
3136 bzero(sv_87, sizeof(*sv_87));
3137
3138 /* FPU control/status */
3139 penv_87->en_cw = penv_xmm->en_cw;
3140 penv_87->en_sw = penv_xmm->en_sw;
3141 penv_87->en_tw = penv_xmm->en_tw;
3142 penv_87->en_fip = penv_xmm->en_fip;
3143 penv_87->en_fcs = penv_xmm->en_fcs;
3144 penv_87->en_opcode = penv_xmm->en_opcode;
3145 penv_87->en_foo = penv_xmm->en_foo;
3146 penv_87->en_fos = penv_xmm->en_fos;
3147
3148 /* FPU registers */
3149 for (i = 0; i < 8; ++i)
3150 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
3151 }
3152
3153 static void
3154 set_fpregs_xmm(sv_87, sv_xmm)
3155 struct save87 *sv_87;
3156 struct savexmm *sv_xmm;
3157 {
3158 register struct env87 *penv_87 = &sv_87->sv_env;
3159 register struct envxmm *penv_xmm = &sv_xmm->sv_env;
3160 int i;
3161
3162 /* FPU control/status */
3163 penv_xmm->en_cw = penv_87->en_cw;
3164 penv_xmm->en_sw = penv_87->en_sw;
3165 penv_xmm->en_tw = penv_87->en_tw;
3166 penv_xmm->en_fip = penv_87->en_fip;
3167 penv_xmm->en_fcs = penv_87->en_fcs;
3168 penv_xmm->en_opcode = penv_87->en_opcode;
3169 penv_xmm->en_foo = penv_87->en_foo;
3170 penv_xmm->en_fos = penv_87->en_fos;
3171
3172 /* FPU registers */
3173 for (i = 0; i < 8; ++i)
3174 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
3175 }
3176 #endif /* CPU_ENABLE_SSE */
3177
3178 int
3179 fill_fpregs(struct thread *td, struct fpreg *fpregs)
3180 {
3181 #ifdef CPU_ENABLE_SSE
3182 if (cpu_fxsr) {
3183 fill_fpregs_xmm(&td->td_pcb->pcb_save.sv_xmm,
3184 (struct save87 *)fpregs);
3185 return (0);
3186 }
3187 #endif /* CPU_ENABLE_SSE */
3188 bcopy(&td->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
3189 return (0);
3190 }
3191
3192 int
3193 set_fpregs(struct thread *td, struct fpreg *fpregs)
3194 {
3195 #ifdef CPU_ENABLE_SSE
3196 if (cpu_fxsr) {
3197 set_fpregs_xmm((struct save87 *)fpregs,
3198 &td->td_pcb->pcb_save.sv_xmm);
3199 return (0);
3200 }
3201 #endif /* CPU_ENABLE_SSE */
3202 bcopy(fpregs, &td->td_pcb->pcb_save.sv_87, sizeof *fpregs);
3203 return (0);
3204 }
3205
3206 /*
3207 * Get machine context.
3208 */
3209 int
3210 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
3211 {
3212 struct trapframe *tp;
3213 struct segment_descriptor *sdp;
3214
3215 tp = td->td_frame;
3216
3217 PROC_LOCK(curthread->td_proc);
3218 mcp->mc_onstack = sigonstack(tp->tf_esp);
3219 PROC_UNLOCK(curthread->td_proc);
3220 mcp->mc_gs = td->td_pcb->pcb_gs;
3221 mcp->mc_fs = tp->tf_fs;
3222 mcp->mc_es = tp->tf_es;
3223 mcp->mc_ds = tp->tf_ds;
3224 mcp->mc_edi = tp->tf_edi;
3225 mcp->mc_esi = tp->tf_esi;
3226 mcp->mc_ebp = tp->tf_ebp;
3227 mcp->mc_isp = tp->tf_isp;
3228 mcp->mc_eflags = tp->tf_eflags;
3229 if (flags & GET_MC_CLEAR_RET) {
3230 mcp->mc_eax = 0;
3231 mcp->mc_edx = 0;
3232 mcp->mc_eflags &= ~PSL_C;
3233 } else {
3234 mcp->mc_eax = tp->tf_eax;
3235 mcp->mc_edx = tp->tf_edx;
3236 }
3237 mcp->mc_ebx = tp->tf_ebx;
3238 mcp->mc_ecx = tp->tf_ecx;
3239 mcp->mc_eip = tp->tf_eip;
3240 mcp->mc_cs = tp->tf_cs;
3241 mcp->mc_esp = tp->tf_esp;
3242 mcp->mc_ss = tp->tf_ss;
3243 mcp->mc_len = sizeof(*mcp);
3244 get_fpcontext(td, mcp);
3245 sdp = &td->td_pcb->pcb_gsd;
3246 mcp->mc_fsbase = sdp->sd_hibase << 24 | sdp->sd_lobase;
3247 sdp = &td->td_pcb->pcb_fsd;
3248 mcp->mc_gsbase = sdp->sd_hibase << 24 | sdp->sd_lobase;
3249
3250 return (0);
3251 }
3252
3253 /*
3254 * Set machine context.
3255 *
3256 * However, we don't set any but the user modifiable flags, and we won't
3257 * touch the cs selector.
3258 */
3259 int
3260 set_mcontext(struct thread *td, const mcontext_t *mcp)
3261 {
3262 struct trapframe *tp;
3263 int eflags, ret;
3264
3265 tp = td->td_frame;
3266 if (mcp->mc_len != sizeof(*mcp))
3267 return (EINVAL);
3268 eflags = (mcp->mc_eflags & PSL_USERCHANGE) |
3269 (tp->tf_eflags & ~PSL_USERCHANGE);
3270 if ((ret = set_fpcontext(td, mcp)) == 0) {
3271 tp->tf_fs = mcp->mc_fs;
3272 tp->tf_es = mcp->mc_es;
3273 tp->tf_ds = mcp->mc_ds;
3274 tp->tf_edi = mcp->mc_edi;
3275 tp->tf_esi = mcp->mc_esi;
3276 tp->tf_ebp = mcp->mc_ebp;
3277 tp->tf_ebx = mcp->mc_ebx;
3278 tp->tf_edx = mcp->mc_edx;
3279 tp->tf_ecx = mcp->mc_ecx;
3280 tp->tf_eax = mcp->mc_eax;
3281 tp->tf_eip = mcp->mc_eip;
3282 tp->tf_eflags = eflags;
3283 tp->tf_esp = mcp->mc_esp;
3284 tp->tf_ss = mcp->mc_ss;
3285 td->td_pcb->pcb_gs = mcp->mc_gs;
3286 ret = 0;
3287 }
3288 return (ret);
3289 }
3290
3291 static void
3292 get_fpcontext(struct thread *td, mcontext_t *mcp)
3293 {
3294 #ifndef DEV_NPX
3295 mcp->mc_fpformat = _MC_FPFMT_NODEV;
3296 mcp->mc_ownedfp = _MC_FPOWNED_NONE;
3297 #else
3298 union savefpu *addr;
3299
3300 /*
3301 * XXX mc_fpstate might be misaligned, since its declaration is not
3302 * unportabilized using __attribute__((aligned(16))) like the
3303 * declaration of struct savemm, and anyway, alignment doesn't work
3304 * for auto variables since we don't use gcc's pessimal stack
3305 * alignment. Work around this by abusing the spare fields after
3306 * mcp->mc_fpstate.
3307 *
3308 * XXX unpessimize most cases by only aligning when fxsave might be
3309 * called, although this requires knowing too much about
3310 * npxgetregs()'s internals.
3311 */
3312 addr = (union savefpu *)&mcp->mc_fpstate;
3313 if (td == PCPU_GET(fpcurthread) &&
3314 #ifdef CPU_ENABLE_SSE
3315 cpu_fxsr &&
3316 #endif
3317 ((uintptr_t)(void *)addr & 0xF)) {
3318 do
3319 addr = (void *)((char *)addr + 4);
3320 while ((uintptr_t)(void *)addr & 0xF);
3321 }
3322 mcp->mc_ownedfp = npxgetregs(td, addr);
3323 if (addr != (union savefpu *)&mcp->mc_fpstate) {
3324 bcopy(addr, &mcp->mc_fpstate, sizeof(mcp->mc_fpstate));
3325 bzero(&mcp->mc_spare2, sizeof(mcp->mc_spare2));
3326 }
3327 mcp->mc_fpformat = npxformat();
3328 #endif
3329 }
3330
3331 static int
3332 set_fpcontext(struct thread *td, const mcontext_t *mcp)
3333 {
3334 union savefpu *addr;
3335
3336 if (mcp->mc_fpformat == _MC_FPFMT_NODEV)
3337 return (0);
3338 else if (mcp->mc_fpformat != _MC_FPFMT_387 &&
3339 mcp->mc_fpformat != _MC_FPFMT_XMM)
3340 return (EINVAL);
3341 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE)
3342 /* We don't care what state is left in the FPU or PCB. */
3343 fpstate_drop(td);
3344 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU ||
3345 mcp->mc_ownedfp == _MC_FPOWNED_PCB) {
3346 /* XXX align as above. */
3347 addr = (union savefpu *)&mcp->mc_fpstate;
3348 if (td == PCPU_GET(fpcurthread) &&
3349 #ifdef CPU_ENABLE_SSE
3350 cpu_fxsr &&
3351 #endif
3352 ((uintptr_t)(void *)addr & 0xF)) {
3353 do
3354 addr = (void *)((char *)addr + 4);
3355 while ((uintptr_t)(void *)addr & 0xF);
3356 bcopy(&mcp->mc_fpstate, addr, sizeof(mcp->mc_fpstate));
3357 }
3358 #ifdef DEV_NPX
3359 #ifdef CPU_ENABLE_SSE
3360 if (cpu_fxsr)
3361 addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask;
3362 #endif
3363 /*
3364 * XXX we violate the dubious requirement that npxsetregs()
3365 * be called with interrupts disabled.
3366 */
3367 npxsetregs(td, addr);
3368 #endif
3369 /*
3370 * Don't bother putting things back where they were in the
3371 * misaligned case, since we know that the caller won't use
3372 * them again.
3373 */
3374 } else
3375 return (EINVAL);
3376 return (0);
3377 }
3378
3379 static void
3380 fpstate_drop(struct thread *td)
3381 {
3382 register_t s;
3383
3384 s = intr_disable();
3385 #ifdef DEV_NPX
3386 if (PCPU_GET(fpcurthread) == td)
3387 npxdrop();
3388 #endif
3389 /*
3390 * XXX force a full drop of the npx. The above only drops it if we
3391 * owned it. npxgetregs() has the same bug in the !cpu_fxsr case.
3392 *
3393 * XXX I don't much like npxgetregs()'s semantics of doing a full
3394 * drop. Dropping only to the pcb matches fnsave's behaviour.
3395 * We only need to drop to !PCB_INITDONE in sendsig(). But
3396 * sendsig() is the only caller of npxgetregs()... perhaps we just
3397 * have too many layers.
3398 */
3399 curthread->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
3400 intr_restore(s);
3401 }
3402
3403 int
3404 fill_dbregs(struct thread *td, struct dbreg *dbregs)
3405 {
3406 struct pcb *pcb;
3407
3408 if (td == NULL) {
3409 dbregs->dr[0] = rdr0();
3410 dbregs->dr[1] = rdr1();
3411 dbregs->dr[2] = rdr2();
3412 dbregs->dr[3] = rdr3();
3413 dbregs->dr[4] = rdr4();
3414 dbregs->dr[5] = rdr5();
3415 dbregs->dr[6] = rdr6();
3416 dbregs->dr[7] = rdr7();
3417 } else {
3418 pcb = td->td_pcb;
3419 dbregs->dr[0] = pcb->pcb_dr0;
3420 dbregs->dr[1] = pcb->pcb_dr1;
3421 dbregs->dr[2] = pcb->pcb_dr2;
3422 dbregs->dr[3] = pcb->pcb_dr3;
3423 dbregs->dr[4] = 0;
3424 dbregs->dr[5] = 0;
3425 dbregs->dr[6] = pcb->pcb_dr6;
3426 dbregs->dr[7] = pcb->pcb_dr7;
3427 }
3428 return (0);
3429 }
3430
3431 int
3432 set_dbregs(struct thread *td, struct dbreg *dbregs)
3433 {
3434 struct pcb *pcb;
3435 int i;
3436
3437 if (td == NULL) {
3438 load_dr0(dbregs->dr[0]);
3439 load_dr1(dbregs->dr[1]);
3440 load_dr2(dbregs->dr[2]);
3441 load_dr3(dbregs->dr[3]);
3442 load_dr4(dbregs->dr[4]);
3443 load_dr5(dbregs->dr[5]);
3444 load_dr6(dbregs->dr[6]);
3445 load_dr7(dbregs->dr[7]);
3446 } else {
3447 /*
3448 * Don't let an illegal value for dr7 get set. Specifically,
3449 * check for undefined settings. Setting these bit patterns
3450 * result in undefined behaviour and can lead to an unexpected
3451 * TRCTRAP.
3452 */
3453 for (i = 0; i < 4; i++) {
3454 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02)
3455 return (EINVAL);
3456 if (DBREG_DR7_LEN(dbregs->dr[7], i) == 0x02)
3457 return (EINVAL);
3458 }
3459
3460 pcb = td->td_pcb;
3461
3462 /*
3463 * Don't let a process set a breakpoint that is not within the
3464 * process's address space. If a process could do this, it
3465 * could halt the system by setting a breakpoint in the kernel
3466 * (if ddb was enabled). Thus, we need to check to make sure
3467 * that no breakpoints are being enabled for addresses outside
3468 * process's address space.
3469 *
3470 * XXX - what about when the watched area of the user's
3471 * address space is written into from within the kernel
3472 * ... wouldn't that still cause a breakpoint to be generated
3473 * from within kernel mode?
3474 */
3475
3476 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) {
3477 /* dr0 is enabled */
3478 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
3479 return (EINVAL);
3480 }
3481
3482 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) {
3483 /* dr1 is enabled */
3484 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
3485 return (EINVAL);
3486 }
3487
3488 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) {
3489 /* dr2 is enabled */
3490 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
3491 return (EINVAL);
3492 }
3493
3494 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) {
3495 /* dr3 is enabled */
3496 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
3497 return (EINVAL);
3498 }
3499
3500 pcb->pcb_dr0 = dbregs->dr[0];
3501 pcb->pcb_dr1 = dbregs->dr[1];
3502 pcb->pcb_dr2 = dbregs->dr[2];
3503 pcb->pcb_dr3 = dbregs->dr[3];
3504 pcb->pcb_dr6 = dbregs->dr[6];
3505 pcb->pcb_dr7 = dbregs->dr[7];
3506
3507 pcb->pcb_flags |= PCB_DBREGS;
3508 }
3509
3510 return (0);
3511 }
3512
3513 /*
3514 * Return > 0 if a hardware breakpoint has been hit, and the
3515 * breakpoint was in user space. Return 0, otherwise.
3516 */
3517 int
3518 user_dbreg_trap(void)
3519 {
3520 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
3521 u_int32_t bp; /* breakpoint bits extracted from dr6 */
3522 int nbp; /* number of breakpoints that triggered */
3523 caddr_t addr[4]; /* breakpoint addresses */
3524 int i;
3525
3526 dr7 = rdr7();
3527 if ((dr7 & 0x000000ff) == 0) {
3528 /*
3529 * all GE and LE bits in the dr7 register are zero,
3530 * thus the trap couldn't have been caused by the
3531 * hardware debug registers
3532 */
3533 return 0;
3534 }
3535
3536 nbp = 0;
3537 dr6 = rdr6();
3538 bp = dr6 & 0x0000000f;
3539
3540 if (!bp) {
3541 /*
3542 * None of the breakpoint bits are set meaning this
3543 * trap was not caused by any of the debug registers
3544 */
3545 return 0;
3546 }
3547
3548 /*
3549 * at least one of the breakpoints were hit, check to see
3550 * which ones and if any of them are user space addresses
3551 */
3552
3553 if (bp & 0x01) {
3554 addr[nbp++] = (caddr_t)rdr0();
3555 }
3556 if (bp & 0x02) {
3557 addr[nbp++] = (caddr_t)rdr1();
3558 }
3559 if (bp & 0x04) {
3560 addr[nbp++] = (caddr_t)rdr2();
3561 }
3562 if (bp & 0x08) {
3563 addr[nbp++] = (caddr_t)rdr3();
3564 }
3565
3566 for (i = 0; i < nbp; i++) {
3567 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
3568 /*
3569 * addr[i] is in user space
3570 */
3571 return nbp;
3572 }
3573 }
3574
3575 /*
3576 * None of the breakpoints are in user space.
3577 */
3578 return 0;
3579 }
3580
3581 #ifndef DEV_APIC
3582 #include <machine/apicvar.h>
3583
3584 /*
3585 * Provide stub functions so that the MADT APIC enumerator in the acpi
3586 * kernel module will link against a kernel without 'device apic'.
3587 *
3588 * XXX - This is a gross hack.
3589 */
3590 void
3591 apic_register_enumerator(struct apic_enumerator *enumerator)
3592 {
3593 }
3594
3595 void *
3596 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
3597 {
3598 return (NULL);
3599 }
3600
3601 int
3602 ioapic_disable_pin(void *cookie, u_int pin)
3603 {
3604 return (ENXIO);
3605 }
3606
3607 int
3608 ioapic_get_vector(void *cookie, u_int pin)
3609 {
3610 return (-1);
3611 }
3612
3613 void
3614 ioapic_register(void *cookie)
3615 {
3616 }
3617
3618 int
3619 ioapic_remap_vector(void *cookie, u_int pin, int vector)
3620 {
3621 return (ENXIO);
3622 }
3623
3624 int
3625 ioapic_set_extint(void *cookie, u_int pin)
3626 {
3627 return (ENXIO);
3628 }
3629
3630 int
3631 ioapic_set_nmi(void *cookie, u_int pin)
3632 {
3633 return (ENXIO);
3634 }
3635
3636 int
3637 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
3638 {
3639 return (ENXIO);
3640 }
3641
3642 int
3643 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
3644 {
3645 return (ENXIO);
3646 }
3647
3648 void
3649 lapic_create(u_int apic_id, int boot_cpu)
3650 {
3651 }
3652
3653 void
3654 lapic_init(vm_paddr_t addr)
3655 {
3656 }
3657
3658 int
3659 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
3660 {
3661 return (ENXIO);
3662 }
3663
3664 int
3665 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
3666 {
3667 return (ENXIO);
3668 }
3669
3670 int
3671 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
3672 {
3673 return (ENXIO);
3674 }
3675 #endif
3676
3677 #ifdef KDB
3678
3679 /*
3680 * Provide inb() and outb() as functions. They are normally only available as
3681 * inline functions, thus cannot be called from the debugger.
3682 */
3683
3684 /* silence compiler warnings */
3685 u_char inb_(u_short);
3686 void outb_(u_short, u_char);
3687
3688 u_char
3689 inb_(u_short port)
3690 {
3691 return inb(port);
3692 }
3693
3694 void
3695 outb_(u_short port, u_char data)
3696 {
3697 outb(port, data);
3698 }
3699
3700 #endif /* KDB */
Cache object: aea700c5978d448e72568d50d60f77da
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