1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD: releng/10.2/sys/i386/i386/mp_machdep.c 281560 2015-04-15 16:52:34Z jhb $");
28
29 #include "opt_apic.h"
30 #include "opt_cpu.h"
31 #include "opt_kstack_pages.h"
32 #include "opt_pmap.h"
33 #include "opt_sched.h"
34 #include "opt_smp.h"
35
36 #if !defined(lint)
37 #if !defined(SMP)
38 #error How did you get here?
39 #endif
40
41 #ifndef DEV_APIC
42 #error The apic device is required for SMP, add "device apic" to your config file.
43 #endif
44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
45 #error SMP not supported with CPU_DISABLE_CMPXCHG
46 #endif
47 #endif /* not lint */
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/bus.h>
52 #include <sys/cons.h> /* cngetc() */
53 #include <sys/cpuset.h>
54 #ifdef GPROF
55 #include <sys/gmon.h>
56 #endif
57 #include <sys/kernel.h>
58 #include <sys/ktr.h>
59 #include <sys/lock.h>
60 #include <sys/malloc.h>
61 #include <sys/memrange.h>
62 #include <sys/mutex.h>
63 #include <sys/pcpu.h>
64 #include <sys/proc.h>
65 #include <sys/sched.h>
66 #include <sys/smp.h>
67 #include <sys/sysctl.h>
68
69 #include <vm/vm.h>
70 #include <vm/vm_param.h>
71 #include <vm/pmap.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_extern.h>
74
75 #include <x86/apicreg.h>
76 #include <machine/clock.h>
77 #include <machine/cputypes.h>
78 #include <x86/mca.h>
79 #include <machine/md_var.h>
80 #include <machine/pcb.h>
81 #include <machine/psl.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
84 #include <machine/cpu.h>
85
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
89
90 #define CMOS_REG (0x70)
91 #define CMOS_DATA (0x71)
92 #define BIOS_RESET (0x0f)
93 #define BIOS_WARM (0x0a)
94
95 /*
96 * this code MUST be enabled here and in mpboot.s.
97 * it follows the very early stages of AP boot by placing values in CMOS ram.
98 * it NORMALLY will never be needed and thus the primitive method for enabling.
99 *
100 #define CHECK_POINTS
101 */
102
103 #if defined(CHECK_POINTS) && !defined(PC98)
104 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
105 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
106
107 #define CHECK_INIT(D); \
108 CHECK_WRITE(0x34, (D)); \
109 CHECK_WRITE(0x35, (D)); \
110 CHECK_WRITE(0x36, (D)); \
111 CHECK_WRITE(0x37, (D)); \
112 CHECK_WRITE(0x38, (D)); \
113 CHECK_WRITE(0x39, (D));
114
115 #define CHECK_PRINT(S); \
116 printf("%s: %d, %d, %d, %d, %d, %d\n", \
117 (S), \
118 CHECK_READ(0x34), \
119 CHECK_READ(0x35), \
120 CHECK_READ(0x36), \
121 CHECK_READ(0x37), \
122 CHECK_READ(0x38), \
123 CHECK_READ(0x39));
124
125 #else /* CHECK_POINTS */
126
127 #define CHECK_INIT(D)
128 #define CHECK_PRINT(S)
129 #define CHECK_WRITE(A, D)
130
131 #endif /* CHECK_POINTS */
132
133 /* lock region used by kernel profiling */
134 int mcount_lock;
135
136 int mp_naps; /* # of Applications processors */
137 int boot_cpu_id = -1; /* designated BSP */
138
139 extern struct pcpu __pcpu[];
140
141 /* AP uses this during bootstrap. Do not staticize. */
142 char *bootSTK;
143 static int bootAP;
144
145 /* Free these after use */
146 void *bootstacks[MAXCPU];
147 static void *dpcpu;
148
149 struct pcb stoppcbs[MAXCPU];
150 struct susppcb **susppcbs;
151
152 /* Variables needed for SMP tlb shootdown. */
153 vm_offset_t smp_tlb_addr1;
154 vm_offset_t smp_tlb_addr2;
155 volatile int smp_tlb_wait;
156
157 #ifdef COUNT_IPIS
158 /* Interrupt counts. */
159 static u_long *ipi_preempt_counts[MAXCPU];
160 static u_long *ipi_ast_counts[MAXCPU];
161 u_long *ipi_invltlb_counts[MAXCPU];
162 u_long *ipi_invlrng_counts[MAXCPU];
163 u_long *ipi_invlpg_counts[MAXCPU];
164 u_long *ipi_invlcache_counts[MAXCPU];
165 u_long *ipi_rendezvous_counts[MAXCPU];
166 u_long *ipi_lazypmap_counts[MAXCPU];
167 static u_long *ipi_hardclock_counts[MAXCPU];
168 #endif
169
170 /* Default cpu_ops implementation. */
171 struct cpu_ops cpu_ops = {
172 .ipi_vectored = lapic_ipi_vectored
173 };
174
175 /*
176 * Local data and functions.
177 */
178
179 static volatile cpuset_t ipi_nmi_pending;
180
181 /* used to hold the AP's until we are ready to release them */
182 static struct mtx ap_boot_mtx;
183
184 /* Set to 1 once we're ready to let the APs out of the pen. */
185 static volatile int aps_ready = 0;
186
187 /*
188 * Store data from cpu_add() until later in the boot when we actually setup
189 * the APs.
190 */
191 struct cpu_info {
192 int cpu_present:1;
193 int cpu_bsp:1;
194 int cpu_disabled:1;
195 int cpu_hyperthread:1;
196 } static cpu_info[MAX_APIC_ID + 1];
197 int cpu_apic_ids[MAXCPU];
198 int apic_cpuids[MAX_APIC_ID + 1];
199
200 /* Holds pending bitmap based IPIs per CPU */
201 volatile u_int cpu_ipi_pending[MAXCPU];
202
203 static u_int boot_address;
204 static int cpu_logical; /* logical cpus per core */
205 static int cpu_cores; /* cores per package */
206
207 static void assign_cpu_ids(void);
208 static void install_ap_tramp(void);
209 static void set_interrupt_apic_ids(void);
210 static int start_all_aps(void);
211 static int start_ap(int apic_id);
212 static void release_aps(void *dummy);
213
214 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
215 static int hyperthreading_allowed = 1;
216
217 static void
218 mem_range_AP_init(void)
219 {
220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
221 mem_range_softc.mr_op->initAP(&mem_range_softc);
222 }
223
224 static void
225 topo_probe_amd(void)
226 {
227 int core_id_bits;
228 int id;
229
230 /* AMD processors do not support HTT. */
231 cpu_logical = 1;
232
233 if ((amd_feature2 & AMDID2_CMP) == 0) {
234 cpu_cores = 1;
235 return;
236 }
237
238 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
239 AMDID_COREID_SIZE_SHIFT;
240 if (core_id_bits == 0) {
241 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
242 return;
243 }
244
245 /* Fam 10h and newer should get here. */
246 for (id = 0; id <= MAX_APIC_ID; id++) {
247 /* Check logical CPU availability. */
248 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
249 continue;
250 /* Check if logical CPU has the same package ID. */
251 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
252 continue;
253 cpu_cores++;
254 }
255 }
256
257 /*
258 * Round up to the next power of two, if necessary, and then
259 * take log2.
260 * Returns -1 if argument is zero.
261 */
262 static __inline int
263 mask_width(u_int x)
264 {
265
266 return (fls(x << (1 - powerof2(x))) - 1);
267 }
268
269 static void
270 topo_probe_0x4(void)
271 {
272 u_int p[4];
273 int pkg_id_bits;
274 int core_id_bits;
275 int max_cores;
276 int max_logical;
277 int id;
278
279 /* Both zero and one here mean one logical processor per package. */
280 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
281 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
282 if (max_logical <= 1)
283 return;
284
285 /*
286 * Because of uniformity assumption we examine only
287 * those logical processors that belong to the same
288 * package as BSP. Further, we count number of
289 * logical processors that belong to the same core
290 * as BSP thus deducing number of threads per core.
291 */
292 if (cpu_high >= 0x4) {
293 cpuid_count(0x04, 0, p);
294 max_cores = ((p[0] >> 26) & 0x3f) + 1;
295 } else
296 max_cores = 1;
297 core_id_bits = mask_width(max_logical/max_cores);
298 if (core_id_bits < 0)
299 return;
300 pkg_id_bits = core_id_bits + mask_width(max_cores);
301
302 for (id = 0; id <= MAX_APIC_ID; id++) {
303 /* Check logical CPU availability. */
304 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
305 continue;
306 /* Check if logical CPU has the same package ID. */
307 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
308 continue;
309 cpu_cores++;
310 /* Check if logical CPU has the same package and core IDs. */
311 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
312 cpu_logical++;
313 }
314
315 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
316 ("topo_probe_0x4 couldn't find BSP"));
317
318 cpu_cores /= cpu_logical;
319 hyperthreading_cpus = cpu_logical;
320 }
321
322 static void
323 topo_probe_0xb(void)
324 {
325 u_int p[4];
326 int bits;
327 int cnt;
328 int i;
329 int logical;
330 int type;
331 int x;
332
333 /* We only support three levels for now. */
334 for (i = 0; i < 3; i++) {
335 cpuid_count(0x0b, i, p);
336
337 /* Fall back if CPU leaf 11 doesn't really exist. */
338 if (i == 0 && p[1] == 0) {
339 topo_probe_0x4();
340 return;
341 }
342
343 bits = p[0] & 0x1f;
344 logical = p[1] &= 0xffff;
345 type = (p[2] >> 8) & 0xff;
346 if (type == 0 || logical == 0)
347 break;
348 /*
349 * Because of uniformity assumption we examine only
350 * those logical processors that belong to the same
351 * package as BSP.
352 */
353 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
354 if (!cpu_info[x].cpu_present ||
355 cpu_info[x].cpu_disabled)
356 continue;
357 if (x >> bits == boot_cpu_id >> bits)
358 cnt++;
359 }
360 if (type == CPUID_TYPE_SMT)
361 cpu_logical = cnt;
362 else if (type == CPUID_TYPE_CORE)
363 cpu_cores = cnt;
364 }
365 if (cpu_logical == 0)
366 cpu_logical = 1;
367 cpu_cores /= cpu_logical;
368 }
369
370 /*
371 * Both topology discovery code and code that consumes topology
372 * information assume top-down uniformity of the topology.
373 * That is, all physical packages must be identical and each
374 * core in a package must have the same number of threads.
375 * Topology information is queried only on BSP, on which this
376 * code runs and for which it can query CPUID information.
377 * Then topology is extrapolated on all packages using the
378 * uniformity assumption.
379 */
380 static void
381 topo_probe(void)
382 {
383 static int cpu_topo_probed = 0;
384
385 if (cpu_topo_probed)
386 return;
387
388 CPU_ZERO(&logical_cpus_mask);
389 if (mp_ncpus <= 1)
390 cpu_cores = cpu_logical = 1;
391 else if (cpu_vendor_id == CPU_VENDOR_AMD)
392 topo_probe_amd();
393 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
394 /*
395 * See Intel(R) 64 Architecture Processor
396 * Topology Enumeration article for details.
397 *
398 * Note that 0x1 <= cpu_high < 4 case should be
399 * compatible with topo_probe_0x4() logic when
400 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
401 * or it should trigger the fallback otherwise.
402 */
403 if (cpu_high >= 0xb)
404 topo_probe_0xb();
405 else if (cpu_high >= 0x1)
406 topo_probe_0x4();
407 }
408
409 /*
410 * Fallback: assume each logical CPU is in separate
411 * physical package. That is, no multi-core, no SMT.
412 */
413 if (cpu_cores == 0 || cpu_logical == 0)
414 cpu_cores = cpu_logical = 1;
415 cpu_topo_probed = 1;
416 }
417
418 struct cpu_group *
419 cpu_topo(void)
420 {
421 int cg_flags;
422
423 /*
424 * Determine whether any threading flags are
425 * necessry.
426 */
427 topo_probe();
428 if (cpu_logical > 1 && hyperthreading_cpus)
429 cg_flags = CG_FLAG_HTT;
430 else if (cpu_logical > 1)
431 cg_flags = CG_FLAG_SMT;
432 else
433 cg_flags = 0;
434 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
435 printf("WARNING: Non-uniform processors.\n");
436 printf("WARNING: Using suboptimal topology.\n");
437 return (smp_topo_none());
438 }
439 /*
440 * No multi-core or hyper-threaded.
441 */
442 if (cpu_logical * cpu_cores == 1)
443 return (smp_topo_none());
444 /*
445 * Only HTT no multi-core.
446 */
447 if (cpu_logical > 1 && cpu_cores == 1)
448 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
449 /*
450 * Only multi-core no HTT.
451 */
452 if (cpu_cores > 1 && cpu_logical == 1)
453 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
454 /*
455 * Both HTT and multi-core.
456 */
457 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
458 CG_SHARE_L1, cpu_logical, cg_flags));
459 }
460
461
462 /*
463 * Calculate usable address in base memory for AP trampoline code.
464 */
465 u_int
466 mp_bootaddress(u_int basemem)
467 {
468
469 boot_address = trunc_page(basemem); /* round down to 4k boundary */
470 if ((basemem - boot_address) < bootMP_size)
471 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
472
473 return boot_address;
474 }
475
476 void
477 cpu_add(u_int apic_id, char boot_cpu)
478 {
479
480 if (apic_id > MAX_APIC_ID) {
481 panic("SMP: APIC ID %d too high", apic_id);
482 return;
483 }
484 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
485 apic_id));
486 cpu_info[apic_id].cpu_present = 1;
487 if (boot_cpu) {
488 KASSERT(boot_cpu_id == -1,
489 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
490 boot_cpu_id));
491 boot_cpu_id = apic_id;
492 cpu_info[apic_id].cpu_bsp = 1;
493 }
494 if (mp_ncpus < MAXCPU) {
495 mp_ncpus++;
496 mp_maxid = mp_ncpus - 1;
497 }
498 if (bootverbose)
499 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
500 "AP");
501 }
502
503 void
504 cpu_mp_setmaxid(void)
505 {
506
507 /*
508 * mp_maxid should be already set by calls to cpu_add().
509 * Just sanity check its value here.
510 */
511 if (mp_ncpus == 0)
512 KASSERT(mp_maxid == 0,
513 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
514 else if (mp_ncpus == 1)
515 mp_maxid = 0;
516 else
517 KASSERT(mp_maxid >= mp_ncpus - 1,
518 ("%s: counters out of sync: max %d, count %d", __func__,
519 mp_maxid, mp_ncpus));
520 }
521
522 int
523 cpu_mp_probe(void)
524 {
525
526 /*
527 * Always record BSP in CPU map so that the mbuf init code works
528 * correctly.
529 */
530 CPU_SETOF(0, &all_cpus);
531 if (mp_ncpus == 0) {
532 /*
533 * No CPUs were found, so this must be a UP system. Setup
534 * the variables to represent a system with a single CPU
535 * with an id of 0.
536 */
537 mp_ncpus = 1;
538 return (0);
539 }
540
541 /* At least one CPU was found. */
542 if (mp_ncpus == 1) {
543 /*
544 * One CPU was found, so this must be a UP system with
545 * an I/O APIC.
546 */
547 mp_maxid = 0;
548 return (0);
549 }
550
551 /* At least two CPUs were found. */
552 return (1);
553 }
554
555 /*
556 * Initialize the IPI handlers and start up the AP's.
557 */
558 void
559 cpu_mp_start(void)
560 {
561 int i;
562
563 /* Initialize the logical ID to APIC ID table. */
564 for (i = 0; i < MAXCPU; i++) {
565 cpu_apic_ids[i] = -1;
566 cpu_ipi_pending[i] = 0;
567 }
568
569 /* Install an inter-CPU IPI for TLB invalidation */
570 setidt(IPI_INVLTLB, IDTVEC(invltlb),
571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572 setidt(IPI_INVLPG, IDTVEC(invlpg),
573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
574 setidt(IPI_INVLRNG, IDTVEC(invlrng),
575 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
576
577 /* Install an inter-CPU IPI for cache invalidation. */
578 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
579 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
580
581 /* Install an inter-CPU IPI for lazy pmap release */
582 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
584
585 /* Install an inter-CPU IPI for all-CPU rendezvous */
586 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
588
589 /* Install generic inter-CPU IPI handler */
590 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
592
593 /* Install an inter-CPU IPI for CPU stop/restart */
594 setidt(IPI_STOP, IDTVEC(cpustop),
595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596
597 /* Install an inter-CPU IPI for CPU suspend/resume */
598 setidt(IPI_SUSPEND, IDTVEC(cpususpend),
599 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
600
601 /* Set boot_cpu_id if needed. */
602 if (boot_cpu_id == -1) {
603 boot_cpu_id = PCPU_GET(apic_id);
604 cpu_info[boot_cpu_id].cpu_bsp = 1;
605 } else
606 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
607 ("BSP's APIC ID doesn't match boot_cpu_id"));
608
609 /* Probe logical/physical core configuration. */
610 topo_probe();
611
612 assign_cpu_ids();
613
614 /* Start each Application Processor */
615 start_all_aps();
616
617 set_interrupt_apic_ids();
618 }
619
620
621 /*
622 * Print various information about the SMP system hardware and setup.
623 */
624 void
625 cpu_mp_announce(void)
626 {
627 const char *hyperthread;
628 int i;
629
630 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
631 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
632 if (hyperthreading_cpus > 1)
633 printf(" x %d HTT threads", cpu_logical);
634 else if (cpu_logical > 1)
635 printf(" x %d SMT threads", cpu_logical);
636 printf("\n");
637
638 /* List active CPUs first. */
639 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
640 for (i = 1; i < mp_ncpus; i++) {
641 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
642 hyperthread = "/HT";
643 else
644 hyperthread = "";
645 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
646 cpu_apic_ids[i]);
647 }
648
649 /* List disabled CPUs last. */
650 for (i = 0; i <= MAX_APIC_ID; i++) {
651 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
652 continue;
653 if (cpu_info[i].cpu_hyperthread)
654 hyperthread = "/HT";
655 else
656 hyperthread = "";
657 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
658 i);
659 }
660 }
661
662 /*
663 * AP CPU's call this to initialize themselves.
664 */
665 void
666 init_secondary(void)
667 {
668 struct pcpu *pc;
669 vm_offset_t addr;
670 int gsel_tss;
671 int x, myid;
672 u_int cpuid, cr0;
673
674 /* bootAP is set in start_ap() to our ID. */
675 myid = bootAP;
676
677 /* Get per-cpu data */
678 pc = &__pcpu[myid];
679
680 /* prime data page for it to use */
681 pcpu_init(pc, myid, sizeof(struct pcpu));
682 dpcpu_init(dpcpu, myid);
683 pc->pc_apic_id = cpu_apic_ids[myid];
684 pc->pc_prvspace = pc;
685 pc->pc_curthread = 0;
686
687 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
688 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
689
690 for (x = 0; x < NGDT; x++) {
691 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
692 }
693
694 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
695 r_gdt.rd_base = (int) &gdt[myid * NGDT];
696 lgdt(&r_gdt); /* does magic intra-segment return */
697
698 lidt(&r_idt);
699
700 lldt(_default_ldt);
701 PCPU_SET(currentldt, _default_ldt);
702
703 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
704 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
705 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
706 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
707 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
708 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
709 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
710 ltr(gsel_tss);
711
712 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
713
714 /*
715 * Set to a known state:
716 * Set by mpboot.s: CR0_PG, CR0_PE
717 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
718 */
719 cr0 = rcr0();
720 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
721 load_cr0(cr0);
722 CHECK_WRITE(0x38, 5);
723
724 /* Disable local APIC just to be sure. */
725 lapic_disable();
726
727 /* signal our startup to the BSP. */
728 mp_naps++;
729 CHECK_WRITE(0x39, 6);
730
731 /* Spin until the BSP releases the AP's. */
732 while (!aps_ready)
733 ia32_pause();
734
735 /* BSP may have changed PTD while we were waiting */
736 invltlb();
737 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
738 invlpg(addr);
739
740 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
741 lidt(&r_idt);
742 #endif
743
744 /* Initialize the PAT MSR if present. */
745 pmap_init_pat();
746
747 /* set up CPU registers and state */
748 cpu_setregs();
749
750 /* set up SSE/NX */
751 initializecpu();
752
753 /* set up FPU state on the AP */
754 npxinit(false);
755
756 if (cpu_ops.cpu_init)
757 cpu_ops.cpu_init();
758
759 /* A quick check from sanity claus */
760 cpuid = PCPU_GET(cpuid);
761 if (PCPU_GET(apic_id) != lapic_id()) {
762 printf("SMP: cpuid = %d\n", cpuid);
763 printf("SMP: actual apic_id = %d\n", lapic_id());
764 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
765 panic("cpuid mismatch! boom!!");
766 }
767
768 /* Initialize curthread. */
769 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
770 PCPU_SET(curthread, PCPU_GET(idlethread));
771
772 mca_init();
773
774 mtx_lock_spin(&ap_boot_mtx);
775
776 /* Init local apic for irq's */
777 lapic_setup(1);
778
779 /* Set memory range attributes for this CPU to match the BSP */
780 mem_range_AP_init();
781
782 smp_cpus++;
783
784 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
785 printf("SMP: AP CPU #%d Launched!\n", cpuid);
786
787 /* Determine if we are a logical CPU. */
788 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
789 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
790 CPU_SET(cpuid, &logical_cpus_mask);
791
792 if (bootverbose)
793 lapic_dump("AP");
794
795 if (smp_cpus == mp_ncpus) {
796 /* enable IPI's, tlb shootdown, freezes etc */
797 atomic_store_rel_int(&smp_started, 1);
798 }
799
800 mtx_unlock_spin(&ap_boot_mtx);
801
802 /* Wait until all the AP's are up. */
803 while (smp_started == 0)
804 ia32_pause();
805
806 /* Start per-CPU event timers. */
807 cpu_initclocks_ap();
808
809 /* Enter the scheduler. */
810 sched_throw(NULL);
811
812 panic("scheduler returned us to %s", __func__);
813 /* NOTREACHED */
814 }
815
816 /*******************************************************************
817 * local functions and data
818 */
819
820 /*
821 * We tell the I/O APIC code about all the CPUs we want to receive
822 * interrupts. If we don't want certain CPUs to receive IRQs we
823 * can simply not tell the I/O APIC code about them in this function.
824 * We also do not tell it about the BSP since it tells itself about
825 * the BSP internally to work with UP kernels and on UP machines.
826 */
827 static void
828 set_interrupt_apic_ids(void)
829 {
830 u_int i, apic_id;
831
832 for (i = 0; i < MAXCPU; i++) {
833 apic_id = cpu_apic_ids[i];
834 if (apic_id == -1)
835 continue;
836 if (cpu_info[apic_id].cpu_bsp)
837 continue;
838 if (cpu_info[apic_id].cpu_disabled)
839 continue;
840
841 /* Don't let hyperthreads service interrupts. */
842 if (hyperthreading_cpus > 1 &&
843 apic_id % hyperthreading_cpus != 0)
844 continue;
845
846 intr_add_cpu(i);
847 }
848 }
849
850 /*
851 * Assign logical CPU IDs to local APICs.
852 */
853 static void
854 assign_cpu_ids(void)
855 {
856 u_int i;
857
858 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
859 &hyperthreading_allowed);
860
861 /* Check for explicitly disabled CPUs. */
862 for (i = 0; i <= MAX_APIC_ID; i++) {
863 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
864 continue;
865
866 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
867 cpu_info[i].cpu_hyperthread = 1;
868
869 /*
870 * Don't use HT CPU if it has been disabled by a
871 * tunable.
872 */
873 if (hyperthreading_allowed == 0) {
874 cpu_info[i].cpu_disabled = 1;
875 continue;
876 }
877 }
878
879 /* Don't use this CPU if it has been disabled by a tunable. */
880 if (resource_disabled("lapic", i)) {
881 cpu_info[i].cpu_disabled = 1;
882 continue;
883 }
884 }
885
886 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
887 hyperthreading_cpus = 0;
888 cpu_logical = 1;
889 }
890
891 /*
892 * Assign CPU IDs to local APIC IDs and disable any CPUs
893 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
894 *
895 * To minimize confusion for userland, we attempt to number
896 * CPUs such that all threads and cores in a package are
897 * grouped together. For now we assume that the BSP is always
898 * the first thread in a package and just start adding APs
899 * starting with the BSP's APIC ID.
900 */
901 mp_ncpus = 1;
902 cpu_apic_ids[0] = boot_cpu_id;
903 apic_cpuids[boot_cpu_id] = 0;
904 for (i = boot_cpu_id + 1; i != boot_cpu_id;
905 i == MAX_APIC_ID ? i = 0 : i++) {
906 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
907 cpu_info[i].cpu_disabled)
908 continue;
909
910 if (mp_ncpus < MAXCPU) {
911 cpu_apic_ids[mp_ncpus] = i;
912 apic_cpuids[i] = mp_ncpus;
913 mp_ncpus++;
914 } else
915 cpu_info[i].cpu_disabled = 1;
916 }
917 KASSERT(mp_maxid >= mp_ncpus - 1,
918 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
919 mp_ncpus));
920 }
921
922 /*
923 * start each AP in our list
924 */
925 /* Lowest 1MB is already mapped: don't touch*/
926 #define TMPMAP_START 1
927 static int
928 start_all_aps(void)
929 {
930 #ifndef PC98
931 u_char mpbiosreason;
932 #endif
933 u_int32_t mpbioswarmvec;
934 int apic_id, cpu, i;
935
936 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
937
938 /* install the AP 1st level boot code */
939 install_ap_tramp();
940
941 /* save the current value of the warm-start vector */
942 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
943 #ifndef PC98
944 outb(CMOS_REG, BIOS_RESET);
945 mpbiosreason = inb(CMOS_DATA);
946 #endif
947
948 /* set up temporary P==V mapping for AP boot */
949 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
950 for (i = TMPMAP_START; i < NKPT; i++)
951 PTD[i] = PTD[KPTDI + i];
952 invltlb();
953
954 /* start each AP */
955 for (cpu = 1; cpu < mp_ncpus; cpu++) {
956 apic_id = cpu_apic_ids[cpu];
957
958 /* allocate and set up a boot stack data page */
959 bootstacks[cpu] =
960 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE,
961 M_WAITOK | M_ZERO);
962 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
963 M_WAITOK | M_ZERO);
964 /* setup a vector to our boot code */
965 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
966 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
967 #ifndef PC98
968 outb(CMOS_REG, BIOS_RESET);
969 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
970 #endif
971
972 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
973 bootAP = cpu;
974
975 /* attempt to start the Application Processor */
976 CHECK_INIT(99); /* setup checkpoints */
977 if (!start_ap(apic_id)) {
978 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
979 CHECK_PRINT("trace"); /* show checkpoints */
980 /* better panic as the AP may be running loose */
981 printf("panic y/n? [y] ");
982 if (cngetc() != 'n')
983 panic("bye-bye");
984 }
985 CHECK_PRINT("trace"); /* show checkpoints */
986
987 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
988 }
989
990 /* restore the warmstart vector */
991 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
992
993 #ifndef PC98
994 outb(CMOS_REG, BIOS_RESET);
995 outb(CMOS_DATA, mpbiosreason);
996 #endif
997
998 /* Undo V==P hack from above */
999 for (i = TMPMAP_START; i < NKPT; i++)
1000 PTD[i] = 0;
1001 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
1002
1003 /* number of APs actually started */
1004 return mp_naps;
1005 }
1006
1007 /*
1008 * load the 1st level AP boot code into base memory.
1009 */
1010
1011 /* targets for relocation */
1012 extern void bigJump(void);
1013 extern void bootCodeSeg(void);
1014 extern void bootDataSeg(void);
1015 extern void MPentry(void);
1016 extern u_int MP_GDT;
1017 extern u_int mp_gdtbase;
1018
1019 static void
1020 install_ap_tramp(void)
1021 {
1022 int x;
1023 int size = *(int *) ((u_long) & bootMP_size);
1024 vm_offset_t va = boot_address + KERNBASE;
1025 u_char *src = (u_char *) ((u_long) bootMP);
1026 u_char *dst = (u_char *) va;
1027 u_int boot_base = (u_int) bootMP;
1028 u_int8_t *dst8;
1029 u_int16_t *dst16;
1030 u_int32_t *dst32;
1031
1032 KASSERT (size <= PAGE_SIZE,
1033 ("'size' do not fit into PAGE_SIZE, as expected."));
1034 pmap_kenter(va, boot_address);
1035 pmap_invalidate_page (kernel_pmap, va);
1036 for (x = 0; x < size; ++x)
1037 *dst++ = *src++;
1038
1039 /*
1040 * modify addresses in code we just moved to basemem. unfortunately we
1041 * need fairly detailed info about mpboot.s for this to work. changes
1042 * to mpboot.s might require changes here.
1043 */
1044
1045 /* boot code is located in KERNEL space */
1046 dst = (u_char *) va;
1047
1048 /* modify the lgdt arg */
1049 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1050 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
1051
1052 /* modify the ljmp target for MPentry() */
1053 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1054 *dst32 = ((u_int) MPentry - KERNBASE);
1055
1056 /* modify the target for boot code segment */
1057 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1058 dst8 = (u_int8_t *) (dst16 + 1);
1059 *dst16 = (u_int) boot_address & 0xffff;
1060 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1061
1062 /* modify the target for boot data segment */
1063 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1064 dst8 = (u_int8_t *) (dst16 + 1);
1065 *dst16 = (u_int) boot_address & 0xffff;
1066 *dst8 = ((u_int) boot_address >> 16) & 0xff;
1067 }
1068
1069 /*
1070 * This function starts the AP (application processor) identified
1071 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1072 * to accomplish this. This is necessary because of the nuances
1073 * of the different hardware we might encounter. It isn't pretty,
1074 * but it seems to work.
1075 */
1076 static int
1077 start_ap(int apic_id)
1078 {
1079 int vector, ms;
1080 int cpus;
1081
1082 /* calculate the vector */
1083 vector = (boot_address >> 12) & 0xff;
1084
1085 /* used as a watchpoint to signal AP startup */
1086 cpus = mp_naps;
1087
1088 ipi_startup(apic_id, vector);
1089
1090 /* Wait up to 5 seconds for it to start. */
1091 for (ms = 0; ms < 5000; ms++) {
1092 if (mp_naps > cpus)
1093 return 1; /* return SUCCESS */
1094 DELAY(1000);
1095 }
1096 return 0; /* return FAILURE */
1097 }
1098
1099 #ifdef COUNT_XINVLTLB_HITS
1100 u_int xhits_gbl[MAXCPU];
1101 u_int xhits_pg[MAXCPU];
1102 u_int xhits_rng[MAXCPU];
1103 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1104 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1105 sizeof(xhits_gbl), "IU", "");
1106 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1107 sizeof(xhits_pg), "IU", "");
1108 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1109 sizeof(xhits_rng), "IU", "");
1110
1111 u_int ipi_global;
1112 u_int ipi_page;
1113 u_int ipi_range;
1114 u_int ipi_range_size;
1115 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1116 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1117 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1118 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1119 0, "");
1120
1121 u_int ipi_masked_global;
1122 u_int ipi_masked_page;
1123 u_int ipi_masked_range;
1124 u_int ipi_masked_range_size;
1125 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1126 &ipi_masked_global, 0, "");
1127 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1128 &ipi_masked_page, 0, "");
1129 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1130 &ipi_masked_range, 0, "");
1131 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1132 &ipi_masked_range_size, 0, "");
1133 #endif /* COUNT_XINVLTLB_HITS */
1134
1135 /*
1136 * Init and startup IPI.
1137 */
1138 void
1139 ipi_startup(int apic_id, int vector)
1140 {
1141
1142 /*
1143 * This attempts to follow the algorithm described in the
1144 * Intel Multiprocessor Specification v1.4 in section B.4.
1145 * For each IPI, we allow the local APIC ~20us to deliver the
1146 * IPI. If that times out, we panic.
1147 */
1148
1149 /*
1150 * first we do an INIT IPI: this INIT IPI might be run, resetting
1151 * and running the target CPU. OR this INIT IPI might be latched (P5
1152 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1153 * ignored.
1154 */
1155 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1156 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1157 lapic_ipi_wait(100);
1158
1159 /* Explicitly deassert the INIT IPI. */
1160 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1161 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1162 apic_id);
1163
1164 DELAY(10000); /* wait ~10mS */
1165
1166 /*
1167 * next we do a STARTUP IPI: the previous INIT IPI might still be
1168 * latched, (P5 bug) this 1st STARTUP would then terminate
1169 * immediately, and the previously started INIT IPI would continue. OR
1170 * the previous INIT IPI has already run. and this STARTUP IPI will
1171 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1172 * will run.
1173 */
1174 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1175 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1176 vector, apic_id);
1177 if (!lapic_ipi_wait(100))
1178 panic("Failed to deliver first STARTUP IPI to APIC %d",
1179 apic_id);
1180 DELAY(200); /* wait ~200uS */
1181
1182 /*
1183 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1184 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1185 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1186 * recognized after hardware RESET or INIT IPI.
1187 */
1188 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1189 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1190 vector, apic_id);
1191 if (!lapic_ipi_wait(100))
1192 panic("Failed to deliver second STARTUP IPI to APIC %d",
1193 apic_id);
1194
1195 DELAY(200); /* wait ~200uS */
1196 }
1197
1198 /*
1199 * Send an IPI to specified CPU handling the bitmap logic.
1200 */
1201 static void
1202 ipi_send_cpu(int cpu, u_int ipi)
1203 {
1204 u_int bitmap, old_pending, new_pending;
1205
1206 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1207
1208 if (IPI_IS_BITMAPED(ipi)) {
1209 bitmap = 1 << ipi;
1210 ipi = IPI_BITMAP_VECTOR;
1211 do {
1212 old_pending = cpu_ipi_pending[cpu];
1213 new_pending = old_pending | bitmap;
1214 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1215 old_pending, new_pending));
1216 if (old_pending)
1217 return;
1218 }
1219 cpu_ops.ipi_vectored(ipi, cpu_apic_ids[cpu]);
1220 }
1221
1222 /*
1223 * Flush the TLB on all other CPU's
1224 */
1225 static void
1226 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1227 {
1228 u_int ncpu;
1229
1230 ncpu = mp_ncpus - 1; /* does not shootdown self */
1231 if (ncpu < 1)
1232 return; /* no other cpus */
1233 if (!(read_eflags() & PSL_I))
1234 panic("%s: interrupts disabled", __func__);
1235 mtx_lock_spin(&smp_ipi_mtx);
1236 smp_tlb_addr1 = addr1;
1237 smp_tlb_addr2 = addr2;
1238 atomic_store_rel_int(&smp_tlb_wait, 0);
1239 ipi_all_but_self(vector);
1240 while (smp_tlb_wait < ncpu)
1241 ia32_pause();
1242 mtx_unlock_spin(&smp_ipi_mtx);
1243 }
1244
1245 static void
1246 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1247 {
1248 int cpu, ncpu, othercpus;
1249
1250 othercpus = mp_ncpus - 1;
1251 if (CPU_ISFULLSET(&mask)) {
1252 if (othercpus < 1)
1253 return;
1254 } else {
1255 CPU_CLR(PCPU_GET(cpuid), &mask);
1256 if (CPU_EMPTY(&mask))
1257 return;
1258 }
1259 if (!(read_eflags() & PSL_I))
1260 panic("%s: interrupts disabled", __func__);
1261 mtx_lock_spin(&smp_ipi_mtx);
1262 smp_tlb_addr1 = addr1;
1263 smp_tlb_addr2 = addr2;
1264 atomic_store_rel_int(&smp_tlb_wait, 0);
1265 if (CPU_ISFULLSET(&mask)) {
1266 ncpu = othercpus;
1267 ipi_all_but_self(vector);
1268 } else {
1269 ncpu = 0;
1270 while ((cpu = CPU_FFS(&mask)) != 0) {
1271 cpu--;
1272 CPU_CLR(cpu, &mask);
1273 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
1274 vector);
1275 ipi_send_cpu(cpu, vector);
1276 ncpu++;
1277 }
1278 }
1279 while (smp_tlb_wait < ncpu)
1280 ia32_pause();
1281 mtx_unlock_spin(&smp_ipi_mtx);
1282 }
1283
1284 void
1285 smp_cache_flush(void)
1286 {
1287
1288 if (smp_started)
1289 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1290 }
1291
1292 void
1293 smp_invltlb(void)
1294 {
1295
1296 if (smp_started) {
1297 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1298 #ifdef COUNT_XINVLTLB_HITS
1299 ipi_global++;
1300 #endif
1301 }
1302 }
1303
1304 void
1305 smp_invlpg(vm_offset_t addr)
1306 {
1307
1308 if (smp_started) {
1309 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1310 #ifdef COUNT_XINVLTLB_HITS
1311 ipi_page++;
1312 #endif
1313 }
1314 }
1315
1316 void
1317 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1318 {
1319
1320 if (smp_started) {
1321 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1322 #ifdef COUNT_XINVLTLB_HITS
1323 ipi_range++;
1324 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1325 #endif
1326 }
1327 }
1328
1329 void
1330 smp_masked_invltlb(cpuset_t mask)
1331 {
1332
1333 if (smp_started) {
1334 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1335 #ifdef COUNT_XINVLTLB_HITS
1336 ipi_masked_global++;
1337 #endif
1338 }
1339 }
1340
1341 void
1342 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1343 {
1344
1345 if (smp_started) {
1346 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1347 #ifdef COUNT_XINVLTLB_HITS
1348 ipi_masked_page++;
1349 #endif
1350 }
1351 }
1352
1353 void
1354 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1355 {
1356
1357 if (smp_started) {
1358 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1359 #ifdef COUNT_XINVLTLB_HITS
1360 ipi_masked_range++;
1361 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1362 #endif
1363 }
1364 }
1365
1366 void
1367 ipi_bitmap_handler(struct trapframe frame)
1368 {
1369 struct trapframe *oldframe;
1370 struct thread *td;
1371 int cpu = PCPU_GET(cpuid);
1372 u_int ipi_bitmap;
1373
1374 critical_enter();
1375 td = curthread;
1376 td->td_intr_nesting_level++;
1377 oldframe = td->td_intr_frame;
1378 td->td_intr_frame = &frame;
1379 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1380 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1381 #ifdef COUNT_IPIS
1382 (*ipi_preempt_counts[cpu])++;
1383 #endif
1384 sched_preempt(td);
1385 }
1386 if (ipi_bitmap & (1 << IPI_AST)) {
1387 #ifdef COUNT_IPIS
1388 (*ipi_ast_counts[cpu])++;
1389 #endif
1390 /* Nothing to do for AST */
1391 }
1392 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1393 #ifdef COUNT_IPIS
1394 (*ipi_hardclock_counts[cpu])++;
1395 #endif
1396 hardclockintr();
1397 }
1398 td->td_intr_frame = oldframe;
1399 td->td_intr_nesting_level--;
1400 critical_exit();
1401 }
1402
1403 /*
1404 * send an IPI to a set of cpus.
1405 */
1406 void
1407 ipi_selected(cpuset_t cpus, u_int ipi)
1408 {
1409 int cpu;
1410
1411 /*
1412 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1413 * of help in order to understand what is the source.
1414 * Set the mask of receiving CPUs for this purpose.
1415 */
1416 if (ipi == IPI_STOP_HARD)
1417 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1418
1419 while ((cpu = CPU_FFS(&cpus)) != 0) {
1420 cpu--;
1421 CPU_CLR(cpu, &cpus);
1422 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1423 ipi_send_cpu(cpu, ipi);
1424 }
1425 }
1426
1427 /*
1428 * send an IPI to a specific CPU.
1429 */
1430 void
1431 ipi_cpu(int cpu, u_int ipi)
1432 {
1433
1434 /*
1435 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1436 * of help in order to understand what is the source.
1437 * Set the mask of receiving CPUs for this purpose.
1438 */
1439 if (ipi == IPI_STOP_HARD)
1440 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1441
1442 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1443 ipi_send_cpu(cpu, ipi);
1444 }
1445
1446 /*
1447 * send an IPI to all CPUs EXCEPT myself
1448 */
1449 void
1450 ipi_all_but_self(u_int ipi)
1451 {
1452 cpuset_t other_cpus;
1453
1454 other_cpus = all_cpus;
1455 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1456 if (IPI_IS_BITMAPED(ipi)) {
1457 ipi_selected(other_cpus, ipi);
1458 return;
1459 }
1460
1461 /*
1462 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1463 * of help in order to understand what is the source.
1464 * Set the mask of receiving CPUs for this purpose.
1465 */
1466 if (ipi == IPI_STOP_HARD)
1467 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
1468
1469 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1470 cpu_ops.ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1471 }
1472
1473 int
1474 ipi_nmi_handler()
1475 {
1476 u_int cpuid;
1477
1478 /*
1479 * As long as there is not a simple way to know about a NMI's
1480 * source, if the bitmask for the current CPU is present in
1481 * the global pending bitword an IPI_STOP_HARD has been issued
1482 * and should be handled.
1483 */
1484 cpuid = PCPU_GET(cpuid);
1485 if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
1486 return (1);
1487
1488 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
1489 cpustop_handler();
1490 return (0);
1491 }
1492
1493 /*
1494 * Handle an IPI_STOP by saving our current context and spinning until we
1495 * are resumed.
1496 */
1497 void
1498 cpustop_handler(void)
1499 {
1500 u_int cpu;
1501
1502 cpu = PCPU_GET(cpuid);
1503
1504 savectx(&stoppcbs[cpu]);
1505
1506 /* Indicate that we are stopped */
1507 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1508
1509 /* Wait for restart */
1510 while (!CPU_ISSET(cpu, &started_cpus))
1511 ia32_pause();
1512
1513 CPU_CLR_ATOMIC(cpu, &started_cpus);
1514 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1515
1516 if (cpu == 0 && cpustop_restartfunc != NULL) {
1517 cpustop_restartfunc();
1518 cpustop_restartfunc = NULL;
1519 }
1520 }
1521
1522 /*
1523 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1524 * are resumed.
1525 */
1526 void
1527 cpususpend_handler(void)
1528 {
1529 u_int cpu;
1530
1531 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1532
1533 cpu = PCPU_GET(cpuid);
1534 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1535 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1536 wbinvd();
1537 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1538 } else {
1539 npxresume(susppcbs[cpu]->sp_fpususpend);
1540 pmap_init_pat();
1541 initializecpu();
1542 PCPU_SET(switchtime, 0);
1543 PCPU_SET(switchticks, ticks);
1544
1545 /* Indicate that we are resumed */
1546 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1547 }
1548
1549 /* Wait for resume */
1550 while (!CPU_ISSET(cpu, &started_cpus))
1551 ia32_pause();
1552
1553 if (cpu_ops.cpu_resume)
1554 cpu_ops.cpu_resume();
1555
1556 /* Resume MCA and local APIC */
1557 mca_resume();
1558 lapic_setup(0);
1559
1560 /* Indicate that we are resumed */
1561 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1562 CPU_CLR_ATOMIC(cpu, &started_cpus);
1563 }
1564
1565 /*
1566 * Handlers for TLB related IPIs
1567 */
1568 void
1569 invltlb_handler(void)
1570 {
1571 uint64_t cr3;
1572 #ifdef COUNT_XINVLTLB_HITS
1573 xhits_gbl[PCPU_GET(cpuid)]++;
1574 #endif /* COUNT_XINVLTLB_HITS */
1575 #ifdef COUNT_IPIS
1576 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1577 #endif /* COUNT_IPIS */
1578
1579 cr3 = rcr3();
1580 load_cr3(cr3);
1581 atomic_add_int(&smp_tlb_wait, 1);
1582 }
1583
1584 void
1585 invlpg_handler(void)
1586 {
1587 #ifdef COUNT_XINVLTLB_HITS
1588 xhits_pg[PCPU_GET(cpuid)]++;
1589 #endif /* COUNT_XINVLTLB_HITS */
1590 #ifdef COUNT_IPIS
1591 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1592 #endif /* COUNT_IPIS */
1593
1594 invlpg(smp_tlb_addr1);
1595
1596 atomic_add_int(&smp_tlb_wait, 1);
1597 }
1598
1599 void
1600 invlrng_handler(void)
1601 {
1602 vm_offset_t addr;
1603 #ifdef COUNT_XINVLTLB_HITS
1604 xhits_rng[PCPU_GET(cpuid)]++;
1605 #endif /* COUNT_XINVLTLB_HITS */
1606 #ifdef COUNT_IPIS
1607 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1608 #endif /* COUNT_IPIS */
1609
1610 addr = smp_tlb_addr1;
1611 do {
1612 invlpg(addr);
1613 addr += PAGE_SIZE;
1614 } while (addr < smp_tlb_addr2);
1615
1616 atomic_add_int(&smp_tlb_wait, 1);
1617 }
1618
1619 void
1620 invlcache_handler(void)
1621 {
1622 #ifdef COUNT_IPIS
1623 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1624 #endif /* COUNT_IPIS */
1625
1626 wbinvd();
1627 atomic_add_int(&smp_tlb_wait, 1);
1628 }
1629
1630 /*
1631 * This is called once the rest of the system is up and running and we're
1632 * ready to let the AP's out of the pen.
1633 */
1634 static void
1635 release_aps(void *dummy __unused)
1636 {
1637
1638 if (mp_ncpus == 1)
1639 return;
1640 atomic_store_rel_int(&aps_ready, 1);
1641 while (smp_started == 0)
1642 ia32_pause();
1643 }
1644 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1645
1646 #ifdef COUNT_IPIS
1647 /*
1648 * Setup interrupt counters for IPI handlers.
1649 */
1650 static void
1651 mp_ipi_intrcnt(void *dummy)
1652 {
1653 char buf[64];
1654 int i;
1655
1656 CPU_FOREACH(i) {
1657 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1658 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1659 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1660 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1661 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1662 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1663 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1664 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1665 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1666 intrcnt_add(buf, &ipi_preempt_counts[i]);
1667 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1668 intrcnt_add(buf, &ipi_ast_counts[i]);
1669 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1670 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1671 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
1672 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1673 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1674 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1675 }
1676 }
1677 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1678 #endif
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