The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/mp_machdep.c

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    1 /*-
    2  * Copyright (c) 1996, by Steve Passe
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the developer may NOT be used to endorse or promote products
   11  *    derived from this software without specific prior written permission.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD: releng/6.3/sys/i386/i386/mp_machdep.c 173886 2007-11-24 19:45:58Z cvs2svn $");
   28 
   29 #include "opt_apic.h"
   30 #include "opt_cpu.h"
   31 #include "opt_kdb.h"
   32 #include "opt_kstack_pages.h"
   33 #include "opt_mp_watchdog.h"
   34 #include "opt_sched.h"
   35 
   36 #if !defined(lint)
   37 #if !defined(SMP)
   38 #error How did you get here?
   39 #endif
   40 
   41 #ifndef DEV_APIC
   42 #error The apic device is required for SMP, add "device apic" to your config file.
   43 #endif
   44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
   45 #error SMP not supported with CPU_DISABLE_CMPXCHG
   46 #endif
   47 #endif /* not lint */
   48 
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/bus.h>
   52 #include <sys/cons.h>   /* cngetc() */
   53 #ifdef GPROF 
   54 #include <sys/gmon.h>
   55 #endif
   56 #include <sys/kernel.h>
   57 #include <sys/ktr.h>
   58 #include <sys/lock.h>
   59 #include <sys/malloc.h>
   60 #include <sys/memrange.h>
   61 #include <sys/mutex.h>
   62 #include <sys/pcpu.h>
   63 #include <sys/proc.h>
   64 #include <sys/smp.h>
   65 #include <sys/sysctl.h>
   66 
   67 #include <vm/vm.h>
   68 #include <vm/vm_param.h>
   69 #include <vm/pmap.h>
   70 #include <vm/vm_kern.h>
   71 #include <vm/vm_extern.h>
   72 
   73 #include <machine/apicreg.h>
   74 #include <machine/clock.h>
   75 #include <machine/md_var.h>
   76 #include <machine/mp_watchdog.h>
   77 #include <machine/pcb.h>
   78 #include <machine/psl.h>
   79 #include <machine/smp.h>
   80 #include <machine/smptests.h>   /** COUNT_XINVLTLB_HITS */
   81 #include <machine/specialreg.h>
   82 #include <machine/privatespace.h>
   83 
   84 #define WARMBOOT_TARGET         0
   85 #define WARMBOOT_OFF            (KERNBASE + 0x0467)
   86 #define WARMBOOT_SEG            (KERNBASE + 0x0469)
   87 
   88 #define CMOS_REG                (0x70)
   89 #define CMOS_DATA               (0x71)
   90 #define BIOS_RESET              (0x0f)
   91 #define BIOS_WARM               (0x0a)
   92 
   93 /*
   94  * this code MUST be enabled here and in mpboot.s.
   95  * it follows the very early stages of AP boot by placing values in CMOS ram.
   96  * it NORMALLY will never be needed and thus the primitive method for enabling.
   97  *
   98 #define CHECK_POINTS
   99  */
  100 
  101 #if defined(CHECK_POINTS) && !defined(PC98)
  102 #define CHECK_READ(A)    (outb(CMOS_REG, (A)), inb(CMOS_DATA))
  103 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
  104 
  105 #define CHECK_INIT(D);                          \
  106         CHECK_WRITE(0x34, (D));                 \
  107         CHECK_WRITE(0x35, (D));                 \
  108         CHECK_WRITE(0x36, (D));                 \
  109         CHECK_WRITE(0x37, (D));                 \
  110         CHECK_WRITE(0x38, (D));                 \
  111         CHECK_WRITE(0x39, (D));
  112 
  113 #define CHECK_PRINT(S);                         \
  114         printf("%s: %d, %d, %d, %d, %d, %d\n",  \
  115            (S),                                 \
  116            CHECK_READ(0x34),                    \
  117            CHECK_READ(0x35),                    \
  118            CHECK_READ(0x36),                    \
  119            CHECK_READ(0x37),                    \
  120            CHECK_READ(0x38),                    \
  121            CHECK_READ(0x39));
  122 
  123 #else                           /* CHECK_POINTS */
  124 
  125 #define CHECK_INIT(D)
  126 #define CHECK_PRINT(S)
  127 #define CHECK_WRITE(A, D)
  128 
  129 #endif                          /* CHECK_POINTS */
  130 
  131 /*
  132  * Values to send to the POST hardware.
  133  */
  134 #define MP_BOOTADDRESS_POST     0x10
  135 #define MP_PROBE_POST           0x11
  136 #define MPTABLE_PASS1_POST      0x12
  137 
  138 #define MP_START_POST           0x13
  139 #define MP_ENABLE_POST          0x14
  140 #define MPTABLE_PASS2_POST      0x15
  141 
  142 #define START_ALL_APS_POST      0x16
  143 #define INSTALL_AP_TRAMP_POST   0x17
  144 #define START_AP_POST           0x18
  145 
  146 #define MP_ANNOUNCE_POST        0x19
  147 
  148 /* lock region used by kernel profiling */
  149 int     mcount_lock;
  150 
  151 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
  152 int     current_postcode;
  153 
  154 int     mp_naps;                /* # of Applications processors */
  155 int     boot_cpu_id = -1;       /* designated BSP */
  156 extern  int nkpt;
  157 
  158 /*
  159  * CPU topology map datastructures for HTT.
  160  */
  161 static struct cpu_group mp_groups[MAXCPU];
  162 static struct cpu_top mp_top;
  163 
  164 /* AP uses this during bootstrap.  Do not staticize.  */
  165 char *bootSTK;
  166 static int bootAP;
  167 
  168 /* Hotwire a 0->4MB V==P mapping */
  169 extern pt_entry_t *KPTphys;
  170 
  171 /* SMP page table page */
  172 extern pt_entry_t *SMPpt;
  173 
  174 struct pcb stoppcbs[MAXCPU];
  175 
  176 /* Variables needed for SMP tlb shootdown. */
  177 vm_offset_t smp_tlb_addr1;
  178 vm_offset_t smp_tlb_addr2;
  179 volatile int smp_tlb_wait;
  180 
  181 #ifdef KDB_STOP_NMI
  182 volatile cpumask_t ipi_nmi_pending;
  183 #endif 
  184 
  185 #ifdef COUNT_IPIS
  186 /* Interrupt counts. */
  187 #ifdef IPI_PREEMPTION
  188 static u_long *ipi_preempt_counts[MAXCPU];
  189 #endif
  190 static u_long *ipi_ast_counts[MAXCPU];
  191 u_long *ipi_invltlb_counts[MAXCPU];
  192 u_long *ipi_invlrng_counts[MAXCPU];
  193 u_long *ipi_invlpg_counts[MAXCPU];
  194 u_long *ipi_invlcache_counts[MAXCPU];
  195 u_long *ipi_rendezvous_counts[MAXCPU];
  196 u_long *ipi_lazypmap_counts[MAXCPU];
  197 #endif
  198 
  199 /*
  200  * Local data and functions.
  201  */
  202 
  203 static u_int logical_cpus;
  204 
  205 /* used to hold the AP's until we are ready to release them */
  206 static struct mtx ap_boot_mtx;
  207 
  208 /* Set to 1 once we're ready to let the APs out of the pen. */
  209 static volatile int aps_ready = 0;
  210 
  211 /*
  212  * Store data from cpu_add() until later in the boot when we actually setup
  213  * the APs.
  214  */
  215 struct cpu_info {
  216         int     cpu_present:1;
  217         int     cpu_bsp:1;
  218         int     cpu_disabled:1;
  219 } static cpu_info[MAX_APIC_ID + 1];
  220 static int cpu_apic_ids[MAXCPU];
  221 
  222 /* Holds pending bitmap based IPIs per CPU */
  223 static volatile u_int cpu_ipi_pending[MAXCPU];
  224 
  225 static u_int boot_address;
  226 
  227 static void     assign_cpu_ids(void);
  228 static void     install_ap_tramp(void);
  229 static void     set_interrupt_apic_ids(void);
  230 static int      start_all_aps(void);
  231 static int      start_ap(int apic_id);
  232 static void     release_aps(void *dummy);
  233 
  234 static int      hlt_logical_cpus;
  235 static u_int    hyperthreading_cpus;
  236 static cpumask_t        hyperthreading_cpus_mask;
  237 static int      hyperthreading_allowed;
  238 static struct   sysctl_ctx_list logical_cpu_clist;
  239 
  240 static void
  241 mem_range_AP_init(void)
  242 {
  243         if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
  244                 mem_range_softc.mr_op->initAP(&mem_range_softc);
  245 }
  246 
  247 void
  248 mp_topology(void)
  249 {
  250         struct cpu_group *group;
  251         int logical_cpus;
  252         int apic_id;
  253         int groups;
  254         int cpu;
  255 
  256         /* Build the smp_topology map. */
  257         /* Nothing to do if there is no HTT support. */
  258         if ((cpu_feature & CPUID_HTT) == 0)
  259                 return;
  260         logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
  261         if (logical_cpus <= 1)
  262                 return;
  263         group = &mp_groups[0];
  264         groups = 1;
  265         for (cpu = 0, apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
  266                 if (!cpu_info[apic_id].cpu_present)
  267                         continue;
  268                 /*
  269                  * If the current group has members and we're not a logical
  270                  * cpu, create a new group.
  271                  */
  272                 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) {
  273                         group++;
  274                         groups++;
  275                 }
  276                 group->cg_count++;
  277                 group->cg_mask |= 1 << cpu;
  278                 cpu++;
  279         }
  280 
  281         mp_top.ct_count = groups;
  282         mp_top.ct_group = mp_groups;
  283         smp_topology = &mp_top;
  284 }
  285 
  286 
  287 /*
  288  * Calculate usable address in base memory for AP trampoline code.
  289  */
  290 u_int
  291 mp_bootaddress(u_int basemem)
  292 {
  293         POSTCODE(MP_BOOTADDRESS_POST);
  294 
  295         boot_address = trunc_page(basemem);     /* round down to 4k boundary */
  296         if ((basemem - boot_address) < bootMP_size)
  297                 boot_address -= PAGE_SIZE;      /* not enough, lower by 4k */
  298 
  299         return boot_address;
  300 }
  301 
  302 void
  303 cpu_add(u_int apic_id, char boot_cpu)
  304 {
  305 
  306         if (apic_id > MAX_APIC_ID) {
  307                 panic("SMP: APIC ID %d too high", apic_id);
  308                 return;
  309         }
  310         KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
  311             apic_id));
  312         cpu_info[apic_id].cpu_present = 1;
  313         if (boot_cpu) {
  314                 KASSERT(boot_cpu_id == -1,
  315                     ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
  316                     boot_cpu_id));
  317                 boot_cpu_id = apic_id;
  318                 cpu_info[apic_id].cpu_bsp = 1;
  319         }
  320         if (mp_ncpus < MAXCPU)
  321                 mp_ncpus++;
  322         if (bootverbose)
  323                 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
  324                     "AP");
  325 }
  326 
  327 void
  328 cpu_mp_setmaxid(void)
  329 {
  330 
  331         mp_maxid = MAXCPU - 1;
  332 }
  333 
  334 int
  335 cpu_mp_probe(void)
  336 {
  337 
  338         /*
  339          * Always record BSP in CPU map so that the mbuf init code works
  340          * correctly.
  341          */
  342         all_cpus = 1;
  343         if (mp_ncpus == 0) {
  344                 /*
  345                  * No CPUs were found, so this must be a UP system.  Setup
  346                  * the variables to represent a system with a single CPU
  347                  * with an id of 0.
  348                  */
  349                 mp_ncpus = 1;
  350                 return (0);
  351         }
  352 
  353         /* At least one CPU was found. */
  354         if (mp_ncpus == 1) {
  355                 /*
  356                  * One CPU was found, so this must be a UP system with
  357                  * an I/O APIC.
  358                  */
  359                 return (0);
  360         }
  361 
  362         /* At least two CPUs were found. */
  363         return (1);
  364 }
  365 
  366 /*
  367  * Initialize the IPI handlers and start up the AP's.
  368  */
  369 void
  370 cpu_mp_start(void)
  371 {
  372         int i;
  373         u_int threads_per_cache, p[4];
  374 
  375         POSTCODE(MP_START_POST);
  376 
  377         /* Initialize the logical ID to APIC ID table. */
  378         for (i = 0; i < MAXCPU; i++) {
  379                 cpu_apic_ids[i] = -1;
  380                 cpu_ipi_pending[i] = 0;
  381         }
  382 
  383         /* Install an inter-CPU IPI for TLB invalidation */
  384         setidt(IPI_INVLTLB, IDTVEC(invltlb),
  385                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  386         setidt(IPI_INVLPG, IDTVEC(invlpg),
  387                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  388         setidt(IPI_INVLRNG, IDTVEC(invlrng),
  389                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  390 
  391         /* Install an inter-CPU IPI for cache invalidation. */
  392         setidt(IPI_INVLCACHE, IDTVEC(invlcache),
  393                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  394 
  395         /* Install an inter-CPU IPI for lazy pmap release */
  396         setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
  397                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  398 
  399         /* Install an inter-CPU IPI for all-CPU rendezvous */
  400         setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
  401                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  402 
  403         /* Install generic inter-CPU IPI handler */
  404         setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
  405                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  406 
  407         /* Install an inter-CPU IPI for CPU stop/restart */
  408         setidt(IPI_STOP, IDTVEC(cpustop),
  409                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  410 
  411 
  412         /* Set boot_cpu_id if needed. */
  413         if (boot_cpu_id == -1) {
  414                 boot_cpu_id = PCPU_GET(apic_id);
  415                 cpu_info[boot_cpu_id].cpu_bsp = 1;
  416         } else
  417                 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
  418                     ("BSP's APIC ID doesn't match boot_cpu_id"));
  419         cpu_apic_ids[0] = boot_cpu_id;
  420 
  421         assign_cpu_ids();
  422 
  423         /* Start each Application Processor */
  424         start_all_aps();
  425 
  426         /* Setup the initial logical CPUs info. */
  427         logical_cpus = logical_cpus_mask = 0;
  428         if (cpu_feature & CPUID_HTT)
  429                 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
  430 
  431         /*
  432          * Work out if hyperthreading is *really* enabled.  This
  433          * is made really ugly by the fact that processors lie: Dual
  434          * core processors claim to be hyperthreaded even when they're
  435          * not, presumably because they want to be treated the same
  436          * way as HTT with respect to per-cpu software licensing.
  437          * At the time of writing (May 12, 2005) the only hyperthreaded
  438          * cpus are from Intel, and Intel's dual-core processors can be
  439          * identified via the "deterministic cache parameters" cpuid
  440          * calls.
  441          */
  442         /*
  443          * First determine if this is an Intel processor which claims
  444          * to have hyperthreading support.
  445          */
  446         if ((cpu_feature & CPUID_HTT) &&
  447             (strcmp(cpu_vendor, "GenuineIntel") == 0)) {
  448                 /*
  449                  * If the "deterministic cache parameters" cpuid calls
  450                  * are available, use them.
  451                  */
  452                 if (cpu_high >= 4) {
  453                         /* Ask the processor about the L1 cache. */
  454                         for (i = 0; i < 1; i++) {
  455                                 cpuid_count(4, i, p);
  456                                 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
  457                                 if (hyperthreading_cpus < threads_per_cache)
  458                                         hyperthreading_cpus = threads_per_cache;
  459                                 if ((p[0] & 0x1f) == 0)
  460                                         break;
  461                         }
  462                 }
  463 
  464                 /*
  465                  * If the deterministic cache parameters are not
  466                  * available, or if no caches were reported to exist,
  467                  * just accept what the HTT flag indicated.
  468                  */
  469                 if (hyperthreading_cpus == 0)
  470                         hyperthreading_cpus = logical_cpus;
  471         }
  472 
  473         set_interrupt_apic_ids();
  474 }
  475 
  476 
  477 /*
  478  * Print various information about the SMP system hardware and setup.
  479  */
  480 void
  481 cpu_mp_announce(void)
  482 {
  483         int i, x;
  484 
  485         POSTCODE(MP_ANNOUNCE_POST);
  486 
  487         /* List CPUs */
  488         printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
  489         for (i = 1, x = 0; x <= MAX_APIC_ID; x++) {
  490                 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp)
  491                         continue;
  492                 if (cpu_info[x].cpu_disabled)
  493                         printf("  cpu (AP): APIC ID: %2d (disabled)\n", x);
  494                 else {
  495                         KASSERT(i < mp_ncpus,
  496                             ("mp_ncpus and actual cpus are out of whack"));
  497                         printf(" cpu%d (AP): APIC ID: %2d\n", i++, x);
  498                 }
  499         }
  500 }
  501 
  502 /*
  503  * AP CPU's call this to initialize themselves.
  504  */
  505 void
  506 init_secondary(void)
  507 {
  508         vm_offset_t addr;
  509         int     gsel_tss;
  510         int     x, myid;
  511         u_int   cr0;
  512 
  513         /* bootAP is set in start_ap() to our ID. */
  514         myid = bootAP;
  515         gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
  516         gdt_segs[GPROC0_SEL].ssd_base =
  517                 (int) &SMP_prvspace[myid].pcpu.pc_common_tss;
  518         SMP_prvspace[myid].pcpu.pc_prvspace =
  519                 &SMP_prvspace[myid].pcpu;
  520 
  521         for (x = 0; x < NGDT; x++) {
  522                 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
  523         }
  524 
  525         r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
  526         r_gdt.rd_base = (int) &gdt[myid * NGDT];
  527         lgdt(&r_gdt);                   /* does magic intra-segment return */
  528 
  529         lidt(&r_idt);
  530 
  531         lldt(_default_ldt);
  532         PCPU_SET(currentldt, _default_ldt);
  533 
  534         gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
  535         gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
  536         PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
  537         PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
  538         PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
  539         PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
  540         PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
  541         ltr(gsel_tss);
  542 
  543         PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
  544 
  545         /*
  546          * Set to a known state:
  547          * Set by mpboot.s: CR0_PG, CR0_PE
  548          * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
  549          */
  550         cr0 = rcr0();
  551         cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
  552         load_cr0(cr0);
  553         CHECK_WRITE(0x38, 5);
  554         
  555         /* Disable local APIC just to be sure. */
  556         lapic_disable();
  557 
  558         /* signal our startup to the BSP. */
  559         mp_naps++;
  560         CHECK_WRITE(0x39, 6);
  561 
  562         /* Spin until the BSP releases the AP's. */
  563         while (!aps_ready)
  564                 ia32_pause();
  565 
  566         /* BSP may have changed PTD while we were waiting */
  567         invltlb();
  568         for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
  569                 invlpg(addr);
  570 
  571 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  572         lidt(&r_idt);
  573 #endif
  574 
  575         /* Initialize the PAT MSR if present. */
  576         pmap_init_pat();
  577 
  578         /* set up CPU registers and state */
  579         cpu_setregs();
  580 
  581         /* set up FPU state on the AP */
  582         npxinit(__INITIAL_NPXCW__);
  583 
  584         /* set up SSE registers */
  585         enable_sse();
  586 
  587         /* A quick check from sanity claus */
  588         if (PCPU_GET(apic_id) != lapic_id()) {
  589                 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
  590                 printf("SMP: actual apic_id = %d\n", lapic_id());
  591                 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
  592                 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]);
  593                 panic("cpuid mismatch! boom!!");
  594         }
  595 
  596         /* Initialize curthread. */
  597         KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
  598         PCPU_SET(curthread, PCPU_GET(idlethread));
  599 
  600         mtx_lock_spin(&ap_boot_mtx);
  601 
  602         /* Init local apic for irq's */
  603         lapic_setup(1);
  604 
  605         /* Set memory range attributes for this CPU to match the BSP */
  606         mem_range_AP_init();
  607 
  608         smp_cpus++;
  609 
  610         CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
  611         printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
  612 
  613         /* Determine if we are a logical CPU. */
  614         if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
  615                 logical_cpus_mask |= PCPU_GET(cpumask);
  616         
  617         /* Determine if we are a hyperthread. */
  618         if (hyperthreading_cpus > 1 &&
  619             PCPU_GET(apic_id) % hyperthreading_cpus != 0)
  620                 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
  621 
  622         /* Build our map of 'other' CPUs. */
  623         PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
  624 
  625         if (bootverbose)
  626                 lapic_dump("AP");
  627 
  628         if (smp_cpus == mp_ncpus) {
  629                 /* enable IPI's, tlb shootdown, freezes etc */
  630                 atomic_store_rel_int(&smp_started, 1);
  631                 smp_active = 1;  /* historic */
  632         }
  633 
  634         mtx_unlock_spin(&ap_boot_mtx);
  635 
  636         /* wait until all the AP's are up */
  637         while (smp_started == 0)
  638                 ia32_pause();
  639 
  640         /* ok, now grab sched_lock and enter the scheduler */
  641         mtx_lock_spin(&sched_lock);
  642 
  643         /*
  644          * Correct spinlock nesting.  The idle thread context that we are
  645          * borrowing was created so that it would start out with a single
  646          * spin lock (sched_lock) held in fork_trampoline().  Since we've
  647          * explicitly acquired locks in this function, the nesting count
  648          * is now 2 rather than 1.  Since we are nested, calling
  649          * spinlock_exit() will simply adjust the counts without allowing
  650          * spin lock using code to interrupt us.
  651          */
  652         spinlock_exit();
  653         KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count"));
  654 
  655         binuptime(PCPU_PTR(switchtime));
  656         PCPU_SET(switchticks, ticks);
  657 
  658         cpu_throw(NULL, choosethread());        /* doesn't return */
  659 
  660         panic("scheduler returned us to %s", __func__);
  661         /* NOTREACHED */
  662 }
  663 
  664 /*******************************************************************
  665  * local functions and data
  666  */
  667 
  668 /*
  669  * We tell the I/O APIC code about all the CPUs we want to receive
  670  * interrupts.  If we don't want certain CPUs to receive IRQs we
  671  * can simply not tell the I/O APIC code about them in this function.
  672  * We also do not tell it about the BSP since it tells itself about
  673  * the BSP internally to work with UP kernels and on UP machines.
  674  */
  675 static void
  676 set_interrupt_apic_ids(void)
  677 {
  678         u_int apic_id;
  679 
  680         for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
  681                 if (!cpu_info[apic_id].cpu_present)
  682                         continue;
  683                 if (cpu_info[apic_id].cpu_bsp)
  684                         continue;
  685                 if (cpu_info[apic_id].cpu_disabled)
  686                         continue;
  687 
  688                 /* Don't let hyperthreads service interrupts. */
  689                 if (hyperthreading_cpus > 1 &&
  690                     apic_id % hyperthreading_cpus != 0)
  691                         continue;
  692 
  693                 intr_add_cpu(apic_id);
  694         }
  695 }
  696 
  697 /*
  698  * Assign logical CPU IDs to local APICs.
  699  */
  700 static void
  701 assign_cpu_ids(void)
  702 {
  703         u_int i;
  704 
  705         /* Check for explicitly disabled CPUs. */
  706         for (i = 0; i <= MAX_APIC_ID; i++) {
  707                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
  708                         continue;
  709 
  710                 /* Don't use this CPU if it has been disabled by a tunable. */
  711                 if (resource_disabled("lapic", i)) {
  712                         cpu_info[i].cpu_disabled = 1;
  713                         continue;
  714                 }
  715         }
  716 
  717         /*
  718          * Assign CPU IDs to local APIC IDs and disable any CPUs
  719          * beyond MAXCPU.  CPU 0 has already been assigned to the BSP,
  720          * so we only have to assign IDs for APs.
  721          */
  722         mp_ncpus = 1;
  723         for (i = 0; i <= MAX_APIC_ID; i++) {
  724                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
  725                     cpu_info[i].cpu_disabled)
  726                         continue;
  727 
  728                 if (mp_ncpus < MAXCPU) {
  729                         cpu_apic_ids[mp_ncpus] = i;
  730                         mp_ncpus++;
  731                 } else
  732                         cpu_info[i].cpu_disabled = 1;
  733         }
  734         KASSERT(mp_maxid >= mp_ncpus - 1,
  735             ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
  736             mp_ncpus));         
  737 }
  738 
  739 /*
  740  * start each AP in our list
  741  */
  742 static int
  743 start_all_aps(void)
  744 {
  745 #ifndef PC98
  746         u_char mpbiosreason;
  747 #endif
  748         struct pcpu *pc;
  749         char *stack;
  750         uintptr_t kptbase;
  751         u_int32_t mpbioswarmvec;
  752         int apic_id, cpu, i, pg;
  753 
  754         POSTCODE(START_ALL_APS_POST);
  755 
  756         mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
  757 
  758         /* install the AP 1st level boot code */
  759         install_ap_tramp();
  760 
  761         /* save the current value of the warm-start vector */
  762         mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
  763 #ifndef PC98
  764         outb(CMOS_REG, BIOS_RESET);
  765         mpbiosreason = inb(CMOS_DATA);
  766 #endif
  767 
  768         /* set up temporary P==V mapping for AP boot */
  769         /* XXX this is a hack, we should boot the AP on its own stack/PTD */
  770         kptbase = (uintptr_t)(void *)KPTphys;
  771         for (i = 0; i < NKPT; i++)
  772                 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
  773                     ((kptbase + i * PAGE_SIZE) & PG_FRAME));
  774         invltlb();
  775 
  776         /* start each AP */
  777         for (cpu = 1; cpu < mp_ncpus; cpu++) {
  778                 apic_id = cpu_apic_ids[cpu];
  779 
  780                 /* first page of AP's private space */
  781                 pg = cpu * i386_btop(sizeof(struct privatespace));
  782 
  783                 /* allocate a new private data page */
  784                 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE);
  785 
  786                 /* wire it into the private page table page */
  787                 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc));
  788 
  789                 /* allocate and set up an idle stack data page */
  790                 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */
  791                 for (i = 0; i < KSTACK_PAGES; i++)
  792                         SMPpt[pg + 1 + i] = (pt_entry_t)
  793                             (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
  794 
  795                 /* prime data page for it to use */
  796                 pcpu_init(pc, cpu, sizeof(struct pcpu));
  797                 pc->pc_apic_id = apic_id;
  798 
  799                 /* setup a vector to our boot code */
  800                 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
  801                 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
  802 #ifndef PC98
  803                 outb(CMOS_REG, BIOS_RESET);
  804                 outb(CMOS_DATA, BIOS_WARM);     /* 'warm-start' */
  805 #endif
  806 
  807                 bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES *
  808                     PAGE_SIZE];
  809                 bootAP = cpu;
  810 
  811                 /* attempt to start the Application Processor */
  812                 CHECK_INIT(99); /* setup checkpoints */
  813                 if (!start_ap(apic_id)) {
  814                         printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
  815                         CHECK_PRINT("trace");   /* show checkpoints */
  816                         /* better panic as the AP may be running loose */
  817                         printf("panic y/n? [y] ");
  818                         if (cngetc() != 'n')
  819                                 panic("bye-bye");
  820                 }
  821                 CHECK_PRINT("trace");           /* show checkpoints */
  822 
  823                 all_cpus |= (1 << cpu);         /* record AP in CPU map */
  824         }
  825 
  826         /* build our map of 'other' CPUs */
  827         PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
  828 
  829         /* restore the warmstart vector */
  830         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  831 
  832 #ifndef PC98
  833         outb(CMOS_REG, BIOS_RESET);
  834         outb(CMOS_DATA, mpbiosreason);
  835 #endif
  836 
  837         /*
  838          * Set up the idle context for the BSP.  Similar to above except
  839          * that some was done by locore, some by pmap.c and some is implicit
  840          * because the BSP is cpu#0 and the page is initially zero and also
  841          * because we can refer to variables by name on the BSP..
  842          */
  843 
  844         /* Allocate and setup BSP idle stack */
  845         stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
  846         for (i = 0; i < KSTACK_PAGES; i++)
  847                 SMPpt[1 + i] = (pt_entry_t)
  848                     (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
  849 
  850         for (i = 0; i < NKPT; i++)
  851                 PTD[i] = 0;
  852         pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
  853 
  854         /* number of APs actually started */
  855         return mp_naps;
  856 }
  857 
  858 /*
  859  * load the 1st level AP boot code into base memory.
  860  */
  861 
  862 /* targets for relocation */
  863 extern void bigJump(void);
  864 extern void bootCodeSeg(void);
  865 extern void bootDataSeg(void);
  866 extern void MPentry(void);
  867 extern u_int MP_GDT;
  868 extern u_int mp_gdtbase;
  869 
  870 static void
  871 install_ap_tramp(void)
  872 {
  873         int     x;
  874         int     size = *(int *) ((u_long) & bootMP_size);
  875         vm_offset_t va = boot_address + KERNBASE;
  876         u_char *src = (u_char *) ((u_long) bootMP);
  877         u_char *dst = (u_char *) va;
  878         u_int   boot_base = (u_int) bootMP;
  879         u_int8_t *dst8;
  880         u_int16_t *dst16;
  881         u_int32_t *dst32;
  882 
  883         POSTCODE(INSTALL_AP_TRAMP_POST);
  884 
  885         KASSERT (size <= PAGE_SIZE,
  886             ("'size' do not fit into PAGE_SIZE, as expected."));
  887         pmap_kenter(va, boot_address);
  888         pmap_invalidate_page (kernel_pmap, va);
  889         for (x = 0; x < size; ++x)
  890                 *dst++ = *src++;
  891 
  892         /*
  893          * modify addresses in code we just moved to basemem. unfortunately we
  894          * need fairly detailed info about mpboot.s for this to work.  changes
  895          * to mpboot.s might require changes here.
  896          */
  897 
  898         /* boot code is located in KERNEL space */
  899         dst = (u_char *) va;
  900 
  901         /* modify the lgdt arg */
  902         dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
  903         *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
  904 
  905         /* modify the ljmp target for MPentry() */
  906         dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
  907         *dst32 = ((u_int) MPentry - KERNBASE);
  908 
  909         /* modify the target for boot code segment */
  910         dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
  911         dst8 = (u_int8_t *) (dst16 + 1);
  912         *dst16 = (u_int) boot_address & 0xffff;
  913         *dst8 = ((u_int) boot_address >> 16) & 0xff;
  914 
  915         /* modify the target for boot data segment */
  916         dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
  917         dst8 = (u_int8_t *) (dst16 + 1);
  918         *dst16 = (u_int) boot_address & 0xffff;
  919         *dst8 = ((u_int) boot_address >> 16) & 0xff;
  920 }
  921 
  922 /*
  923  * This function starts the AP (application processor) identified
  924  * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
  925  * to accomplish this.  This is necessary because of the nuances
  926  * of the different hardware we might encounter.  It isn't pretty,
  927  * but it seems to work.
  928  */
  929 static int
  930 start_ap(int apic_id)
  931 {
  932         int vector, ms;
  933         int cpus;
  934 
  935         POSTCODE(START_AP_POST);
  936 
  937         /* calculate the vector */
  938         vector = (boot_address >> 12) & 0xff;
  939 
  940         /* used as a watchpoint to signal AP startup */
  941         cpus = mp_naps;
  942 
  943         /*
  944          * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
  945          * and running the target CPU. OR this INIT IPI might be latched (P5
  946          * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
  947          * ignored.
  948          */
  949 
  950         /* do an INIT IPI: assert RESET */
  951         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
  952             APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
  953 
  954         /* wait for pending status end */
  955         lapic_ipi_wait(-1);
  956 
  957         /* do an INIT IPI: deassert RESET */
  958         lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
  959             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
  960 
  961         /* wait for pending status end */
  962         DELAY(10000);           /* wait ~10mS */
  963         lapic_ipi_wait(-1);
  964 
  965         /*
  966          * next we do a STARTUP IPI: the previous INIT IPI might still be
  967          * latched, (P5 bug) this 1st STARTUP would then terminate
  968          * immediately, and the previously started INIT IPI would continue. OR
  969          * the previous INIT IPI has already run. and this STARTUP IPI will
  970          * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
  971          * will run.
  972          */
  973 
  974         /* do a STARTUP IPI */
  975         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
  976             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
  977             vector, apic_id);
  978         lapic_ipi_wait(-1);
  979         DELAY(200);             /* wait ~200uS */
  980 
  981         /*
  982          * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
  983          * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
  984          * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
  985          * recognized after hardware RESET or INIT IPI.
  986          */
  987 
  988         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
  989             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
  990             vector, apic_id);
  991         lapic_ipi_wait(-1);
  992         DELAY(200);             /* wait ~200uS */
  993 
  994         /* Wait up to 5 seconds for it to start. */
  995         for (ms = 0; ms < 5000; ms++) {
  996                 if (mp_naps > cpus)
  997                         return 1;       /* return SUCCESS */
  998                 DELAY(1000);
  999         }
 1000         return 0;               /* return FAILURE */
 1001 }
 1002 
 1003 #ifdef COUNT_XINVLTLB_HITS
 1004 u_int xhits_gbl[MAXCPU];
 1005 u_int xhits_pg[MAXCPU];
 1006 u_int xhits_rng[MAXCPU];
 1007 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
 1008 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
 1009     sizeof(xhits_gbl), "IU", "");
 1010 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
 1011     sizeof(xhits_pg), "IU", "");
 1012 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
 1013     sizeof(xhits_rng), "IU", "");
 1014 
 1015 u_int ipi_global;
 1016 u_int ipi_page;
 1017 u_int ipi_range;
 1018 u_int ipi_range_size;
 1019 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
 1020 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
 1021 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
 1022 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
 1023     0, "");
 1024 
 1025 u_int ipi_masked_global;
 1026 u_int ipi_masked_page;
 1027 u_int ipi_masked_range;
 1028 u_int ipi_masked_range_size;
 1029 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
 1030     &ipi_masked_global, 0, "");
 1031 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
 1032     &ipi_masked_page, 0, "");
 1033 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
 1034     &ipi_masked_range, 0, "");
 1035 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
 1036     &ipi_masked_range_size, 0, "");
 1037 #endif /* COUNT_XINVLTLB_HITS */
 1038 
 1039 /*
 1040  * Flush the TLB on all other CPU's
 1041  */
 1042 static void
 1043 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1044 {
 1045         u_int ncpu;
 1046 
 1047         ncpu = mp_ncpus - 1;    /* does not shootdown self */
 1048         if (ncpu < 1)
 1049                 return;         /* no other cpus */
 1050         if (!(read_eflags() & PSL_I))
 1051                 panic("%s: interrupts disabled", __func__);
 1052         mtx_lock_spin(&smp_ipi_mtx);
 1053         smp_tlb_addr1 = addr1;
 1054         smp_tlb_addr2 = addr2;
 1055         atomic_store_rel_int(&smp_tlb_wait, 0);
 1056         ipi_all_but_self(vector);
 1057         while (smp_tlb_wait < ncpu)
 1058                 ia32_pause();
 1059         mtx_unlock_spin(&smp_ipi_mtx);
 1060 }
 1061 
 1062 static void
 1063 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1064 {
 1065         int ncpu, othercpus;
 1066 
 1067         othercpus = mp_ncpus - 1;
 1068         if (mask == (u_int)-1) {
 1069                 ncpu = othercpus;
 1070                 if (ncpu < 1)
 1071                         return;
 1072         } else {
 1073                 mask &= ~PCPU_GET(cpumask);
 1074                 if (mask == 0)
 1075                         return;
 1076                 ncpu = bitcount32(mask);
 1077                 if (ncpu > othercpus) {
 1078                         /* XXX this should be a panic offence */
 1079                         printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
 1080                             ncpu, othercpus);
 1081                         ncpu = othercpus;
 1082                 }
 1083                 /* XXX should be a panic, implied by mask == 0 above */
 1084                 if (ncpu < 1)
 1085                         return;
 1086         }
 1087         if (!(read_eflags() & PSL_I))
 1088                 panic("%s: interrupts disabled", __func__);
 1089         mtx_lock_spin(&smp_ipi_mtx);
 1090         smp_tlb_addr1 = addr1;
 1091         smp_tlb_addr2 = addr2;
 1092         atomic_store_rel_int(&smp_tlb_wait, 0);
 1093         if (mask == (u_int)-1)
 1094                 ipi_all_but_self(vector);
 1095         else
 1096                 ipi_selected(mask, vector);
 1097         while (smp_tlb_wait < ncpu)
 1098                 ia32_pause();
 1099         mtx_unlock_spin(&smp_ipi_mtx);
 1100 }
 1101 
 1102 void
 1103 smp_cache_flush(void)
 1104 {
 1105 
 1106         if (smp_started)
 1107                 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
 1108 }
 1109 
 1110 void
 1111 smp_invltlb(void)
 1112 {
 1113 
 1114         if (smp_started) {
 1115                 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
 1116 #ifdef COUNT_XINVLTLB_HITS
 1117                 ipi_global++;
 1118 #endif
 1119         }
 1120 }
 1121 
 1122 void
 1123 smp_invlpg(vm_offset_t addr)
 1124 {
 1125 
 1126         if (smp_started) {
 1127                 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
 1128 #ifdef COUNT_XINVLTLB_HITS
 1129                 ipi_page++;
 1130 #endif
 1131         }
 1132 }
 1133 
 1134 void
 1135 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
 1136 {
 1137 
 1138         if (smp_started) {
 1139                 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
 1140 #ifdef COUNT_XINVLTLB_HITS
 1141                 ipi_range++;
 1142                 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
 1143 #endif
 1144         }
 1145 }
 1146 
 1147 void
 1148 smp_masked_invltlb(u_int mask)
 1149 {
 1150 
 1151         if (smp_started) {
 1152                 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
 1153 #ifdef COUNT_XINVLTLB_HITS
 1154                 ipi_masked_global++;
 1155 #endif
 1156         }
 1157 }
 1158 
 1159 void
 1160 smp_masked_invlpg(u_int mask, vm_offset_t addr)
 1161 {
 1162 
 1163         if (smp_started) {
 1164                 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
 1165 #ifdef COUNT_XINVLTLB_HITS
 1166                 ipi_masked_page++;
 1167 #endif
 1168         }
 1169 }
 1170 
 1171 void
 1172 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
 1173 {
 1174 
 1175         if (smp_started) {
 1176                 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
 1177 #ifdef COUNT_XINVLTLB_HITS
 1178                 ipi_masked_range++;
 1179                 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
 1180 #endif
 1181         }
 1182 }
 1183 
 1184 
 1185 void
 1186 ipi_bitmap_handler(struct clockframe frame)
 1187 {
 1188         int cpu = PCPU_GET(cpuid);
 1189         u_int ipi_bitmap;
 1190 
 1191         ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
 1192 
 1193 #ifdef IPI_PREEMPTION
 1194         if (ipi_bitmap & (1 << IPI_PREEMPT)) {
 1195 #ifdef COUNT_IPIS
 1196                 *ipi_preempt_counts[cpu]++;
 1197 #endif
 1198                 mtx_lock_spin(&sched_lock);
 1199                 /* Don't preempt the idle thread */
 1200                 if (curthread != PCPU_GET(idlethread)) {
 1201                         struct thread *running_thread = curthread;
 1202                         if (running_thread->td_critnest > 1) 
 1203                                 running_thread->td_owepreempt = 1;
 1204                         else            
 1205                                 mi_switch(SW_INVOL | SW_PREEMPT, NULL);
 1206                 }
 1207                 mtx_unlock_spin(&sched_lock);
 1208         }
 1209 #endif
 1210 
 1211         if (ipi_bitmap & (1 << IPI_AST)) {
 1212 #ifdef COUNT_IPIS
 1213                 *ipi_ast_counts[cpu]++;
 1214 #endif
 1215                 /* Nothing to do for AST */
 1216         }
 1217 }
 1218 
 1219 /*
 1220  * send an IPI to a set of cpus.
 1221  */
 1222 void
 1223 ipi_selected(u_int32_t cpus, u_int ipi)
 1224 {
 1225         int cpu;
 1226         u_int bitmap = 0;
 1227         u_int old_pending;
 1228         u_int new_pending;
 1229 
 1230         if (IPI_IS_BITMAPED(ipi)) { 
 1231                 bitmap = 1 << ipi;
 1232                 ipi = IPI_BITMAP_VECTOR;
 1233         }
 1234 
 1235         CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
 1236         while ((cpu = ffs(cpus)) != 0) {
 1237                 cpu--;
 1238                 cpus &= ~(1 << cpu);
 1239 
 1240                 KASSERT(cpu_apic_ids[cpu] != -1,
 1241                     ("IPI to non-existent CPU %d", cpu));
 1242 
 1243                 if (bitmap) {
 1244                         do {
 1245                                 old_pending = cpu_ipi_pending[cpu];
 1246                                 new_pending = old_pending | bitmap;
 1247                         } while  (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));  
 1248 
 1249                         if (old_pending)
 1250                                 continue;
 1251                 }
 1252 
 1253                 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
 1254         }
 1255 
 1256 }
 1257 
 1258 /*
 1259  * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
 1260  */
 1261 void
 1262 ipi_all(u_int ipi)
 1263 {
 1264 
 1265         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1266         lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
 1267 }
 1268 
 1269 /*
 1270  * send an IPI to all CPUs EXCEPT myself
 1271  */
 1272 void
 1273 ipi_all_but_self(u_int ipi)
 1274 {
 1275 
 1276         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1277         lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
 1278 }
 1279 
 1280 /*
 1281  * send an IPI to myself
 1282  */
 1283 void
 1284 ipi_self(u_int ipi)
 1285 {
 1286 
 1287         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1288         lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
 1289 }
 1290 
 1291 #ifdef KDB_STOP_NMI
 1292 /*
 1293  * send NMI IPI to selected CPUs
 1294  */
 1295 
 1296 #define BEFORE_SPIN     1000000
 1297 
 1298 void
 1299 ipi_nmi_selected(u_int32_t cpus)
 1300 {
 1301 
 1302         int cpu;
 1303         register_t icrlo;
 1304 
 1305         icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 
 1306                 | APIC_TRIGMOD_EDGE; 
 1307         
 1308         CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus);
 1309 
 1310 
 1311         atomic_set_int(&ipi_nmi_pending, cpus);
 1312 
 1313 
 1314         while ((cpu = ffs(cpus)) != 0) {
 1315                 cpu--;
 1316                 cpus &= ~(1 << cpu);
 1317 
 1318                 KASSERT(cpu_apic_ids[cpu] != -1,
 1319                     ("IPI NMI to non-existent CPU %d", cpu));
 1320                 
 1321                 /* Wait for an earlier IPI to finish. */
 1322                 if (!lapic_ipi_wait(BEFORE_SPIN))
 1323                         panic("ipi_nmi_selected: previous IPI has not cleared");
 1324 
 1325                 lapic_ipi_raw(icrlo,cpu_apic_ids[cpu]);
 1326         }
 1327 }
 1328 
 1329 
 1330 int
 1331 ipi_nmi_handler()
 1332 {
 1333         int cpu  = PCPU_GET(cpuid);
 1334 
 1335         if(!(atomic_load_acq_int(&ipi_nmi_pending) & (1 << cpu)))
 1336                 return 1;
 1337 
 1338         atomic_clear_int(&ipi_nmi_pending,1 << cpu);
 1339 
 1340         savectx(&stoppcbs[cpu]);
 1341 
 1342         /* Indicate that we are stopped */
 1343         atomic_set_int(&stopped_cpus,1 << cpu);
 1344 
 1345 
 1346         /* Wait for restart */
 1347         while(!(atomic_load_acq_int(&started_cpus) & (1 << cpu)))
 1348             ia32_pause();
 1349 
 1350         atomic_clear_int(&started_cpus,1 << cpu);
 1351         atomic_clear_int(&stopped_cpus,1 << cpu);
 1352 
 1353         if(cpu == 0 && cpustop_restartfunc != NULL)
 1354                 cpustop_restartfunc();
 1355 
 1356         return 0;
 1357 }
 1358      
 1359 #endif /* KDB_STOP_NMI */
 1360 
 1361 /*
 1362  * This is called once the rest of the system is up and running and we're
 1363  * ready to let the AP's out of the pen.
 1364  */
 1365 static void
 1366 release_aps(void *dummy __unused)
 1367 {
 1368 
 1369         if (mp_ncpus == 1) 
 1370                 return;
 1371         mtx_lock_spin(&sched_lock);
 1372         atomic_store_rel_int(&aps_ready, 1);
 1373         while (smp_started == 0)
 1374                 ia32_pause();
 1375         mtx_unlock_spin(&sched_lock);
 1376 }
 1377 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
 1378 
 1379 static int
 1380 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
 1381 {
 1382         u_int mask;
 1383         int error;
 1384 
 1385         mask = hlt_cpus_mask;
 1386         error = sysctl_handle_int(oidp, &mask, 0, req);
 1387         if (error || !req->newptr)
 1388                 return (error);
 1389 
 1390         if (logical_cpus_mask != 0 &&
 1391             (mask & logical_cpus_mask) == logical_cpus_mask)
 1392                 hlt_logical_cpus = 1;
 1393         else
 1394                 hlt_logical_cpus = 0;
 1395 
 1396         if (! hyperthreading_allowed)
 1397                 mask |= hyperthreading_cpus_mask;
 1398 
 1399         if ((mask & all_cpus) == all_cpus)
 1400                 mask &= ~(1<<0);
 1401         hlt_cpus_mask = mask;
 1402         return (error);
 1403 }
 1404 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
 1405     0, 0, sysctl_hlt_cpus, "IU",
 1406     "Bitmap of CPUs to halt.  101 (binary) will halt CPUs 0 and 2.");
 1407 
 1408 static int
 1409 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
 1410 {
 1411         int disable, error;
 1412 
 1413         disable = hlt_logical_cpus;
 1414         error = sysctl_handle_int(oidp, &disable, 0, req);
 1415         if (error || !req->newptr)
 1416                 return (error);
 1417 
 1418         if (disable)
 1419                 hlt_cpus_mask |= logical_cpus_mask;
 1420         else
 1421                 hlt_cpus_mask &= ~logical_cpus_mask;
 1422 
 1423         if (! hyperthreading_allowed)
 1424                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1425 
 1426         if ((hlt_cpus_mask & all_cpus) == all_cpus)
 1427                 hlt_cpus_mask &= ~(1<<0);
 1428 
 1429         hlt_logical_cpus = disable;
 1430         return (error);
 1431 }
 1432 
 1433 static int
 1434 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
 1435 {
 1436         int allowed, error;
 1437 
 1438         allowed = hyperthreading_allowed;
 1439         error = sysctl_handle_int(oidp, &allowed, 0, req);
 1440         if (error || !req->newptr)
 1441                 return (error);
 1442 
 1443         if (allowed)
 1444                 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
 1445         else
 1446                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1447 
 1448         if (logical_cpus_mask != 0 &&
 1449             (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
 1450                 hlt_logical_cpus = 1;
 1451         else
 1452                 hlt_logical_cpus = 0;
 1453 
 1454         if ((hlt_cpus_mask & all_cpus) == all_cpus)
 1455                 hlt_cpus_mask &= ~(1<<0);
 1456 
 1457         hyperthreading_allowed = allowed;
 1458         return (error);
 1459 }
 1460 
 1461 static void
 1462 cpu_hlt_setup(void *dummy __unused)
 1463 {
 1464 
 1465         if (logical_cpus_mask != 0) {
 1466                 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
 1467                     &hlt_logical_cpus);
 1468                 sysctl_ctx_init(&logical_cpu_clist);
 1469                 SYSCTL_ADD_PROC(&logical_cpu_clist,
 1470                     SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1471                     "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
 1472                     sysctl_hlt_logical_cpus, "IU", "");
 1473                 SYSCTL_ADD_UINT(&logical_cpu_clist,
 1474                     SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1475                     "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
 1476                     &logical_cpus_mask, 0, "");
 1477 
 1478                 if (hlt_logical_cpus)
 1479                         hlt_cpus_mask |= logical_cpus_mask;
 1480 
 1481                 /*
 1482                  * If necessary for security purposes, force
 1483                  * hyperthreading off, regardless of the value
 1484                  * of hlt_logical_cpus.
 1485                  */
 1486                 if (hyperthreading_cpus_mask) {
 1487                         TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
 1488                             &hyperthreading_allowed);
 1489                         SYSCTL_ADD_PROC(&logical_cpu_clist,
 1490                             SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1491                             "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
 1492                             0, 0, sysctl_hyperthreading_allowed, "IU", "");
 1493                         if (! hyperthreading_allowed)
 1494                                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1495                 }
 1496         }
 1497 }
 1498 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
 1499 
 1500 int
 1501 mp_grab_cpu_hlt(void)
 1502 {
 1503         u_int mask = PCPU_GET(cpumask);
 1504 #ifdef MP_WATCHDOG
 1505         u_int cpuid = PCPU_GET(cpuid);
 1506 #endif
 1507         int retval;
 1508 
 1509 #ifdef MP_WATCHDOG
 1510         ap_watchdog(cpuid);
 1511 #endif
 1512 
 1513         retval = mask & hlt_cpus_mask;
 1514         while (mask & hlt_cpus_mask)
 1515                 __asm __volatile("sti; hlt" : : : "memory");
 1516         return (retval);
 1517 }
 1518 
 1519 #ifdef COUNT_IPIS
 1520 /*
 1521  * Setup interrupt counters for IPI handlers.
 1522  */
 1523 static void
 1524 mp_ipi_intrcnt(void *dummy)
 1525 {
 1526         char buf[64];
 1527         int i;
 1528 
 1529         for (i = 0; i < mp_maxid; i++) {
 1530                 if (CPU_ABSENT(i))
 1531                         continue;
 1532                 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i);
 1533                 intrcnt_add(buf, &ipi_invltlb_counts[i]);
 1534                 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i);
 1535                 intrcnt_add(buf, &ipi_invlrng_counts[i]);
 1536                 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i);
 1537                 intrcnt_add(buf, &ipi_invlpg_counts[i]);
 1538 #ifdef IPI_PREEMPTION
 1539                 snprintf(buf, sizeof(buf), "cpu%d: preempt", i);
 1540                 intrcnt_add(buf, &ipi_preempt_counts[i]);
 1541 #endif
 1542                 snprintf(buf, sizeof(buf), "cpu%d: ast", i);
 1543                 intrcnt_add(buf, &ipi_ast_counts[i]);
 1544                 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i);
 1545                 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
 1546                 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i);
 1547                 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
 1548         }               
 1549 }
 1550 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL)
 1551 #endif

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