1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include "opt_apic.h"
30 #include "opt_cpu.h"
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
33 #include "opt_sched.h"
34 #include "opt_smp.h"
35
36 #if !defined(lint)
37 #if !defined(SMP)
38 #error How did you get here?
39 #endif
40
41 #ifndef DEV_APIC
42 #error The apic device is required for SMP, add "device apic" to your config file.
43 #endif
44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
45 #error SMP not supported with CPU_DISABLE_CMPXCHG
46 #endif
47 #endif /* not lint */
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/bus.h>
52 #include <sys/cons.h> /* cngetc() */
53 #ifdef GPROF
54 #include <sys/gmon.h>
55 #endif
56 #include <sys/kernel.h>
57 #include <sys/ktr.h>
58 #include <sys/lock.h>
59 #include <sys/malloc.h>
60 #include <sys/memrange.h>
61 #include <sys/mutex.h>
62 #include <sys/pcpu.h>
63 #include <sys/proc.h>
64 #include <sys/sched.h>
65 #include <sys/smp.h>
66 #include <sys/sysctl.h>
67
68 #include <vm/vm.h>
69 #include <vm/vm_param.h>
70 #include <vm/pmap.h>
71 #include <vm/vm_kern.h>
72 #include <vm/vm_extern.h>
73
74 #include <machine/apicreg.h>
75 #include <machine/md_var.h>
76 #include <machine/mp_watchdog.h>
77 #include <machine/pcb.h>
78 #include <machine/psl.h>
79 #include <machine/smp.h>
80 #include <machine/specialreg.h>
81
82 #define WARMBOOT_TARGET 0
83 #define WARMBOOT_OFF (KERNBASE + 0x0467)
84 #define WARMBOOT_SEG (KERNBASE + 0x0469)
85
86 #define CMOS_REG (0x70)
87 #define CMOS_DATA (0x71)
88 #define BIOS_RESET (0x0f)
89 #define BIOS_WARM (0x0a)
90
91 /*
92 * this code MUST be enabled here and in mpboot.s.
93 * it follows the very early stages of AP boot by placing values in CMOS ram.
94 * it NORMALLY will never be needed and thus the primitive method for enabling.
95 *
96 #define CHECK_POINTS
97 */
98
99 #if defined(CHECK_POINTS) && !defined(PC98)
100 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
101 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
102
103 #define CHECK_INIT(D); \
104 CHECK_WRITE(0x34, (D)); \
105 CHECK_WRITE(0x35, (D)); \
106 CHECK_WRITE(0x36, (D)); \
107 CHECK_WRITE(0x37, (D)); \
108 CHECK_WRITE(0x38, (D)); \
109 CHECK_WRITE(0x39, (D));
110
111 #define CHECK_PRINT(S); \
112 printf("%s: %d, %d, %d, %d, %d, %d\n", \
113 (S), \
114 CHECK_READ(0x34), \
115 CHECK_READ(0x35), \
116 CHECK_READ(0x36), \
117 CHECK_READ(0x37), \
118 CHECK_READ(0x38), \
119 CHECK_READ(0x39));
120
121 #else /* CHECK_POINTS */
122
123 #define CHECK_INIT(D)
124 #define CHECK_PRINT(S)
125 #define CHECK_WRITE(A, D)
126
127 #endif /* CHECK_POINTS */
128
129 /* lock region used by kernel profiling */
130 int mcount_lock;
131
132 int mp_naps; /* # of Applications processors */
133 int boot_cpu_id = -1; /* designated BSP */
134 extern int nkpt;
135
136 extern struct pcpu __pcpu[];
137
138 /*
139 * CPU topology map datastructures for HTT.
140 */
141 static struct cpu_group mp_groups[MAXCPU];
142 static struct cpu_top mp_top;
143
144 /* AP uses this during bootstrap. Do not staticize. */
145 char *bootSTK;
146 static int bootAP;
147
148 /* Free these after use */
149 void *bootstacks[MAXCPU];
150
151 /* Hotwire a 0->4MB V==P mapping */
152 extern pt_entry_t *KPTphys;
153
154 struct pcb stoppcbs[MAXCPU];
155
156 /* Variables needed for SMP tlb shootdown. */
157 vm_offset_t smp_tlb_addr1;
158 vm_offset_t smp_tlb_addr2;
159 volatile int smp_tlb_wait;
160
161 #ifdef STOP_NMI
162 volatile cpumask_t ipi_nmi_pending;
163
164 static void ipi_nmi_selected(u_int32_t cpus);
165 #endif
166
167 #ifdef COUNT_IPIS
168 /* Interrupt counts. */
169 static u_long *ipi_preempt_counts[MAXCPU];
170 static u_long *ipi_ast_counts[MAXCPU];
171 u_long *ipi_invltlb_counts[MAXCPU];
172 u_long *ipi_invlrng_counts[MAXCPU];
173 u_long *ipi_invlpg_counts[MAXCPU];
174 u_long *ipi_invlcache_counts[MAXCPU];
175 u_long *ipi_rendezvous_counts[MAXCPU];
176 u_long *ipi_lazypmap_counts[MAXCPU];
177 #endif
178
179 /*
180 * Local data and functions.
181 */
182
183 #ifdef STOP_NMI
184 /*
185 * Provide an alternate method of stopping other CPUs. If another CPU has
186 * disabled interrupts the conventional STOP IPI will be blocked. This
187 * NMI-based stop should get through in that case.
188 */
189 static int stop_cpus_with_nmi = 1;
190 SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW,
191 &stop_cpus_with_nmi, 0, "");
192 TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi);
193 #else
194 #define stop_cpus_with_nmi 0
195 #endif
196
197 static u_int logical_cpus;
198
199 /* used to hold the AP's until we are ready to release them */
200 static struct mtx ap_boot_mtx;
201
202 /* Set to 1 once we're ready to let the APs out of the pen. */
203 static volatile int aps_ready = 0;
204
205 /*
206 * Store data from cpu_add() until later in the boot when we actually setup
207 * the APs.
208 */
209 struct cpu_info {
210 int cpu_present:1;
211 int cpu_bsp:1;
212 int cpu_disabled:1;
213 } static cpu_info[MAX_APIC_ID + 1];
214 int cpu_apic_ids[MAXCPU];
215
216 /* Holds pending bitmap based IPIs per CPU */
217 static volatile u_int cpu_ipi_pending[MAXCPU];
218
219 static u_int boot_address;
220
221 static void assign_cpu_ids(void);
222 static void install_ap_tramp(void);
223 static void set_interrupt_apic_ids(void);
224 static int start_all_aps(void);
225 static int start_ap(int apic_id);
226 static void release_aps(void *dummy);
227
228 static int hlt_logical_cpus;
229 static u_int hyperthreading_cpus;
230 static cpumask_t hyperthreading_cpus_mask;
231 static int hyperthreading_allowed = 1;
232 static struct sysctl_ctx_list logical_cpu_clist;
233
234 static void
235 mem_range_AP_init(void)
236 {
237 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
238 mem_range_softc.mr_op->initAP(&mem_range_softc);
239 }
240
241 void
242 mp_topology(void)
243 {
244 struct cpu_group *group;
245 int apic_id;
246 int groups;
247 int cpu;
248
249 /* Build the smp_topology map. */
250 /* Nothing to do if there is no HTT support. */
251 if (hyperthreading_cpus <= 1)
252 return;
253 group = &mp_groups[0];
254 groups = 1;
255 for (cpu = 0, apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
256 if (!cpu_info[apic_id].cpu_present)
257 continue;
258 /*
259 * If the current group has members and we're not a logical
260 * cpu, create a new group.
261 */
262 if (group->cg_count != 0 &&
263 (apic_id % hyperthreading_cpus) == 0) {
264 group++;
265 groups++;
266 }
267 group->cg_count++;
268 group->cg_mask |= 1 << cpu;
269 cpu++;
270 }
271
272 mp_top.ct_count = groups;
273 mp_top.ct_group = mp_groups;
274 smp_topology = &mp_top;
275 }
276
277
278 /*
279 * Calculate usable address in base memory for AP trampoline code.
280 */
281 u_int
282 mp_bootaddress(u_int basemem)
283 {
284
285 boot_address = trunc_page(basemem); /* round down to 4k boundary */
286 if ((basemem - boot_address) < bootMP_size)
287 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
288
289 return boot_address;
290 }
291
292 void
293 cpu_add(u_int apic_id, char boot_cpu)
294 {
295
296 if (apic_id > MAX_APIC_ID) {
297 panic("SMP: APIC ID %d too high", apic_id);
298 return;
299 }
300 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
301 apic_id));
302 cpu_info[apic_id].cpu_present = 1;
303 if (boot_cpu) {
304 KASSERT(boot_cpu_id == -1,
305 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
306 boot_cpu_id));
307 boot_cpu_id = apic_id;
308 cpu_info[apic_id].cpu_bsp = 1;
309 }
310 if (mp_ncpus < MAXCPU)
311 mp_ncpus++;
312 if (bootverbose)
313 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
314 "AP");
315 }
316
317 void
318 cpu_mp_setmaxid(void)
319 {
320
321 mp_maxid = MAXCPU - 1;
322 }
323
324 int
325 cpu_mp_probe(void)
326 {
327
328 /*
329 * Always record BSP in CPU map so that the mbuf init code works
330 * correctly.
331 */
332 all_cpus = 1;
333 if (mp_ncpus == 0) {
334 /*
335 * No CPUs were found, so this must be a UP system. Setup
336 * the variables to represent a system with a single CPU
337 * with an id of 0.
338 */
339 mp_ncpus = 1;
340 return (0);
341 }
342
343 /* At least one CPU was found. */
344 if (mp_ncpus == 1) {
345 /*
346 * One CPU was found, so this must be a UP system with
347 * an I/O APIC.
348 */
349 return (0);
350 }
351
352 /* At least two CPUs were found. */
353 return (1);
354 }
355
356 /*
357 * Initialize the IPI handlers and start up the AP's.
358 */
359 void
360 cpu_mp_start(void)
361 {
362 int i;
363 u_int threads_per_cache, p[4];
364
365 /* Initialize the logical ID to APIC ID table. */
366 for (i = 0; i < MAXCPU; i++) {
367 cpu_apic_ids[i] = -1;
368 cpu_ipi_pending[i] = 0;
369 }
370
371 /* Install an inter-CPU IPI for TLB invalidation */
372 setidt(IPI_INVLTLB, IDTVEC(invltlb),
373 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
374 setidt(IPI_INVLPG, IDTVEC(invlpg),
375 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
376 setidt(IPI_INVLRNG, IDTVEC(invlrng),
377 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
378
379 /* Install an inter-CPU IPI for cache invalidation. */
380 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
381 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
382
383 /* Install an inter-CPU IPI for lazy pmap release */
384 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
385 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
386
387 /* Install an inter-CPU IPI for all-CPU rendezvous */
388 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
389 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
390
391 /* Install generic inter-CPU IPI handler */
392 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
393 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
394
395 /* Install an inter-CPU IPI for CPU stop/restart */
396 setidt(IPI_STOP, IDTVEC(cpustop),
397 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
398
399
400 /* Set boot_cpu_id if needed. */
401 if (boot_cpu_id == -1) {
402 boot_cpu_id = PCPU_GET(apic_id);
403 cpu_info[boot_cpu_id].cpu_bsp = 1;
404 } else
405 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
406 ("BSP's APIC ID doesn't match boot_cpu_id"));
407 cpu_apic_ids[0] = boot_cpu_id;
408
409 assign_cpu_ids();
410
411 /* Start each Application Processor */
412 start_all_aps();
413
414 /* Setup the initial logical CPUs info. */
415 logical_cpus = logical_cpus_mask = 0;
416 if (cpu_feature & CPUID_HTT)
417 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
418
419 /*
420 * Work out if hyperthreading is *really* enabled. This
421 * is made really ugly by the fact that processors lie: Dual
422 * core processors claim to be hyperthreaded even when they're
423 * not, presumably because they want to be treated the same
424 * way as HTT with respect to per-cpu software licensing.
425 * At the time of writing (May 12, 2005) the only hyperthreaded
426 * cpus are from Intel, and Intel's dual-core processors can be
427 * identified via the "deterministic cache parameters" cpuid
428 * calls.
429 */
430 /*
431 * First determine if this is an Intel processor which claims
432 * to have hyperthreading support.
433 */
434 if ((cpu_feature & CPUID_HTT) &&
435 (strcmp(cpu_vendor, "GenuineIntel") == 0)) {
436 /*
437 * If the "deterministic cache parameters" cpuid calls
438 * are available, use them.
439 */
440 if (cpu_high >= 4) {
441 /* Ask the processor about the L1 cache. */
442 for (i = 0; i < 1; i++) {
443 cpuid_count(4, i, p);
444 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
445 if (hyperthreading_cpus < threads_per_cache)
446 hyperthreading_cpus = threads_per_cache;
447 if ((p[0] & 0x1f) == 0)
448 break;
449 }
450 }
451
452 /*
453 * If the deterministic cache parameters are not
454 * available, or if no caches were reported to exist,
455 * just accept what the HTT flag indicated.
456 */
457 if (hyperthreading_cpus == 0)
458 hyperthreading_cpus = logical_cpus;
459 }
460
461 set_interrupt_apic_ids();
462
463 /* Last, setup the cpu topology now that we have probed CPUs */
464 mp_topology();
465 }
466
467
468 /*
469 * Print various information about the SMP system hardware and setup.
470 */
471 void
472 cpu_mp_announce(void)
473 {
474 int i, x;
475
476 /* List CPUs */
477 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
478 for (i = 1, x = 0; x <= MAX_APIC_ID; x++) {
479 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp)
480 continue;
481 if (cpu_info[x].cpu_disabled)
482 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x);
483 else {
484 KASSERT(i < mp_ncpus,
485 ("mp_ncpus and actual cpus are out of whack"));
486 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x);
487 }
488 }
489 }
490
491 /*
492 * AP CPU's call this to initialize themselves.
493 */
494 void
495 init_secondary(void)
496 {
497 struct pcpu *pc;
498 vm_offset_t addr;
499 int gsel_tss;
500 int x, myid;
501 u_int cr0;
502
503 /* bootAP is set in start_ap() to our ID. */
504 myid = bootAP;
505
506 /* Get per-cpu data */
507 pc = &__pcpu[myid];
508
509 /* prime data page for it to use */
510 pcpu_init(pc, myid, sizeof(struct pcpu));
511 pc->pc_apic_id = cpu_apic_ids[myid];
512 pc->pc_prvspace = pc;
513 pc->pc_curthread = 0;
514
515 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
516 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
517
518 for (x = 0; x < NGDT; x++) {
519 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
520 }
521
522 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
523 r_gdt.rd_base = (int) &gdt[myid * NGDT];
524 lgdt(&r_gdt); /* does magic intra-segment return */
525
526 lidt(&r_idt);
527
528 lldt(_default_ldt);
529 PCPU_SET(currentldt, _default_ldt);
530
531 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
532 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
533 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
534 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
535 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
536 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
537 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
538 ltr(gsel_tss);
539
540 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
541
542 /*
543 * Set to a known state:
544 * Set by mpboot.s: CR0_PG, CR0_PE
545 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
546 */
547 cr0 = rcr0();
548 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
549 load_cr0(cr0);
550 CHECK_WRITE(0x38, 5);
551
552 /* Disable local APIC just to be sure. */
553 lapic_disable();
554
555 /* signal our startup to the BSP. */
556 mp_naps++;
557 CHECK_WRITE(0x39, 6);
558
559 /* Spin until the BSP releases the AP's. */
560 while (!aps_ready)
561 ia32_pause();
562
563 /* BSP may have changed PTD while we were waiting */
564 invltlb();
565 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
566 invlpg(addr);
567
568 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
569 lidt(&r_idt);
570 #endif
571
572 /* Initialize the PAT MSR if present. */
573 pmap_init_pat();
574
575 /* set up CPU registers and state */
576 cpu_setregs();
577
578 /* set up FPU state on the AP */
579 npxinit(__INITIAL_NPXCW__);
580
581 /* set up SSE registers */
582 enable_sse();
583
584 #ifdef PAE
585 /* Enable the PTE no-execute bit. */
586 if ((amd_feature & AMDID_NX) != 0) {
587 uint64_t msr;
588
589 msr = rdmsr(MSR_EFER) | EFER_NXE;
590 wrmsr(MSR_EFER, msr);
591 }
592 #endif
593
594 /* A quick check from sanity claus */
595 if (PCPU_GET(apic_id) != lapic_id()) {
596 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
597 printf("SMP: actual apic_id = %d\n", lapic_id());
598 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
599 panic("cpuid mismatch! boom!!");
600 }
601
602 /* Initialize curthread. */
603 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
604 PCPU_SET(curthread, PCPU_GET(idlethread));
605
606 mtx_lock_spin(&ap_boot_mtx);
607
608 /* Init local apic for irq's */
609 lapic_setup(1);
610
611 /* Set memory range attributes for this CPU to match the BSP */
612 mem_range_AP_init();
613
614 smp_cpus++;
615
616 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
617 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
618
619 /* Determine if we are a logical CPU. */
620 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
621 logical_cpus_mask |= PCPU_GET(cpumask);
622
623 /* Determine if we are a hyperthread. */
624 if (hyperthreading_cpus > 1 &&
625 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
626 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
627
628 /* Build our map of 'other' CPUs. */
629 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
630
631 if (bootverbose)
632 lapic_dump("AP");
633
634 if (smp_cpus == mp_ncpus) {
635 /* enable IPI's, tlb shootdown, freezes etc */
636 atomic_store_rel_int(&smp_started, 1);
637 smp_active = 1; /* historic */
638 }
639
640 mtx_unlock_spin(&ap_boot_mtx);
641
642 /* wait until all the AP's are up */
643 while (smp_started == 0)
644 ia32_pause();
645
646 /* enter the scheduler */
647 sched_throw(NULL);
648
649 panic("scheduler returned us to %s", __func__);
650 /* NOTREACHED */
651 }
652
653 /*******************************************************************
654 * local functions and data
655 */
656
657 /*
658 * We tell the I/O APIC code about all the CPUs we want to receive
659 * interrupts. If we don't want certain CPUs to receive IRQs we
660 * can simply not tell the I/O APIC code about them in this function.
661 * We also do not tell it about the BSP since it tells itself about
662 * the BSP internally to work with UP kernels and on UP machines.
663 */
664 static void
665 set_interrupt_apic_ids(void)
666 {
667 u_int i, apic_id;
668
669 for (i = 0; i < MAXCPU; i++) {
670 apic_id = cpu_apic_ids[i];
671 if (apic_id == -1)
672 continue;
673 if (cpu_info[apic_id].cpu_bsp)
674 continue;
675 if (cpu_info[apic_id].cpu_disabled)
676 continue;
677
678 /* Don't let hyperthreads service interrupts. */
679 if (hyperthreading_cpus > 1 &&
680 apic_id % hyperthreading_cpus != 0)
681 continue;
682
683 intr_add_cpu(i);
684 }
685 }
686
687 /*
688 * Assign logical CPU IDs to local APICs.
689 */
690 static void
691 assign_cpu_ids(void)
692 {
693 u_int i;
694
695 /* Check for explicitly disabled CPUs. */
696 for (i = 0; i <= MAX_APIC_ID; i++) {
697 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
698 continue;
699
700 /* Don't use this CPU if it has been disabled by a tunable. */
701 if (resource_disabled("lapic", i)) {
702 cpu_info[i].cpu_disabled = 1;
703 continue;
704 }
705 }
706
707 /*
708 * Assign CPU IDs to local APIC IDs and disable any CPUs
709 * beyond MAXCPU. CPU 0 has already been assigned to the BSP,
710 * so we only have to assign IDs for APs.
711 */
712 mp_ncpus = 1;
713 for (i = 0; i <= MAX_APIC_ID; i++) {
714 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
715 cpu_info[i].cpu_disabled)
716 continue;
717
718 if (mp_ncpus < MAXCPU) {
719 cpu_apic_ids[mp_ncpus] = i;
720 mp_ncpus++;
721 } else
722 cpu_info[i].cpu_disabled = 1;
723 }
724 KASSERT(mp_maxid >= mp_ncpus - 1,
725 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
726 mp_ncpus));
727 }
728
729 /*
730 * start each AP in our list
731 */
732 static int
733 start_all_aps(void)
734 {
735 #ifndef PC98
736 u_char mpbiosreason;
737 #endif
738 uintptr_t kptbase;
739 u_int32_t mpbioswarmvec;
740 int apic_id, cpu, i;
741
742 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
743
744 /* install the AP 1st level boot code */
745 install_ap_tramp();
746
747 /* save the current value of the warm-start vector */
748 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
749 #ifndef PC98
750 outb(CMOS_REG, BIOS_RESET);
751 mpbiosreason = inb(CMOS_DATA);
752 #endif
753
754 /* set up temporary P==V mapping for AP boot */
755 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
756 kptbase = (uintptr_t)(void *)KPTphys;
757 for (i = 0; i < NKPT; i++)
758 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
759 ((kptbase + i * PAGE_SIZE) & PG_FRAME));
760 invltlb();
761
762 /* start each AP */
763 for (cpu = 1; cpu < mp_ncpus; cpu++) {
764 apic_id = cpu_apic_ids[cpu];
765
766 /* allocate and set up a boot stack data page */
767 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
768
769 /* setup a vector to our boot code */
770 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
771 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
772 #ifndef PC98
773 outb(CMOS_REG, BIOS_RESET);
774 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
775 #endif
776
777 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
778 bootAP = cpu;
779
780 /* attempt to start the Application Processor */
781 CHECK_INIT(99); /* setup checkpoints */
782 if (!start_ap(apic_id)) {
783 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
784 CHECK_PRINT("trace"); /* show checkpoints */
785 /* better panic as the AP may be running loose */
786 printf("panic y/n? [y] ");
787 if (cngetc() != 'n')
788 panic("bye-bye");
789 }
790 CHECK_PRINT("trace"); /* show checkpoints */
791
792 all_cpus |= (1 << cpu); /* record AP in CPU map */
793 }
794
795 /* build our map of 'other' CPUs */
796 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
797
798 /* restore the warmstart vector */
799 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
800
801 #ifndef PC98
802 outb(CMOS_REG, BIOS_RESET);
803 outb(CMOS_DATA, mpbiosreason);
804 #endif
805
806 /* Undo V==P hack from above */
807 for (i = 0; i < NKPT; i++)
808 PTD[i] = 0;
809 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
810
811 /* number of APs actually started */
812 return mp_naps;
813 }
814
815 /*
816 * load the 1st level AP boot code into base memory.
817 */
818
819 /* targets for relocation */
820 extern void bigJump(void);
821 extern void bootCodeSeg(void);
822 extern void bootDataSeg(void);
823 extern void MPentry(void);
824 extern u_int MP_GDT;
825 extern u_int mp_gdtbase;
826
827 static void
828 install_ap_tramp(void)
829 {
830 int x;
831 int size = *(int *) ((u_long) & bootMP_size);
832 vm_offset_t va = boot_address + KERNBASE;
833 u_char *src = (u_char *) ((u_long) bootMP);
834 u_char *dst = (u_char *) va;
835 u_int boot_base = (u_int) bootMP;
836 u_int8_t *dst8;
837 u_int16_t *dst16;
838 u_int32_t *dst32;
839
840 KASSERT (size <= PAGE_SIZE,
841 ("'size' do not fit into PAGE_SIZE, as expected."));
842 pmap_kenter(va, boot_address);
843 pmap_invalidate_page (kernel_pmap, va);
844 for (x = 0; x < size; ++x)
845 *dst++ = *src++;
846
847 /*
848 * modify addresses in code we just moved to basemem. unfortunately we
849 * need fairly detailed info about mpboot.s for this to work. changes
850 * to mpboot.s might require changes here.
851 */
852
853 /* boot code is located in KERNEL space */
854 dst = (u_char *) va;
855
856 /* modify the lgdt arg */
857 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
858 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
859
860 /* modify the ljmp target for MPentry() */
861 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
862 *dst32 = ((u_int) MPentry - KERNBASE);
863
864 /* modify the target for boot code segment */
865 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
866 dst8 = (u_int8_t *) (dst16 + 1);
867 *dst16 = (u_int) boot_address & 0xffff;
868 *dst8 = ((u_int) boot_address >> 16) & 0xff;
869
870 /* modify the target for boot data segment */
871 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
872 dst8 = (u_int8_t *) (dst16 + 1);
873 *dst16 = (u_int) boot_address & 0xffff;
874 *dst8 = ((u_int) boot_address >> 16) & 0xff;
875 }
876
877 /*
878 * This function starts the AP (application processor) identified
879 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
880 * to accomplish this. This is necessary because of the nuances
881 * of the different hardware we might encounter. It isn't pretty,
882 * but it seems to work.
883 */
884 static int
885 start_ap(int apic_id)
886 {
887 int vector, ms;
888 int cpus;
889
890 /* calculate the vector */
891 vector = (boot_address >> 12) & 0xff;
892
893 /* used as a watchpoint to signal AP startup */
894 cpus = mp_naps;
895
896 /*
897 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
898 * and running the target CPU. OR this INIT IPI might be latched (P5
899 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
900 * ignored.
901 */
902
903 /* do an INIT IPI: assert RESET */
904 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
905 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
906
907 /* wait for pending status end */
908 lapic_ipi_wait(-1);
909
910 /* do an INIT IPI: deassert RESET */
911 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
912 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
913
914 /* wait for pending status end */
915 DELAY(10000); /* wait ~10mS */
916 lapic_ipi_wait(-1);
917
918 /*
919 * next we do a STARTUP IPI: the previous INIT IPI might still be
920 * latched, (P5 bug) this 1st STARTUP would then terminate
921 * immediately, and the previously started INIT IPI would continue. OR
922 * the previous INIT IPI has already run. and this STARTUP IPI will
923 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
924 * will run.
925 */
926
927 /* do a STARTUP IPI */
928 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
929 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
930 vector, apic_id);
931 lapic_ipi_wait(-1);
932 DELAY(200); /* wait ~200uS */
933
934 /*
935 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
936 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
937 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
938 * recognized after hardware RESET or INIT IPI.
939 */
940
941 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
942 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
943 vector, apic_id);
944 lapic_ipi_wait(-1);
945 DELAY(200); /* wait ~200uS */
946
947 /* Wait up to 5 seconds for it to start. */
948 for (ms = 0; ms < 5000; ms++) {
949 if (mp_naps > cpus)
950 return 1; /* return SUCCESS */
951 DELAY(1000);
952 }
953 return 0; /* return FAILURE */
954 }
955
956 #ifdef COUNT_XINVLTLB_HITS
957 u_int xhits_gbl[MAXCPU];
958 u_int xhits_pg[MAXCPU];
959 u_int xhits_rng[MAXCPU];
960 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
961 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
962 sizeof(xhits_gbl), "IU", "");
963 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
964 sizeof(xhits_pg), "IU", "");
965 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
966 sizeof(xhits_rng), "IU", "");
967
968 u_int ipi_global;
969 u_int ipi_page;
970 u_int ipi_range;
971 u_int ipi_range_size;
972 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
973 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
974 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
975 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
976 0, "");
977
978 u_int ipi_masked_global;
979 u_int ipi_masked_page;
980 u_int ipi_masked_range;
981 u_int ipi_masked_range_size;
982 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
983 &ipi_masked_global, 0, "");
984 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
985 &ipi_masked_page, 0, "");
986 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
987 &ipi_masked_range, 0, "");
988 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
989 &ipi_masked_range_size, 0, "");
990 #endif /* COUNT_XINVLTLB_HITS */
991
992 /*
993 * Flush the TLB on all other CPU's
994 */
995 static void
996 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
997 {
998 u_int ncpu;
999
1000 ncpu = mp_ncpus - 1; /* does not shootdown self */
1001 if (ncpu < 1)
1002 return; /* no other cpus */
1003 if (!(read_eflags() & PSL_I))
1004 panic("%s: interrupts disabled", __func__);
1005 mtx_lock_spin(&smp_ipi_mtx);
1006 smp_tlb_addr1 = addr1;
1007 smp_tlb_addr2 = addr2;
1008 atomic_store_rel_int(&smp_tlb_wait, 0);
1009 ipi_all_but_self(vector);
1010 while (smp_tlb_wait < ncpu)
1011 ia32_pause();
1012 mtx_unlock_spin(&smp_ipi_mtx);
1013 }
1014
1015 static void
1016 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1017 {
1018 int ncpu, othercpus;
1019
1020 othercpus = mp_ncpus - 1;
1021 if (mask == (u_int)-1) {
1022 ncpu = othercpus;
1023 if (ncpu < 1)
1024 return;
1025 } else {
1026 mask &= ~PCPU_GET(cpumask);
1027 if (mask == 0)
1028 return;
1029 ncpu = bitcount32(mask);
1030 if (ncpu > othercpus) {
1031 /* XXX this should be a panic offence */
1032 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
1033 ncpu, othercpus);
1034 ncpu = othercpus;
1035 }
1036 /* XXX should be a panic, implied by mask == 0 above */
1037 if (ncpu < 1)
1038 return;
1039 }
1040 if (!(read_eflags() & PSL_I))
1041 panic("%s: interrupts disabled", __func__);
1042 mtx_lock_spin(&smp_ipi_mtx);
1043 smp_tlb_addr1 = addr1;
1044 smp_tlb_addr2 = addr2;
1045 atomic_store_rel_int(&smp_tlb_wait, 0);
1046 if (mask == (u_int)-1)
1047 ipi_all_but_self(vector);
1048 else
1049 ipi_selected(mask, vector);
1050 while (smp_tlb_wait < ncpu)
1051 ia32_pause();
1052 mtx_unlock_spin(&smp_ipi_mtx);
1053 }
1054
1055 void
1056 smp_cache_flush(void)
1057 {
1058
1059 if (smp_started)
1060 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1061 }
1062
1063 void
1064 smp_invltlb(void)
1065 {
1066
1067 if (smp_started) {
1068 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1069 #ifdef COUNT_XINVLTLB_HITS
1070 ipi_global++;
1071 #endif
1072 }
1073 }
1074
1075 void
1076 smp_invlpg(vm_offset_t addr)
1077 {
1078
1079 if (smp_started) {
1080 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1081 #ifdef COUNT_XINVLTLB_HITS
1082 ipi_page++;
1083 #endif
1084 }
1085 }
1086
1087 void
1088 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1089 {
1090
1091 if (smp_started) {
1092 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1093 #ifdef COUNT_XINVLTLB_HITS
1094 ipi_range++;
1095 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1096 #endif
1097 }
1098 }
1099
1100 void
1101 smp_masked_invltlb(u_int mask)
1102 {
1103
1104 if (smp_started) {
1105 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1106 #ifdef COUNT_XINVLTLB_HITS
1107 ipi_masked_global++;
1108 #endif
1109 }
1110 }
1111
1112 void
1113 smp_masked_invlpg(u_int mask, vm_offset_t addr)
1114 {
1115
1116 if (smp_started) {
1117 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1118 #ifdef COUNT_XINVLTLB_HITS
1119 ipi_masked_page++;
1120 #endif
1121 }
1122 }
1123
1124 void
1125 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
1126 {
1127
1128 if (smp_started) {
1129 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1130 #ifdef COUNT_XINVLTLB_HITS
1131 ipi_masked_range++;
1132 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1133 #endif
1134 }
1135 }
1136
1137 void
1138 ipi_bitmap_handler(struct trapframe frame)
1139 {
1140 int cpu = PCPU_GET(cpuid);
1141 u_int ipi_bitmap;
1142
1143 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1144
1145 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1146 struct thread *running_thread = curthread;
1147 #ifdef COUNT_IPIS
1148 (*ipi_preempt_counts[cpu])++;
1149 #endif
1150 thread_lock(running_thread);
1151 if (running_thread->td_critnest > 1)
1152 running_thread->td_owepreempt = 1;
1153 else
1154 mi_switch(SW_INVOL | SW_PREEMPT, NULL);
1155 thread_unlock(running_thread);
1156 }
1157
1158 if (ipi_bitmap & (1 << IPI_AST)) {
1159 #ifdef COUNT_IPIS
1160 (*ipi_ast_counts[cpu])++;
1161 #endif
1162 /* Nothing to do for AST */
1163 }
1164 }
1165
1166 /*
1167 * send an IPI to a set of cpus.
1168 */
1169 void
1170 ipi_selected(u_int32_t cpus, u_int ipi)
1171 {
1172 int cpu;
1173 u_int bitmap = 0;
1174 u_int old_pending;
1175 u_int new_pending;
1176
1177 if (IPI_IS_BITMAPED(ipi)) {
1178 bitmap = 1 << ipi;
1179 ipi = IPI_BITMAP_VECTOR;
1180 }
1181
1182 #ifdef STOP_NMI
1183 if (ipi == IPI_STOP && stop_cpus_with_nmi) {
1184 ipi_nmi_selected(cpus);
1185 return;
1186 }
1187 #endif
1188 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
1189 while ((cpu = ffs(cpus)) != 0) {
1190 cpu--;
1191 cpus &= ~(1 << cpu);
1192
1193 KASSERT(cpu_apic_ids[cpu] != -1,
1194 ("IPI to non-existent CPU %d", cpu));
1195
1196 if (bitmap) {
1197 do {
1198 old_pending = cpu_ipi_pending[cpu];
1199 new_pending = old_pending | bitmap;
1200 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));
1201
1202 if (old_pending)
1203 continue;
1204 }
1205
1206 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1207 }
1208
1209 }
1210
1211 /*
1212 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
1213 */
1214 void
1215 ipi_all(u_int ipi)
1216 {
1217
1218 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1219 ipi_selected(all_cpus, ipi);
1220 return;
1221 }
1222 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1223 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
1224 }
1225
1226 /*
1227 * send an IPI to all CPUs EXCEPT myself
1228 */
1229 void
1230 ipi_all_but_self(u_int ipi)
1231 {
1232
1233 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1234 ipi_selected(PCPU_GET(other_cpus), ipi);
1235 return;
1236 }
1237 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1238 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1239 }
1240
1241 /*
1242 * send an IPI to myself
1243 */
1244 void
1245 ipi_self(u_int ipi)
1246 {
1247
1248 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1249 ipi_selected(PCPU_GET(cpumask), ipi);
1250 return;
1251 }
1252 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1253 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
1254 }
1255
1256 #ifdef STOP_NMI
1257 /*
1258 * send NMI IPI to selected CPUs
1259 */
1260
1261 #define BEFORE_SPIN 1000000
1262
1263 void
1264 ipi_nmi_selected(u_int32_t cpus)
1265 {
1266 int cpu;
1267 register_t icrlo;
1268
1269 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT
1270 | APIC_TRIGMOD_EDGE;
1271
1272 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus);
1273
1274 atomic_set_int(&ipi_nmi_pending, cpus);
1275
1276 while ((cpu = ffs(cpus)) != 0) {
1277 cpu--;
1278 cpus &= ~(1 << cpu);
1279
1280 KASSERT(cpu_apic_ids[cpu] != -1,
1281 ("IPI NMI to non-existent CPU %d", cpu));
1282
1283 /* Wait for an earlier IPI to finish. */
1284 if (!lapic_ipi_wait(BEFORE_SPIN))
1285 panic("ipi_nmi_selected: previous IPI has not cleared");
1286
1287 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]);
1288 }
1289 }
1290
1291 int
1292 ipi_nmi_handler(void)
1293 {
1294 int cpumask = PCPU_GET(cpumask);
1295
1296 if (!(ipi_nmi_pending & cpumask))
1297 return 1;
1298
1299 atomic_clear_int(&ipi_nmi_pending, cpumask);
1300 cpustop_handler();
1301 return 0;
1302 }
1303
1304 #endif /* STOP_NMI */
1305
1306 /*
1307 * Handle an IPI_STOP by saving our current context and spinning until we
1308 * are resumed.
1309 */
1310 void
1311 cpustop_handler(void)
1312 {
1313 int cpu = PCPU_GET(cpuid);
1314 int cpumask = PCPU_GET(cpumask);
1315
1316 savectx(&stoppcbs[cpu]);
1317
1318 /* Indicate that we are stopped */
1319 atomic_set_int(&stopped_cpus, cpumask);
1320
1321 /* Wait for restart */
1322 while (!(started_cpus & cpumask))
1323 ia32_pause();
1324
1325 atomic_clear_int(&started_cpus, cpumask);
1326 atomic_clear_int(&stopped_cpus, cpumask);
1327
1328 if (cpu == 0 && cpustop_restartfunc != NULL) {
1329 cpustop_restartfunc();
1330 cpustop_restartfunc = NULL;
1331 }
1332 }
1333
1334 /*
1335 * This is called once the rest of the system is up and running and we're
1336 * ready to let the AP's out of the pen.
1337 */
1338 static void
1339 release_aps(void *dummy __unused)
1340 {
1341
1342 if (mp_ncpus == 1)
1343 return;
1344 atomic_store_rel_int(&aps_ready, 1);
1345 while (smp_started == 0)
1346 ia32_pause();
1347 }
1348 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1349
1350 static int
1351 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1352 {
1353 u_int mask;
1354 int error;
1355
1356 mask = hlt_cpus_mask;
1357 error = sysctl_handle_int(oidp, &mask, 0, req);
1358 if (error || !req->newptr)
1359 return (error);
1360
1361 if (logical_cpus_mask != 0 &&
1362 (mask & logical_cpus_mask) == logical_cpus_mask)
1363 hlt_logical_cpus = 1;
1364 else
1365 hlt_logical_cpus = 0;
1366
1367 if (! hyperthreading_allowed)
1368 mask |= hyperthreading_cpus_mask;
1369
1370 if ((mask & all_cpus) == all_cpus)
1371 mask &= ~(1<<0);
1372 hlt_cpus_mask = mask;
1373 return (error);
1374 }
1375 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1376 0, 0, sysctl_hlt_cpus, "IU",
1377 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1378
1379 static int
1380 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1381 {
1382 int disable, error;
1383
1384 disable = hlt_logical_cpus;
1385 error = sysctl_handle_int(oidp, &disable, 0, req);
1386 if (error || !req->newptr)
1387 return (error);
1388
1389 if (disable)
1390 hlt_cpus_mask |= logical_cpus_mask;
1391 else
1392 hlt_cpus_mask &= ~logical_cpus_mask;
1393
1394 if (! hyperthreading_allowed)
1395 hlt_cpus_mask |= hyperthreading_cpus_mask;
1396
1397 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1398 hlt_cpus_mask &= ~(1<<0);
1399
1400 hlt_logical_cpus = disable;
1401 return (error);
1402 }
1403
1404 static int
1405 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1406 {
1407 int allowed, error;
1408
1409 allowed = hyperthreading_allowed;
1410 error = sysctl_handle_int(oidp, &allowed, 0, req);
1411 if (error || !req->newptr)
1412 return (error);
1413
1414 if (allowed)
1415 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1416 else
1417 hlt_cpus_mask |= hyperthreading_cpus_mask;
1418
1419 if (logical_cpus_mask != 0 &&
1420 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1421 hlt_logical_cpus = 1;
1422 else
1423 hlt_logical_cpus = 0;
1424
1425 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1426 hlt_cpus_mask &= ~(1<<0);
1427
1428 hyperthreading_allowed = allowed;
1429 return (error);
1430 }
1431
1432 static void
1433 cpu_hlt_setup(void *dummy __unused)
1434 {
1435
1436 if (logical_cpus_mask != 0) {
1437 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1438 &hlt_logical_cpus);
1439 sysctl_ctx_init(&logical_cpu_clist);
1440 SYSCTL_ADD_PROC(&logical_cpu_clist,
1441 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1442 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1443 sysctl_hlt_logical_cpus, "IU", "");
1444 SYSCTL_ADD_UINT(&logical_cpu_clist,
1445 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1446 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1447 &logical_cpus_mask, 0, "");
1448
1449 if (hlt_logical_cpus)
1450 hlt_cpus_mask |= logical_cpus_mask;
1451
1452 /*
1453 * If necessary for security purposes, force
1454 * hyperthreading off, regardless of the value
1455 * of hlt_logical_cpus.
1456 */
1457 if (hyperthreading_cpus_mask) {
1458 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
1459 &hyperthreading_allowed);
1460 SYSCTL_ADD_PROC(&logical_cpu_clist,
1461 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1462 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1463 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1464 if (! hyperthreading_allowed)
1465 hlt_cpus_mask |= hyperthreading_cpus_mask;
1466 }
1467 }
1468 }
1469 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1470
1471 int
1472 mp_grab_cpu_hlt(void)
1473 {
1474 u_int mask = PCPU_GET(cpumask);
1475 #ifdef MP_WATCHDOG
1476 u_int cpuid = PCPU_GET(cpuid);
1477 #endif
1478 int retval;
1479
1480 #ifdef MP_WATCHDOG
1481 ap_watchdog(cpuid);
1482 #endif
1483
1484 retval = mask & hlt_cpus_mask;
1485 while (mask & hlt_cpus_mask)
1486 __asm __volatile("sti; hlt" : : : "memory");
1487 return (retval);
1488 }
1489
1490 #ifdef COUNT_IPIS
1491 /*
1492 * Setup interrupt counters for IPI handlers.
1493 */
1494 static void
1495 mp_ipi_intrcnt(void *dummy)
1496 {
1497 char buf[64];
1498 int i;
1499
1500 for (i = 0; i < mp_maxid; i++) {
1501 if (CPU_ABSENT(i))
1502 continue;
1503 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i);
1504 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1505 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i);
1506 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1507 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i);
1508 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1509 snprintf(buf, sizeof(buf), "cpu%d: preempt", i);
1510 intrcnt_add(buf, &ipi_preempt_counts[i]);
1511 snprintf(buf, sizeof(buf), "cpu%d: ast", i);
1512 intrcnt_add(buf, &ipi_ast_counts[i]);
1513 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i);
1514 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1515 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i);
1516 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1517 }
1518 }
1519 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1520 #endif
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